1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/sysfs.h> 71 #include <linux/types.h> 72 #include <linux/minmax.h> 73 #include <linux/mm.h> 74 #include <linux/cpu.h> 75 #include <linux/kasan.h> 76 #include <linux/percpu.h> 77 78 #include <asm/cpu.h> 79 #include <asm/cpufeature.h> 80 #include <asm/cpu_ops.h> 81 #include <asm/fpsimd.h> 82 #include <asm/hwcap.h> 83 #include <asm/insn.h> 84 #include <asm/kvm_host.h> 85 #include <asm/mmu_context.h> 86 #include <asm/mte.h> 87 #include <asm/processor.h> 88 #include <asm/smp.h> 89 #include <asm/sysreg.h> 90 #include <asm/traps.h> 91 #include <asm/vectors.h> 92 #include <asm/virt.h> 93 94 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 95 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 96 97 #ifdef CONFIG_COMPAT 98 #define COMPAT_ELF_HWCAP_DEFAULT \ 99 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 100 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 101 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 102 COMPAT_HWCAP_LPAE) 103 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 104 unsigned int compat_elf_hwcap2 __read_mostly; 105 #endif 106 107 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 108 EXPORT_SYMBOL(cpu_hwcaps); 109 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 110 111 DECLARE_BITMAP(boot_capabilities, ARM64_NCAPS); 112 113 bool arm64_use_ng_mappings = false; 114 EXPORT_SYMBOL(arm64_use_ng_mappings); 115 116 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 117 118 /* 119 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 120 * support it? 121 */ 122 static bool __read_mostly allow_mismatched_32bit_el0; 123 124 /* 125 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 126 * seen at least one CPU capable of 32-bit EL0. 127 */ 128 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 129 130 /* 131 * Mask of CPUs supporting 32-bit EL0. 132 * Only valid if arm64_mismatched_32bit_el0 is enabled. 133 */ 134 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 135 136 void dump_cpu_features(void) 137 { 138 /* file-wide pr_fmt adds "CPU features: " prefix */ 139 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 140 } 141 142 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 143 { \ 144 .sign = SIGNED, \ 145 .visible = VISIBLE, \ 146 .strict = STRICT, \ 147 .type = TYPE, \ 148 .shift = SHIFT, \ 149 .width = WIDTH, \ 150 .safe_val = SAFE_VAL, \ 151 } 152 153 /* Define a feature with unsigned values */ 154 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 155 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 156 157 /* Define a feature with a signed value */ 158 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 159 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 160 161 #define ARM64_FTR_END \ 162 { \ 163 .width = 0, \ 164 } 165 166 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 167 168 static bool __system_matches_cap(unsigned int n); 169 170 /* 171 * NOTE: Any changes to the visibility of features should be kept in 172 * sync with the documentation of the CPU feature register ABI. 173 */ 174 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 175 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 176 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 182 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 184 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 189 ARM64_FTR_END, 190 }; 191 192 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 199 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 200 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 202 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 207 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 208 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 209 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 211 ARM64_FTR_END, 212 }; 213 214 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 217 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 219 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 222 ARM64_FTR_END, 223 }; 224 225 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 233 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 236 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 237 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 242 ARM64_FTR_END, 243 }; 244 245 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 247 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 253 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 254 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 255 ARM64_FTR_END, 256 }; 257 258 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 259 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 260 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 262 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 263 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 264 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 266 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 268 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 270 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 272 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 276 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 277 ARM64_FTR_END, 278 }; 279 280 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 281 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 282 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 284 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 286 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 287 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 288 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 290 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 291 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 292 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 293 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 294 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 295 ARM64_FTR_END, 296 }; 297 298 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 299 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 302 /* 303 * Page size not being supported at Stage-2 is not fatal. You 304 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 305 * your favourite nesting hypervisor. 306 * 307 * There is a small corner case where the hypervisor explicitly 308 * advertises a given granule size at Stage-2 (value 2) on some 309 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 310 * vCPUs. Although this is not forbidden by the architecture, it 311 * indicates that the hypervisor is being silly (or buggy). 312 * 313 * We make no effort to cope with this and pretend that if these 314 * fields are inconsistent across vCPUs, then it isn't worth 315 * trying to bring KVM up. 316 */ 317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 320 /* 321 * We already refuse to boot CPUs that don't support our configured 322 * page size, so we can only detect mismatches for a page size other 323 * than the one we're currently using. Unfortunately, SoCs like this 324 * exist in the wild so, even though we don't like it, we'll have to go 325 * along with it and treat them as non-strict. 326 */ 327 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 328 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 330 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 332 /* Linux shouldn't care about secure memory */ 333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 336 /* 337 * Differing PARange is fine as long as all peripherals and memory are mapped 338 * within the minimum PARange of all CPUs 339 */ 340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 341 ARM64_FTR_END, 342 }; 343 344 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 345 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 346 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 357 ARM64_FTR_END, 358 }; 359 360 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 361 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 376 ARM64_FTR_END, 377 }; 378 379 static const struct arm64_ftr_bits ftr_ctr[] = { 380 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 381 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 382 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 383 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 384 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 386 /* 387 * Linux can handle differing I-cache policies. Userspace JITs will 388 * make use of *minLine. 389 * If we have differing I-cache policies, report it as the weakest - VIPT. 390 */ 391 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 392 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 393 ARM64_FTR_END, 394 }; 395 396 static struct arm64_ftr_override __ro_after_init no_override = { }; 397 398 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 399 .name = "SYS_CTR_EL0", 400 .ftr_bits = ftr_ctr, 401 .override = &no_override, 402 }; 403 404 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 405 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 410 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 411 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 413 ARM64_FTR_END, 414 }; 415 416 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 417 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 419 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 422 /* 423 * We can instantiate multiple PMU instances with different levels 424 * of support. 425 */ 426 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 428 ARM64_FTR_END, 429 }; 430 431 static const struct arm64_ftr_bits ftr_mvfr2[] = { 432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 434 ARM64_FTR_END, 435 }; 436 437 static const struct arm64_ftr_bits ftr_dczid[] = { 438 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 439 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 440 ARM64_FTR_END, 441 }; 442 443 static const struct arm64_ftr_bits ftr_gmid[] = { 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 445 ARM64_FTR_END, 446 }; 447 448 static const struct arm64_ftr_bits ftr_id_isar0[] = { 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 456 ARM64_FTR_END, 457 }; 458 459 static const struct arm64_ftr_bits ftr_id_isar5[] = { 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 466 ARM64_FTR_END, 467 }; 468 469 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 477 478 /* 479 * SpecSEI = 1 indicates that the PE might generate an SError on an 480 * external abort on speculative read. It is safe to assume that an 481 * SError might be generated than it will not be. Hence it has been 482 * classified as FTR_HIGHER_SAFE. 483 */ 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 485 ARM64_FTR_END, 486 }; 487 488 static const struct arm64_ftr_bits ftr_id_isar4[] = { 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 497 ARM64_FTR_END, 498 }; 499 500 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 502 ARM64_FTR_END, 503 }; 504 505 static const struct arm64_ftr_bits ftr_id_isar6[] = { 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 513 ARM64_FTR_END, 514 }; 515 516 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 522 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 523 ARM64_FTR_END, 524 }; 525 526 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 535 ARM64_FTR_END, 536 }; 537 538 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 541 ARM64_FTR_END, 542 }; 543 544 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 545 /* [31:28] TraceFilt */ 546 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_PERFMON_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 553 ARM64_FTR_END, 554 }; 555 556 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 557 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 558 ARM64_FTR_END, 559 }; 560 561 static const struct arm64_ftr_bits ftr_zcr[] = { 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 563 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0), /* LEN */ 564 ARM64_FTR_END, 565 }; 566 567 static const struct arm64_ftr_bits ftr_smcr[] = { 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 569 SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0), /* LEN */ 570 ARM64_FTR_END, 571 }; 572 573 /* 574 * Common ftr bits for a 32bit register with all hidden, strict 575 * attributes, with 4bit feature fields and a default safe value of 576 * 0. Covers the following 32bit registers: 577 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 578 */ 579 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 581 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 587 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 588 ARM64_FTR_END, 589 }; 590 591 /* Table for a single 32bit feature value */ 592 static const struct arm64_ftr_bits ftr_single32[] = { 593 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 594 ARM64_FTR_END, 595 }; 596 597 static const struct arm64_ftr_bits ftr_raz[] = { 598 ARM64_FTR_END, 599 }; 600 601 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 602 .sys_id = id, \ 603 .reg = &(struct arm64_ftr_reg){ \ 604 .name = id_str, \ 605 .override = (ovr), \ 606 .ftr_bits = &((table)[0]), \ 607 }} 608 609 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 610 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 611 612 #define ARM64_FTR_REG(id, table) \ 613 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 614 615 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 616 struct arm64_ftr_override __ro_after_init id_aa64pfr0_override; 617 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 618 struct arm64_ftr_override __ro_after_init id_aa64zfr0_override; 619 struct arm64_ftr_override __ro_after_init id_aa64smfr0_override; 620 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 621 struct arm64_ftr_override __ro_after_init id_aa64isar2_override; 622 623 static const struct __ftr_reg_entry { 624 u32 sys_id; 625 struct arm64_ftr_reg *reg; 626 } arm64_ftr_regs[] = { 627 628 /* Op1 = 0, CRn = 0, CRm = 1 */ 629 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 630 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 631 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 632 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 633 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 634 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 635 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 636 637 /* Op1 = 0, CRn = 0, CRm = 2 */ 638 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 639 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 640 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 641 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 642 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 643 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 644 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 645 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 646 647 /* Op1 = 0, CRn = 0, CRm = 3 */ 648 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 649 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 650 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 651 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 652 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 653 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 654 655 /* Op1 = 0, CRn = 0, CRm = 4 */ 656 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 657 &id_aa64pfr0_override), 658 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 659 &id_aa64pfr1_override), 660 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 661 &id_aa64zfr0_override), 662 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 663 &id_aa64smfr0_override), 664 665 /* Op1 = 0, CRn = 0, CRm = 5 */ 666 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 667 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 668 669 /* Op1 = 0, CRn = 0, CRm = 6 */ 670 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 671 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 672 &id_aa64isar1_override), 673 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 674 &id_aa64isar2_override), 675 676 /* Op1 = 0, CRn = 0, CRm = 7 */ 677 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 678 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 679 &id_aa64mmfr1_override), 680 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 681 682 /* Op1 = 0, CRn = 1, CRm = 2 */ 683 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 684 ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr), 685 686 /* Op1 = 1, CRn = 0, CRm = 0 */ 687 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 688 689 /* Op1 = 3, CRn = 0, CRm = 0 */ 690 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 691 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 692 693 /* Op1 = 3, CRn = 14, CRm = 0 */ 694 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 695 }; 696 697 static int search_cmp_ftr_reg(const void *id, const void *regp) 698 { 699 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 700 } 701 702 /* 703 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 704 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 705 * ascending order of sys_id, we use binary search to find a matching 706 * entry. 707 * 708 * returns - Upon success, matching ftr_reg entry for id. 709 * - NULL on failure. It is upto the caller to decide 710 * the impact of a failure. 711 */ 712 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 713 { 714 const struct __ftr_reg_entry *ret; 715 716 ret = bsearch((const void *)(unsigned long)sys_id, 717 arm64_ftr_regs, 718 ARRAY_SIZE(arm64_ftr_regs), 719 sizeof(arm64_ftr_regs[0]), 720 search_cmp_ftr_reg); 721 if (ret) 722 return ret->reg; 723 return NULL; 724 } 725 726 /* 727 * get_arm64_ftr_reg - Looks up a feature register entry using 728 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 729 * 730 * returns - Upon success, matching ftr_reg entry for id. 731 * - NULL on failure but with an WARN_ON(). 732 */ 733 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 734 { 735 struct arm64_ftr_reg *reg; 736 737 reg = get_arm64_ftr_reg_nowarn(sys_id); 738 739 /* 740 * Requesting a non-existent register search is an error. Warn 741 * and let the caller handle it. 742 */ 743 WARN_ON(!reg); 744 return reg; 745 } 746 747 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 748 s64 ftr_val) 749 { 750 u64 mask = arm64_ftr_mask(ftrp); 751 752 reg &= ~mask; 753 reg |= (ftr_val << ftrp->shift) & mask; 754 return reg; 755 } 756 757 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 758 s64 cur) 759 { 760 s64 ret = 0; 761 762 switch (ftrp->type) { 763 case FTR_EXACT: 764 ret = ftrp->safe_val; 765 break; 766 case FTR_LOWER_SAFE: 767 ret = min(new, cur); 768 break; 769 case FTR_HIGHER_OR_ZERO_SAFE: 770 if (!cur || !new) 771 break; 772 fallthrough; 773 case FTR_HIGHER_SAFE: 774 ret = max(new, cur); 775 break; 776 default: 777 BUG(); 778 } 779 780 return ret; 781 } 782 783 static void __init sort_ftr_regs(void) 784 { 785 unsigned int i; 786 787 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 788 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 789 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 790 unsigned int j = 0; 791 792 /* 793 * Features here must be sorted in descending order with respect 794 * to their shift values and should not overlap with each other. 795 */ 796 for (; ftr_bits->width != 0; ftr_bits++, j++) { 797 unsigned int width = ftr_reg->ftr_bits[j].width; 798 unsigned int shift = ftr_reg->ftr_bits[j].shift; 799 unsigned int prev_shift; 800 801 WARN((shift + width) > 64, 802 "%s has invalid feature at shift %d\n", 803 ftr_reg->name, shift); 804 805 /* 806 * Skip the first feature. There is nothing to 807 * compare against for now. 808 */ 809 if (j == 0) 810 continue; 811 812 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 813 WARN((shift + width) > prev_shift, 814 "%s has feature overlap at shift %d\n", 815 ftr_reg->name, shift); 816 } 817 818 /* 819 * Skip the first register. There is nothing to 820 * compare against for now. 821 */ 822 if (i == 0) 823 continue; 824 /* 825 * Registers here must be sorted in ascending order with respect 826 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 827 * to work correctly. 828 */ 829 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 830 } 831 } 832 833 /* 834 * Initialise the CPU feature register from Boot CPU values. 835 * Also initiliases the strict_mask for the register. 836 * Any bits that are not covered by an arm64_ftr_bits entry are considered 837 * RES0 for the system-wide value, and must strictly match. 838 */ 839 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 840 { 841 u64 val = 0; 842 u64 strict_mask = ~0x0ULL; 843 u64 user_mask = 0; 844 u64 valid_mask = 0; 845 846 const struct arm64_ftr_bits *ftrp; 847 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 848 849 if (!reg) 850 return; 851 852 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 853 u64 ftr_mask = arm64_ftr_mask(ftrp); 854 s64 ftr_new = arm64_ftr_value(ftrp, new); 855 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 856 857 if ((ftr_mask & reg->override->mask) == ftr_mask) { 858 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 859 char *str = NULL; 860 861 if (ftr_ovr != tmp) { 862 /* Unsafe, remove the override */ 863 reg->override->mask &= ~ftr_mask; 864 reg->override->val &= ~ftr_mask; 865 tmp = ftr_ovr; 866 str = "ignoring override"; 867 } else if (ftr_new != tmp) { 868 /* Override was valid */ 869 ftr_new = tmp; 870 str = "forced"; 871 } else if (ftr_ovr == tmp) { 872 /* Override was the safe value */ 873 str = "already set"; 874 } 875 876 if (str) 877 pr_warn("%s[%d:%d]: %s to %llx\n", 878 reg->name, 879 ftrp->shift + ftrp->width - 1, 880 ftrp->shift, str, tmp); 881 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 882 reg->override->val &= ~ftr_mask; 883 pr_warn("%s[%d:%d]: impossible override, ignored\n", 884 reg->name, 885 ftrp->shift + ftrp->width - 1, 886 ftrp->shift); 887 } 888 889 val = arm64_ftr_set_value(ftrp, val, ftr_new); 890 891 valid_mask |= ftr_mask; 892 if (!ftrp->strict) 893 strict_mask &= ~ftr_mask; 894 if (ftrp->visible) 895 user_mask |= ftr_mask; 896 else 897 reg->user_val = arm64_ftr_set_value(ftrp, 898 reg->user_val, 899 ftrp->safe_val); 900 } 901 902 val &= valid_mask; 903 904 reg->sys_val = val; 905 reg->strict_mask = strict_mask; 906 reg->user_mask = user_mask; 907 } 908 909 extern const struct arm64_cpu_capabilities arm64_errata[]; 910 static const struct arm64_cpu_capabilities arm64_features[]; 911 912 static void __init 913 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 914 { 915 for (; caps->matches; caps++) { 916 if (WARN(caps->capability >= ARM64_NCAPS, 917 "Invalid capability %d\n", caps->capability)) 918 continue; 919 if (WARN(cpu_hwcaps_ptrs[caps->capability], 920 "Duplicate entry for capability %d\n", 921 caps->capability)) 922 continue; 923 cpu_hwcaps_ptrs[caps->capability] = caps; 924 } 925 } 926 927 static void __init init_cpu_hwcaps_indirect_list(void) 928 { 929 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 930 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 931 } 932 933 static void __init setup_boot_cpu_capabilities(void); 934 935 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 936 { 937 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 938 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 939 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 940 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 941 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 942 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 943 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 944 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 945 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 946 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 947 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 948 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 949 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 950 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 951 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 952 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 953 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 954 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 955 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 956 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 957 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 958 } 959 960 void __init init_cpu_features(struct cpuinfo_arm64 *info) 961 { 962 /* Before we start using the tables, make sure it is sorted */ 963 sort_ftr_regs(); 964 965 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 966 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 967 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 968 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 969 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 970 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 971 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 972 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 973 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 974 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 975 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 976 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 977 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 978 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 979 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 980 981 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 982 init_32bit_cpu_features(&info->aarch32); 983 984 if (IS_ENABLED(CONFIG_ARM64_SVE) && 985 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 986 info->reg_zcr = read_zcr_features(); 987 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 988 vec_init_vq_map(ARM64_VEC_SVE); 989 } 990 991 if (IS_ENABLED(CONFIG_ARM64_SME) && 992 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 993 info->reg_smcr = read_smcr_features(); 994 /* 995 * We mask out SMPS since even if the hardware 996 * supports priorities the kernel does not at present 997 * and we block access to them. 998 */ 999 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1000 init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr); 1001 vec_init_vq_map(ARM64_VEC_SME); 1002 } 1003 1004 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1005 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1006 1007 /* 1008 * Initialize the indirect array of CPU hwcaps capabilities pointers 1009 * before we handle the boot CPU below. 1010 */ 1011 init_cpu_hwcaps_indirect_list(); 1012 1013 /* 1014 * Detect and enable early CPU capabilities based on the boot CPU, 1015 * after we have initialised the CPU feature infrastructure. 1016 */ 1017 setup_boot_cpu_capabilities(); 1018 } 1019 1020 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1021 { 1022 const struct arm64_ftr_bits *ftrp; 1023 1024 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1025 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1026 s64 ftr_new = arm64_ftr_value(ftrp, new); 1027 1028 if (ftr_cur == ftr_new) 1029 continue; 1030 /* Find a safe value */ 1031 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1032 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1033 } 1034 1035 } 1036 1037 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1038 { 1039 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1040 1041 if (!regp) 1042 return 0; 1043 1044 update_cpu_ftr_reg(regp, val); 1045 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1046 return 0; 1047 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1048 regp->name, boot, cpu, val); 1049 return 1; 1050 } 1051 1052 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1053 { 1054 const struct arm64_ftr_bits *ftrp; 1055 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1056 1057 if (!regp) 1058 return; 1059 1060 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1061 if (ftrp->shift == field) { 1062 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1063 break; 1064 } 1065 } 1066 1067 /* Bogus field? */ 1068 WARN_ON(!ftrp->width); 1069 } 1070 1071 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1072 struct cpuinfo_arm64 *boot) 1073 { 1074 static bool boot_cpu_32bit_regs_overridden = false; 1075 1076 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1077 return; 1078 1079 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1080 return; 1081 1082 boot->aarch32 = info->aarch32; 1083 init_32bit_cpu_features(&boot->aarch32); 1084 boot_cpu_32bit_regs_overridden = true; 1085 } 1086 1087 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1088 struct cpuinfo_32bit *boot) 1089 { 1090 int taint = 0; 1091 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1092 1093 /* 1094 * If we don't have AArch32 at EL1, then relax the strictness of 1095 * EL1-dependent register fields to avoid spurious sanity check fails. 1096 */ 1097 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1098 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 1099 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 1100 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 1101 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 1102 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 1103 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 1104 } 1105 1106 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1107 info->reg_id_dfr0, boot->reg_id_dfr0); 1108 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1109 info->reg_id_dfr1, boot->reg_id_dfr1); 1110 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1111 info->reg_id_isar0, boot->reg_id_isar0); 1112 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1113 info->reg_id_isar1, boot->reg_id_isar1); 1114 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1115 info->reg_id_isar2, boot->reg_id_isar2); 1116 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1117 info->reg_id_isar3, boot->reg_id_isar3); 1118 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1119 info->reg_id_isar4, boot->reg_id_isar4); 1120 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1121 info->reg_id_isar5, boot->reg_id_isar5); 1122 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1123 info->reg_id_isar6, boot->reg_id_isar6); 1124 1125 /* 1126 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1127 * ACTLR formats could differ across CPUs and therefore would have to 1128 * be trapped for virtualization anyway. 1129 */ 1130 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1131 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1132 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1133 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1134 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1135 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1136 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1137 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1138 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1139 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1140 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1141 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1142 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1143 info->reg_id_pfr0, boot->reg_id_pfr0); 1144 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1145 info->reg_id_pfr1, boot->reg_id_pfr1); 1146 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1147 info->reg_id_pfr2, boot->reg_id_pfr2); 1148 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1149 info->reg_mvfr0, boot->reg_mvfr0); 1150 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1151 info->reg_mvfr1, boot->reg_mvfr1); 1152 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1153 info->reg_mvfr2, boot->reg_mvfr2); 1154 1155 return taint; 1156 } 1157 1158 /* 1159 * Update system wide CPU feature registers with the values from a 1160 * non-boot CPU. Also performs SANITY checks to make sure that there 1161 * aren't any insane variations from that of the boot CPU. 1162 */ 1163 void update_cpu_features(int cpu, 1164 struct cpuinfo_arm64 *info, 1165 struct cpuinfo_arm64 *boot) 1166 { 1167 int taint = 0; 1168 1169 /* 1170 * The kernel can handle differing I-cache policies, but otherwise 1171 * caches should look identical. Userspace JITs will make use of 1172 * *minLine. 1173 */ 1174 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1175 info->reg_ctr, boot->reg_ctr); 1176 1177 /* 1178 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1179 * could result in too much or too little memory being zeroed if a 1180 * process is preempted and migrated between CPUs. 1181 */ 1182 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1183 info->reg_dczid, boot->reg_dczid); 1184 1185 /* If different, timekeeping will be broken (especially with KVM) */ 1186 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1187 info->reg_cntfrq, boot->reg_cntfrq); 1188 1189 /* 1190 * The kernel uses self-hosted debug features and expects CPUs to 1191 * support identical debug features. We presently need CTX_CMPs, WRPs, 1192 * and BRPs to be identical. 1193 * ID_AA64DFR1 is currently RES0. 1194 */ 1195 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1196 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1197 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1198 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1199 /* 1200 * Even in big.LITTLE, processors should be identical instruction-set 1201 * wise. 1202 */ 1203 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1204 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1205 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1206 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1207 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1208 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1209 1210 /* 1211 * Differing PARange support is fine as long as all peripherals and 1212 * memory are mapped within the minimum PARange of all CPUs. 1213 * Linux should not care about secure memory. 1214 */ 1215 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1216 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1217 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1218 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1219 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1220 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1221 1222 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1223 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1224 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1225 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1226 1227 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1228 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1229 1230 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1231 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1232 1233 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1234 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1235 info->reg_zcr = read_zcr_features(); 1236 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1237 info->reg_zcr, boot->reg_zcr); 1238 1239 /* Probe vector lengths */ 1240 if (!system_capabilities_finalized()) 1241 vec_update_vq_map(ARM64_VEC_SVE); 1242 } 1243 1244 if (IS_ENABLED(CONFIG_ARM64_SME) && 1245 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1246 info->reg_smcr = read_smcr_features(); 1247 /* 1248 * We mask out SMPS since even if the hardware 1249 * supports priorities the kernel does not at present 1250 * and we block access to them. 1251 */ 1252 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1253 taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu, 1254 info->reg_smcr, boot->reg_smcr); 1255 1256 /* Probe vector lengths */ 1257 if (!system_capabilities_finalized()) 1258 vec_update_vq_map(ARM64_VEC_SME); 1259 } 1260 1261 /* 1262 * The kernel uses the LDGM/STGM instructions and the number of tags 1263 * they read/write depends on the GMID_EL1.BS field. Check that the 1264 * value is the same on all CPUs. 1265 */ 1266 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1267 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1268 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1269 info->reg_gmid, boot->reg_gmid); 1270 } 1271 1272 /* 1273 * If we don't have AArch32 at all then skip the checks entirely 1274 * as the register values may be UNKNOWN and we're not going to be 1275 * using them for anything. 1276 * 1277 * This relies on a sanitised view of the AArch64 ID registers 1278 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1279 */ 1280 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1281 lazy_init_32bit_cpu_features(info, boot); 1282 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1283 &boot->aarch32); 1284 } 1285 1286 /* 1287 * Mismatched CPU features are a recipe for disaster. Don't even 1288 * pretend to support them. 1289 */ 1290 if (taint) { 1291 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1292 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1293 } 1294 } 1295 1296 u64 read_sanitised_ftr_reg(u32 id) 1297 { 1298 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1299 1300 if (!regp) 1301 return 0; 1302 return regp->sys_val; 1303 } 1304 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1305 1306 #define read_sysreg_case(r) \ 1307 case r: val = read_sysreg_s(r); break; 1308 1309 /* 1310 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1311 * Read the system register on the current CPU 1312 */ 1313 u64 __read_sysreg_by_encoding(u32 sys_id) 1314 { 1315 struct arm64_ftr_reg *regp; 1316 u64 val; 1317 1318 switch (sys_id) { 1319 read_sysreg_case(SYS_ID_PFR0_EL1); 1320 read_sysreg_case(SYS_ID_PFR1_EL1); 1321 read_sysreg_case(SYS_ID_PFR2_EL1); 1322 read_sysreg_case(SYS_ID_DFR0_EL1); 1323 read_sysreg_case(SYS_ID_DFR1_EL1); 1324 read_sysreg_case(SYS_ID_MMFR0_EL1); 1325 read_sysreg_case(SYS_ID_MMFR1_EL1); 1326 read_sysreg_case(SYS_ID_MMFR2_EL1); 1327 read_sysreg_case(SYS_ID_MMFR3_EL1); 1328 read_sysreg_case(SYS_ID_MMFR4_EL1); 1329 read_sysreg_case(SYS_ID_MMFR5_EL1); 1330 read_sysreg_case(SYS_ID_ISAR0_EL1); 1331 read_sysreg_case(SYS_ID_ISAR1_EL1); 1332 read_sysreg_case(SYS_ID_ISAR2_EL1); 1333 read_sysreg_case(SYS_ID_ISAR3_EL1); 1334 read_sysreg_case(SYS_ID_ISAR4_EL1); 1335 read_sysreg_case(SYS_ID_ISAR5_EL1); 1336 read_sysreg_case(SYS_ID_ISAR6_EL1); 1337 read_sysreg_case(SYS_MVFR0_EL1); 1338 read_sysreg_case(SYS_MVFR1_EL1); 1339 read_sysreg_case(SYS_MVFR2_EL1); 1340 1341 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1342 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1343 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1344 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1345 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1346 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1347 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1348 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1349 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1350 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1351 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1352 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1353 1354 read_sysreg_case(SYS_CNTFRQ_EL0); 1355 read_sysreg_case(SYS_CTR_EL0); 1356 read_sysreg_case(SYS_DCZID_EL0); 1357 1358 default: 1359 BUG(); 1360 return 0; 1361 } 1362 1363 regp = get_arm64_ftr_reg(sys_id); 1364 if (regp) { 1365 val &= ~regp->override->mask; 1366 val |= (regp->override->val & regp->override->mask); 1367 } 1368 1369 return val; 1370 } 1371 1372 #include <linux/irqchip/arm-gic-v3.h> 1373 1374 static bool 1375 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1376 { 1377 return true; 1378 } 1379 1380 static bool 1381 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1382 { 1383 int val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1384 entry->field_width, 1385 entry->sign); 1386 1387 return val >= entry->min_field_value; 1388 } 1389 1390 static u64 1391 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1392 { 1393 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1394 if (scope == SCOPE_SYSTEM) 1395 return read_sanitised_ftr_reg(entry->sys_reg); 1396 else 1397 return __read_sysreg_by_encoding(entry->sys_reg); 1398 } 1399 1400 static bool 1401 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1402 { 1403 int mask; 1404 struct arm64_ftr_reg *regp; 1405 u64 val = read_scoped_sysreg(entry, scope); 1406 1407 regp = get_arm64_ftr_reg(entry->sys_reg); 1408 if (!regp) 1409 return false; 1410 1411 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1412 entry->field_pos, 1413 entry->field_width); 1414 if (!mask) 1415 return false; 1416 1417 return feature_matches(val, entry); 1418 } 1419 1420 static bool 1421 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1422 { 1423 u64 val = read_scoped_sysreg(entry, scope); 1424 return feature_matches(val, entry); 1425 } 1426 1427 const struct cpumask *system_32bit_el0_cpumask(void) 1428 { 1429 if (!system_supports_32bit_el0()) 1430 return cpu_none_mask; 1431 1432 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1433 return cpu_32bit_el0_mask; 1434 1435 return cpu_possible_mask; 1436 } 1437 1438 static int __init parse_32bit_el0_param(char *str) 1439 { 1440 allow_mismatched_32bit_el0 = true; 1441 return 0; 1442 } 1443 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1444 1445 static ssize_t aarch32_el0_show(struct device *dev, 1446 struct device_attribute *attr, char *buf) 1447 { 1448 const struct cpumask *mask = system_32bit_el0_cpumask(); 1449 1450 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1451 } 1452 static const DEVICE_ATTR_RO(aarch32_el0); 1453 1454 static int __init aarch32_el0_sysfs_init(void) 1455 { 1456 if (!allow_mismatched_32bit_el0) 1457 return 0; 1458 1459 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0); 1460 } 1461 device_initcall(aarch32_el0_sysfs_init); 1462 1463 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1464 { 1465 if (!has_cpuid_feature(entry, scope)) 1466 return allow_mismatched_32bit_el0; 1467 1468 if (scope == SCOPE_SYSTEM) 1469 pr_info("detected: 32-bit EL0 Support\n"); 1470 1471 return true; 1472 } 1473 1474 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1475 { 1476 bool has_sre; 1477 1478 if (!has_cpuid_feature(entry, scope)) 1479 return false; 1480 1481 has_sre = gic_enable_sre(); 1482 if (!has_sre) 1483 pr_warn_once("%s present but disabled by higher exception level\n", 1484 entry->desc); 1485 1486 return has_sre; 1487 } 1488 1489 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1490 { 1491 u32 midr = read_cpuid_id(); 1492 1493 /* Cavium ThunderX pass 1.x and 2.x */ 1494 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1495 MIDR_CPU_VAR_REV(0, 0), 1496 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1497 } 1498 1499 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1500 { 1501 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1502 1503 return cpuid_feature_extract_signed_field(pfr0, 1504 ID_AA64PFR0_EL1_FP_SHIFT) < 0; 1505 } 1506 1507 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1508 int scope) 1509 { 1510 u64 ctr; 1511 1512 if (scope == SCOPE_SYSTEM) 1513 ctr = arm64_ftr_reg_ctrel0.sys_val; 1514 else 1515 ctr = read_cpuid_effective_cachetype(); 1516 1517 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1518 } 1519 1520 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1521 { 1522 /* 1523 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1524 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1525 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1526 * value. 1527 */ 1528 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1529 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1530 } 1531 1532 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1533 int scope) 1534 { 1535 u64 ctr; 1536 1537 if (scope == SCOPE_SYSTEM) 1538 ctr = arm64_ftr_reg_ctrel0.sys_val; 1539 else 1540 ctr = read_cpuid_cachetype(); 1541 1542 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1543 } 1544 1545 static bool __maybe_unused 1546 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1547 { 1548 /* 1549 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1550 * may share TLB entries with a CPU stuck in the crashed 1551 * kernel. 1552 */ 1553 if (is_kdump_kernel()) 1554 return false; 1555 1556 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1557 return false; 1558 1559 return has_cpuid_feature(entry, scope); 1560 } 1561 1562 /* 1563 * This check is triggered during the early boot before the cpufeature 1564 * is initialised. Checking the status on the local CPU allows the boot 1565 * CPU to detect the need for non-global mappings and thus avoiding a 1566 * pagetable re-write after all the CPUs are booted. This check will be 1567 * anyway run on individual CPUs, allowing us to get the consistent 1568 * state once the SMP CPUs are up and thus make the switch to non-global 1569 * mappings if required. 1570 */ 1571 bool kaslr_requires_kpti(void) 1572 { 1573 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1574 return false; 1575 1576 /* 1577 * E0PD does a similar job to KPTI so can be used instead 1578 * where available. 1579 */ 1580 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1581 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1582 if (cpuid_feature_extract_unsigned_field(mmfr2, 1583 ID_AA64MMFR2_EL1_E0PD_SHIFT)) 1584 return false; 1585 } 1586 1587 /* 1588 * Systems affected by Cavium erratum 24756 are incompatible 1589 * with KPTI. 1590 */ 1591 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1592 extern const struct midr_range cavium_erratum_27456_cpus[]; 1593 1594 if (is_midr_in_range_list(read_cpuid_id(), 1595 cavium_erratum_27456_cpus)) 1596 return false; 1597 } 1598 1599 return kaslr_offset() > 0; 1600 } 1601 1602 static bool __meltdown_safe = true; 1603 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1604 1605 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1606 int scope) 1607 { 1608 /* List of CPUs that are not vulnerable and don't need KPTI */ 1609 static const struct midr_range kpti_safe_list[] = { 1610 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1611 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1612 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1613 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1614 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1615 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1616 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1617 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1618 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1619 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1620 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1621 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1622 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1623 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1624 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1625 { /* sentinel */ } 1626 }; 1627 char const *str = "kpti command line option"; 1628 bool meltdown_safe; 1629 1630 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1631 1632 /* Defer to CPU feature registers */ 1633 if (has_cpuid_feature(entry, scope)) 1634 meltdown_safe = true; 1635 1636 if (!meltdown_safe) 1637 __meltdown_safe = false; 1638 1639 /* 1640 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1641 * ThunderX leads to apparent I-cache corruption of kernel text, which 1642 * ends as well as you might imagine. Don't even try. We cannot rely 1643 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1644 * because cpucap detection order may change. However, since we know 1645 * affected CPUs are always in a homogeneous configuration, it is 1646 * safe to rely on this_cpu_has_cap() here. 1647 */ 1648 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1649 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1650 __kpti_forced = -1; 1651 } 1652 1653 /* Useful for KASLR robustness */ 1654 if (kaslr_requires_kpti()) { 1655 if (!__kpti_forced) { 1656 str = "KASLR"; 1657 __kpti_forced = 1; 1658 } 1659 } 1660 1661 if (cpu_mitigations_off() && !__kpti_forced) { 1662 str = "mitigations=off"; 1663 __kpti_forced = -1; 1664 } 1665 1666 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1667 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1668 return false; 1669 } 1670 1671 /* Forced? */ 1672 if (__kpti_forced) { 1673 pr_info_once("kernel page table isolation forced %s by %s\n", 1674 __kpti_forced > 0 ? "ON" : "OFF", str); 1675 return __kpti_forced > 0; 1676 } 1677 1678 return !meltdown_safe; 1679 } 1680 1681 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1682 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1683 1684 extern 1685 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1686 phys_addr_t size, pgprot_t prot, 1687 phys_addr_t (*pgtable_alloc)(int), int flags); 1688 1689 static phys_addr_t kpti_ng_temp_alloc; 1690 1691 static phys_addr_t kpti_ng_pgd_alloc(int shift) 1692 { 1693 kpti_ng_temp_alloc -= PAGE_SIZE; 1694 return kpti_ng_temp_alloc; 1695 } 1696 1697 static void 1698 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1699 { 1700 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1701 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1702 kpti_remap_fn *remap_fn; 1703 1704 int cpu = smp_processor_id(); 1705 int levels = CONFIG_PGTABLE_LEVELS; 1706 int order = order_base_2(levels); 1707 u64 kpti_ng_temp_pgd_pa = 0; 1708 pgd_t *kpti_ng_temp_pgd; 1709 u64 alloc = 0; 1710 1711 if (__this_cpu_read(this_cpu_vector) == vectors) { 1712 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1713 1714 __this_cpu_write(this_cpu_vector, v); 1715 } 1716 1717 /* 1718 * We don't need to rewrite the page-tables if either we've done 1719 * it already or we have KASLR enabled and therefore have not 1720 * created any global mappings at all. 1721 */ 1722 if (arm64_use_ng_mappings) 1723 return; 1724 1725 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1726 1727 if (!cpu) { 1728 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1729 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1730 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1731 1732 // 1733 // Create a minimal page table hierarchy that permits us to map 1734 // the swapper page tables temporarily as we traverse them. 1735 // 1736 // The physical pages are laid out as follows: 1737 // 1738 // +--------+-/-------+-/------ +-\\--------+ 1739 // : PTE[] : | PMD[] : | PUD[] : || PGD[] : 1740 // +--------+-\-------+-\------ +-//--------+ 1741 // ^ 1742 // The first page is mapped into this hierarchy at a PMD_SHIFT 1743 // aligned virtual address, so that we can manipulate the PTE 1744 // level entries while the mapping is active. The first entry 1745 // covers the PTE[] page itself, the remaining entries are free 1746 // to be used as a ad-hoc fixmap. 1747 // 1748 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1749 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1750 kpti_ng_pgd_alloc, 0); 1751 } 1752 1753 cpu_install_idmap(); 1754 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1755 cpu_uninstall_idmap(); 1756 1757 if (!cpu) { 1758 free_pages(alloc, order); 1759 arm64_use_ng_mappings = true; 1760 } 1761 } 1762 #else 1763 static void 1764 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1765 { 1766 } 1767 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1768 1769 static int __init parse_kpti(char *str) 1770 { 1771 bool enabled; 1772 int ret = strtobool(str, &enabled); 1773 1774 if (ret) 1775 return ret; 1776 1777 __kpti_forced = enabled ? 1 : -1; 1778 return 0; 1779 } 1780 early_param("kpti", parse_kpti); 1781 1782 #ifdef CONFIG_ARM64_HW_AFDBM 1783 static inline void __cpu_enable_hw_dbm(void) 1784 { 1785 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1786 1787 write_sysreg(tcr, tcr_el1); 1788 isb(); 1789 local_flush_tlb_all(); 1790 } 1791 1792 static bool cpu_has_broken_dbm(void) 1793 { 1794 /* List of CPUs which have broken DBM support. */ 1795 static const struct midr_range cpus[] = { 1796 #ifdef CONFIG_ARM64_ERRATUM_1024718 1797 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1798 /* Kryo4xx Silver (rdpe => r1p0) */ 1799 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1800 #endif 1801 #ifdef CONFIG_ARM64_ERRATUM_2051678 1802 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1803 #endif 1804 {}, 1805 }; 1806 1807 return is_midr_in_range_list(read_cpuid_id(), cpus); 1808 } 1809 1810 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1811 { 1812 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1813 !cpu_has_broken_dbm(); 1814 } 1815 1816 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1817 { 1818 if (cpu_can_use_dbm(cap)) 1819 __cpu_enable_hw_dbm(); 1820 } 1821 1822 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1823 int __unused) 1824 { 1825 static bool detected = false; 1826 /* 1827 * DBM is a non-conflicting feature. i.e, the kernel can safely 1828 * run a mix of CPUs with and without the feature. So, we 1829 * unconditionally enable the capability to allow any late CPU 1830 * to use the feature. We only enable the control bits on the 1831 * CPU, if it actually supports. 1832 * 1833 * We have to make sure we print the "feature" detection only 1834 * when at least one CPU actually uses it. So check if this CPU 1835 * can actually use it and print the message exactly once. 1836 * 1837 * This is safe as all CPUs (including secondary CPUs - due to the 1838 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1839 * goes through the "matches" check exactly once. Also if a CPU 1840 * matches the criteria, it is guaranteed that the CPU will turn 1841 * the DBM on, as the capability is unconditionally enabled. 1842 */ 1843 if (!detected && cpu_can_use_dbm(cap)) { 1844 detected = true; 1845 pr_info("detected: Hardware dirty bit management\n"); 1846 } 1847 1848 return true; 1849 } 1850 1851 #endif 1852 1853 #ifdef CONFIG_ARM64_AMU_EXTN 1854 1855 /* 1856 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1857 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1858 * information regarding all the events that it supports. When a CPU bit is 1859 * set in the cpumask, the user of this feature can only rely on the presence 1860 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1861 * counters are enabled or access to these counters is enabled by code 1862 * executed at higher exception levels (firmware). 1863 */ 1864 static struct cpumask amu_cpus __read_mostly; 1865 1866 bool cpu_has_amu_feat(int cpu) 1867 { 1868 return cpumask_test_cpu(cpu, &amu_cpus); 1869 } 1870 1871 int get_cpu_with_amu_feat(void) 1872 { 1873 return cpumask_any(&amu_cpus); 1874 } 1875 1876 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1877 { 1878 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1879 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1880 smp_processor_id()); 1881 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1882 1883 /* 0 reference values signal broken/disabled counters */ 1884 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 1885 update_freq_counters_refs(); 1886 } 1887 } 1888 1889 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1890 int __unused) 1891 { 1892 /* 1893 * The AMU extension is a non-conflicting feature: the kernel can 1894 * safely run a mix of CPUs with and without support for the 1895 * activity monitors extension. Therefore, unconditionally enable 1896 * the capability to allow any late CPU to use the feature. 1897 * 1898 * With this feature unconditionally enabled, the cpu_enable 1899 * function will be called for all CPUs that match the criteria, 1900 * including secondary and hotplugged, marking this feature as 1901 * present on that respective CPU. The enable function will also 1902 * print a detection message. 1903 */ 1904 1905 return true; 1906 } 1907 #else 1908 int get_cpu_with_amu_feat(void) 1909 { 1910 return nr_cpu_ids; 1911 } 1912 #endif 1913 1914 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1915 { 1916 return is_kernel_in_hyp_mode(); 1917 } 1918 1919 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1920 { 1921 /* 1922 * Copy register values that aren't redirected by hardware. 1923 * 1924 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1925 * this value to tpidr_el2 before we patch the code. Once we've done 1926 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1927 * do anything here. 1928 */ 1929 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1930 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1931 } 1932 1933 #ifdef CONFIG_ARM64_PAN 1934 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1935 { 1936 /* 1937 * We modify PSTATE. This won't work from irq context as the PSTATE 1938 * is discarded once we return from the exception. 1939 */ 1940 WARN_ON_ONCE(in_interrupt()); 1941 1942 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1943 set_pstate_pan(1); 1944 } 1945 #endif /* CONFIG_ARM64_PAN */ 1946 1947 #ifdef CONFIG_ARM64_RAS_EXTN 1948 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1949 { 1950 /* Firmware may have left a deferred SError in this register. */ 1951 write_sysreg_s(0, SYS_DISR_EL1); 1952 } 1953 #endif /* CONFIG_ARM64_RAS_EXTN */ 1954 1955 #ifdef CONFIG_ARM64_PTR_AUTH 1956 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1957 { 1958 int boot_val, sec_val; 1959 1960 /* We don't expect to be called with SCOPE_SYSTEM */ 1961 WARN_ON(scope == SCOPE_SYSTEM); 1962 /* 1963 * The ptr-auth feature levels are not intercompatible with lower 1964 * levels. Hence we must match ptr-auth feature level of the secondary 1965 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1966 * from the sanitised register whereas direct register read is done for 1967 * the secondary CPUs. 1968 * The sanitised feature state is guaranteed to match that of the 1969 * boot CPU as a mismatched secondary CPU is parked before it gets 1970 * a chance to update the state, with the capability. 1971 */ 1972 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1973 entry->field_pos, entry->sign); 1974 if (scope & SCOPE_BOOT_CPU) 1975 return boot_val >= entry->min_field_value; 1976 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 1977 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 1978 entry->field_pos, entry->sign); 1979 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 1980 } 1981 1982 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 1983 int scope) 1984 { 1985 bool api = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 1986 bool apa = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 1987 bool apa3 = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 1988 1989 return apa || apa3 || api; 1990 } 1991 1992 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1993 int __unused) 1994 { 1995 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1996 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 1997 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 1998 1999 return gpa || gpa3 || gpi; 2000 } 2001 #endif /* CONFIG_ARM64_PTR_AUTH */ 2002 2003 #ifdef CONFIG_ARM64_E0PD 2004 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2005 { 2006 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2007 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2008 } 2009 #endif /* CONFIG_ARM64_E0PD */ 2010 2011 #ifdef CONFIG_ARM64_PSEUDO_NMI 2012 static bool enable_pseudo_nmi; 2013 2014 static int __init early_enable_pseudo_nmi(char *p) 2015 { 2016 return strtobool(p, &enable_pseudo_nmi); 2017 } 2018 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 2019 2020 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2021 int scope) 2022 { 2023 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 2024 } 2025 #endif 2026 2027 #ifdef CONFIG_ARM64_BTI 2028 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2029 { 2030 /* 2031 * Use of X16/X17 for tail-calls and trampolines that jump to 2032 * function entry points using BR is a requirement for 2033 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2034 * So, be strict and forbid other BRs using other registers to 2035 * jump onto a PACIxSP instruction: 2036 */ 2037 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2038 isb(); 2039 } 2040 #endif /* CONFIG_ARM64_BTI */ 2041 2042 #ifdef CONFIG_ARM64_MTE 2043 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2044 { 2045 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2046 2047 mte_cpu_setup(); 2048 2049 /* 2050 * Clear the tags in the zero page. This needs to be done via the 2051 * linear map which has the Tagged attribute. 2052 */ 2053 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) 2054 mte_clear_page_tags(lm_alias(empty_zero_page)); 2055 2056 kasan_init_hw_tags_cpu(); 2057 } 2058 #endif /* CONFIG_ARM64_MTE */ 2059 2060 static void elf_hwcap_fixup(void) 2061 { 2062 #ifdef CONFIG_ARM64_ERRATUM_1742098 2063 if (cpus_have_const_cap(ARM64_WORKAROUND_1742098)) 2064 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2065 #endif /* ARM64_ERRATUM_1742098 */ 2066 } 2067 2068 #ifdef CONFIG_KVM 2069 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2070 { 2071 return kvm_get_mode() == KVM_MODE_PROTECTED; 2072 } 2073 #endif /* CONFIG_KVM */ 2074 2075 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2076 { 2077 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2078 } 2079 2080 /* Internal helper functions to match cpu capability type */ 2081 static bool 2082 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2083 { 2084 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2085 } 2086 2087 static bool 2088 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2089 { 2090 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2091 } 2092 2093 static bool 2094 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2095 { 2096 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2097 } 2098 2099 static const struct arm64_cpu_capabilities arm64_features[] = { 2100 { 2101 .capability = ARM64_ALWAYS_BOOT, 2102 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2103 .matches = has_always, 2104 }, 2105 { 2106 .capability = ARM64_ALWAYS_SYSTEM, 2107 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2108 .matches = has_always, 2109 }, 2110 { 2111 .desc = "GIC system register CPU interface", 2112 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 2113 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2114 .matches = has_useable_gicv3_cpuif, 2115 .sys_reg = SYS_ID_AA64PFR0_EL1, 2116 .field_pos = ID_AA64PFR0_EL1_GIC_SHIFT, 2117 .field_width = 4, 2118 .sign = FTR_UNSIGNED, 2119 .min_field_value = 1, 2120 }, 2121 { 2122 .desc = "Enhanced Counter Virtualization", 2123 .capability = ARM64_HAS_ECV, 2124 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2125 .matches = has_cpuid_feature, 2126 .sys_reg = SYS_ID_AA64MMFR0_EL1, 2127 .field_pos = ID_AA64MMFR0_EL1_ECV_SHIFT, 2128 .field_width = 4, 2129 .sign = FTR_UNSIGNED, 2130 .min_field_value = 1, 2131 }, 2132 #ifdef CONFIG_ARM64_PAN 2133 { 2134 .desc = "Privileged Access Never", 2135 .capability = ARM64_HAS_PAN, 2136 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2137 .matches = has_cpuid_feature, 2138 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2139 .field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT, 2140 .field_width = 4, 2141 .sign = FTR_UNSIGNED, 2142 .min_field_value = 1, 2143 .cpu_enable = cpu_enable_pan, 2144 }, 2145 #endif /* CONFIG_ARM64_PAN */ 2146 #ifdef CONFIG_ARM64_EPAN 2147 { 2148 .desc = "Enhanced Privileged Access Never", 2149 .capability = ARM64_HAS_EPAN, 2150 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2151 .matches = has_cpuid_feature, 2152 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2153 .field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT, 2154 .field_width = 4, 2155 .sign = FTR_UNSIGNED, 2156 .min_field_value = 3, 2157 }, 2158 #endif /* CONFIG_ARM64_EPAN */ 2159 #ifdef CONFIG_ARM64_LSE_ATOMICS 2160 { 2161 .desc = "LSE atomic instructions", 2162 .capability = ARM64_HAS_LSE_ATOMICS, 2163 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2164 .matches = has_cpuid_feature, 2165 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2166 .field_pos = ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 2167 .field_width = 4, 2168 .sign = FTR_UNSIGNED, 2169 .min_field_value = 2, 2170 }, 2171 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2172 { 2173 .desc = "Software prefetching using PRFM", 2174 .capability = ARM64_HAS_NO_HW_PREFETCH, 2175 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2176 .matches = has_no_hw_prefetch, 2177 }, 2178 { 2179 .desc = "Virtualization Host Extensions", 2180 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2181 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2182 .matches = runs_at_el2, 2183 .cpu_enable = cpu_copy_el2regs, 2184 }, 2185 { 2186 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2187 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2188 .matches = has_32bit_el0, 2189 .sys_reg = SYS_ID_AA64PFR0_EL1, 2190 .sign = FTR_UNSIGNED, 2191 .field_pos = ID_AA64PFR0_EL1_EL0_SHIFT, 2192 .field_width = 4, 2193 .min_field_value = ID_AA64PFR0_EL1_ELx_32BIT_64BIT, 2194 }, 2195 #ifdef CONFIG_KVM 2196 { 2197 .desc = "32-bit EL1 Support", 2198 .capability = ARM64_HAS_32BIT_EL1, 2199 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2200 .matches = has_cpuid_feature, 2201 .sys_reg = SYS_ID_AA64PFR0_EL1, 2202 .sign = FTR_UNSIGNED, 2203 .field_pos = ID_AA64PFR0_EL1_EL1_SHIFT, 2204 .field_width = 4, 2205 .min_field_value = ID_AA64PFR0_EL1_ELx_32BIT_64BIT, 2206 }, 2207 { 2208 .desc = "Protected KVM", 2209 .capability = ARM64_KVM_PROTECTED_MODE, 2210 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2211 .matches = is_kvm_protected_mode, 2212 }, 2213 #endif 2214 { 2215 .desc = "Kernel page table isolation (KPTI)", 2216 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2217 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2218 /* 2219 * The ID feature fields below are used to indicate that 2220 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2221 * more details. 2222 */ 2223 .sys_reg = SYS_ID_AA64PFR0_EL1, 2224 .field_pos = ID_AA64PFR0_EL1_CSV3_SHIFT, 2225 .field_width = 4, 2226 .min_field_value = 1, 2227 .matches = unmap_kernel_at_el0, 2228 .cpu_enable = kpti_install_ng_mappings, 2229 }, 2230 { 2231 /* FP/SIMD is not implemented */ 2232 .capability = ARM64_HAS_NO_FPSIMD, 2233 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2234 .min_field_value = 0, 2235 .matches = has_no_fpsimd, 2236 }, 2237 #ifdef CONFIG_ARM64_PMEM 2238 { 2239 .desc = "Data cache clean to Point of Persistence", 2240 .capability = ARM64_HAS_DCPOP, 2241 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2242 .matches = has_cpuid_feature, 2243 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2244 .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT, 2245 .field_width = 4, 2246 .min_field_value = 1, 2247 }, 2248 { 2249 .desc = "Data cache clean to Point of Deep Persistence", 2250 .capability = ARM64_HAS_DCPODP, 2251 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2252 .matches = has_cpuid_feature, 2253 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2254 .sign = FTR_UNSIGNED, 2255 .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT, 2256 .field_width = 4, 2257 .min_field_value = 2, 2258 }, 2259 #endif 2260 #ifdef CONFIG_ARM64_SVE 2261 { 2262 .desc = "Scalable Vector Extension", 2263 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2264 .capability = ARM64_SVE, 2265 .sys_reg = SYS_ID_AA64PFR0_EL1, 2266 .sign = FTR_UNSIGNED, 2267 .field_pos = ID_AA64PFR0_EL1_SVE_SHIFT, 2268 .field_width = 4, 2269 .min_field_value = ID_AA64PFR0_EL1_SVE_IMP, 2270 .matches = has_cpuid_feature, 2271 .cpu_enable = sve_kernel_enable, 2272 }, 2273 #endif /* CONFIG_ARM64_SVE */ 2274 #ifdef CONFIG_ARM64_RAS_EXTN 2275 { 2276 .desc = "RAS Extension Support", 2277 .capability = ARM64_HAS_RAS_EXTN, 2278 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2279 .matches = has_cpuid_feature, 2280 .sys_reg = SYS_ID_AA64PFR0_EL1, 2281 .sign = FTR_UNSIGNED, 2282 .field_pos = ID_AA64PFR0_EL1_RAS_SHIFT, 2283 .field_width = 4, 2284 .min_field_value = ID_AA64PFR0_EL1_RAS_IMP, 2285 .cpu_enable = cpu_clear_disr, 2286 }, 2287 #endif /* CONFIG_ARM64_RAS_EXTN */ 2288 #ifdef CONFIG_ARM64_AMU_EXTN 2289 { 2290 /* 2291 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 2292 * Therefore, don't provide .desc as we don't want the detection 2293 * message to be shown until at least one CPU is detected to 2294 * support the feature. 2295 */ 2296 .capability = ARM64_HAS_AMU_EXTN, 2297 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2298 .matches = has_amu, 2299 .sys_reg = SYS_ID_AA64PFR0_EL1, 2300 .sign = FTR_UNSIGNED, 2301 .field_pos = ID_AA64PFR0_EL1_AMU_SHIFT, 2302 .field_width = 4, 2303 .min_field_value = ID_AA64PFR0_EL1_AMU_IMP, 2304 .cpu_enable = cpu_amu_enable, 2305 }, 2306 #endif /* CONFIG_ARM64_AMU_EXTN */ 2307 { 2308 .desc = "Data cache clean to the PoU not required for I/D coherence", 2309 .capability = ARM64_HAS_CACHE_IDC, 2310 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2311 .matches = has_cache_idc, 2312 .cpu_enable = cpu_emulate_effective_ctr, 2313 }, 2314 { 2315 .desc = "Instruction cache invalidation not required for I/D coherence", 2316 .capability = ARM64_HAS_CACHE_DIC, 2317 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2318 .matches = has_cache_dic, 2319 }, 2320 { 2321 .desc = "Stage-2 Force Write-Back", 2322 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2323 .capability = ARM64_HAS_STAGE2_FWB, 2324 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2325 .sign = FTR_UNSIGNED, 2326 .field_pos = ID_AA64MMFR2_EL1_FWB_SHIFT, 2327 .field_width = 4, 2328 .min_field_value = 1, 2329 .matches = has_cpuid_feature, 2330 }, 2331 { 2332 .desc = "ARMv8.4 Translation Table Level", 2333 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2334 .capability = ARM64_HAS_ARMv8_4_TTL, 2335 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2336 .sign = FTR_UNSIGNED, 2337 .field_pos = ID_AA64MMFR2_EL1_TTL_SHIFT, 2338 .field_width = 4, 2339 .min_field_value = 1, 2340 .matches = has_cpuid_feature, 2341 }, 2342 { 2343 .desc = "TLB range maintenance instructions", 2344 .capability = ARM64_HAS_TLB_RANGE, 2345 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2346 .matches = has_cpuid_feature, 2347 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2348 .field_pos = ID_AA64ISAR0_EL1_TLB_SHIFT, 2349 .field_width = 4, 2350 .sign = FTR_UNSIGNED, 2351 .min_field_value = ID_AA64ISAR0_EL1_TLB_RANGE, 2352 }, 2353 #ifdef CONFIG_ARM64_HW_AFDBM 2354 { 2355 /* 2356 * Since we turn this on always, we don't want the user to 2357 * think that the feature is available when it may not be. 2358 * So hide the description. 2359 * 2360 * .desc = "Hardware pagetable Dirty Bit Management", 2361 * 2362 */ 2363 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2364 .capability = ARM64_HW_DBM, 2365 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2366 .sign = FTR_UNSIGNED, 2367 .field_pos = ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 2368 .field_width = 4, 2369 .min_field_value = 2, 2370 .matches = has_hw_dbm, 2371 .cpu_enable = cpu_enable_hw_dbm, 2372 }, 2373 #endif 2374 { 2375 .desc = "CRC32 instructions", 2376 .capability = ARM64_HAS_CRC32, 2377 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2378 .matches = has_cpuid_feature, 2379 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2380 .field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT, 2381 .field_width = 4, 2382 .min_field_value = 1, 2383 }, 2384 { 2385 .desc = "Speculative Store Bypassing Safe (SSBS)", 2386 .capability = ARM64_SSBS, 2387 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2388 .matches = has_cpuid_feature, 2389 .sys_reg = SYS_ID_AA64PFR1_EL1, 2390 .field_pos = ID_AA64PFR1_EL1_SSBS_SHIFT, 2391 .field_width = 4, 2392 .sign = FTR_UNSIGNED, 2393 .min_field_value = ID_AA64PFR1_EL1_SSBS_IMP, 2394 }, 2395 #ifdef CONFIG_ARM64_CNP 2396 { 2397 .desc = "Common not Private translations", 2398 .capability = ARM64_HAS_CNP, 2399 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2400 .matches = has_useable_cnp, 2401 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2402 .sign = FTR_UNSIGNED, 2403 .field_pos = ID_AA64MMFR2_EL1_CnP_SHIFT, 2404 .field_width = 4, 2405 .min_field_value = 1, 2406 .cpu_enable = cpu_enable_cnp, 2407 }, 2408 #endif 2409 { 2410 .desc = "Speculation barrier (SB)", 2411 .capability = ARM64_HAS_SB, 2412 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2413 .matches = has_cpuid_feature, 2414 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2415 .field_pos = ID_AA64ISAR1_EL1_SB_SHIFT, 2416 .field_width = 4, 2417 .sign = FTR_UNSIGNED, 2418 .min_field_value = 1, 2419 }, 2420 #ifdef CONFIG_ARM64_PTR_AUTH 2421 { 2422 .desc = "Address authentication (architected QARMA5 algorithm)", 2423 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2424 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2425 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2426 .sign = FTR_UNSIGNED, 2427 .field_pos = ID_AA64ISAR1_EL1_APA_SHIFT, 2428 .field_width = 4, 2429 .min_field_value = ID_AA64ISAR1_EL1_APA_PAuth, 2430 .matches = has_address_auth_cpucap, 2431 }, 2432 { 2433 .desc = "Address authentication (architected QARMA3 algorithm)", 2434 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2435 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2436 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2437 .sign = FTR_UNSIGNED, 2438 .field_pos = ID_AA64ISAR2_EL1_APA3_SHIFT, 2439 .field_width = 4, 2440 .min_field_value = ID_AA64ISAR2_EL1_APA3_PAuth, 2441 .matches = has_address_auth_cpucap, 2442 }, 2443 { 2444 .desc = "Address authentication (IMP DEF algorithm)", 2445 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2446 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2447 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2448 .sign = FTR_UNSIGNED, 2449 .field_pos = ID_AA64ISAR1_EL1_API_SHIFT, 2450 .field_width = 4, 2451 .min_field_value = ID_AA64ISAR1_EL1_API_PAuth, 2452 .matches = has_address_auth_cpucap, 2453 }, 2454 { 2455 .capability = ARM64_HAS_ADDRESS_AUTH, 2456 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2457 .matches = has_address_auth_metacap, 2458 }, 2459 { 2460 .desc = "Generic authentication (architected QARMA5 algorithm)", 2461 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2462 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2463 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2464 .sign = FTR_UNSIGNED, 2465 .field_pos = ID_AA64ISAR1_EL1_GPA_SHIFT, 2466 .field_width = 4, 2467 .min_field_value = ID_AA64ISAR1_EL1_GPA_IMP, 2468 .matches = has_cpuid_feature, 2469 }, 2470 { 2471 .desc = "Generic authentication (architected QARMA3 algorithm)", 2472 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2473 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2474 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2475 .sign = FTR_UNSIGNED, 2476 .field_pos = ID_AA64ISAR2_EL1_GPA3_SHIFT, 2477 .field_width = 4, 2478 .min_field_value = ID_AA64ISAR2_EL1_GPA3_IMP, 2479 .matches = has_cpuid_feature, 2480 }, 2481 { 2482 .desc = "Generic authentication (IMP DEF algorithm)", 2483 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2484 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2485 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2486 .sign = FTR_UNSIGNED, 2487 .field_pos = ID_AA64ISAR1_EL1_GPI_SHIFT, 2488 .field_width = 4, 2489 .min_field_value = ID_AA64ISAR1_EL1_GPI_IMP, 2490 .matches = has_cpuid_feature, 2491 }, 2492 { 2493 .capability = ARM64_HAS_GENERIC_AUTH, 2494 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2495 .matches = has_generic_auth, 2496 }, 2497 #endif /* CONFIG_ARM64_PTR_AUTH */ 2498 #ifdef CONFIG_ARM64_PSEUDO_NMI 2499 { 2500 /* 2501 * Depends on having GICv3 2502 */ 2503 .desc = "IRQ priority masking", 2504 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2505 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2506 .matches = can_use_gic_priorities, 2507 .sys_reg = SYS_ID_AA64PFR0_EL1, 2508 .field_pos = ID_AA64PFR0_EL1_GIC_SHIFT, 2509 .field_width = 4, 2510 .sign = FTR_UNSIGNED, 2511 .min_field_value = 1, 2512 }, 2513 #endif 2514 #ifdef CONFIG_ARM64_E0PD 2515 { 2516 .desc = "E0PD", 2517 .capability = ARM64_HAS_E0PD, 2518 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2519 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2520 .sign = FTR_UNSIGNED, 2521 .field_width = 4, 2522 .field_pos = ID_AA64MMFR2_EL1_E0PD_SHIFT, 2523 .matches = has_cpuid_feature, 2524 .min_field_value = 1, 2525 .cpu_enable = cpu_enable_e0pd, 2526 }, 2527 #endif 2528 { 2529 .desc = "Random Number Generator", 2530 .capability = ARM64_HAS_RNG, 2531 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2532 .matches = has_cpuid_feature, 2533 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2534 .field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT, 2535 .field_width = 4, 2536 .sign = FTR_UNSIGNED, 2537 .min_field_value = 1, 2538 }, 2539 #ifdef CONFIG_ARM64_BTI 2540 { 2541 .desc = "Branch Target Identification", 2542 .capability = ARM64_BTI, 2543 #ifdef CONFIG_ARM64_BTI_KERNEL 2544 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2545 #else 2546 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2547 #endif 2548 .matches = has_cpuid_feature, 2549 .cpu_enable = bti_enable, 2550 .sys_reg = SYS_ID_AA64PFR1_EL1, 2551 .field_pos = ID_AA64PFR1_EL1_BT_SHIFT, 2552 .field_width = 4, 2553 .min_field_value = ID_AA64PFR1_EL1_BT_IMP, 2554 .sign = FTR_UNSIGNED, 2555 }, 2556 #endif 2557 #ifdef CONFIG_ARM64_MTE 2558 { 2559 .desc = "Memory Tagging Extension", 2560 .capability = ARM64_MTE, 2561 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2562 .matches = has_cpuid_feature, 2563 .sys_reg = SYS_ID_AA64PFR1_EL1, 2564 .field_pos = ID_AA64PFR1_EL1_MTE_SHIFT, 2565 .field_width = 4, 2566 .min_field_value = ID_AA64PFR1_EL1_MTE_MTE2, 2567 .sign = FTR_UNSIGNED, 2568 .cpu_enable = cpu_enable_mte, 2569 }, 2570 { 2571 .desc = "Asymmetric MTE Tag Check Fault", 2572 .capability = ARM64_MTE_ASYMM, 2573 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2574 .matches = has_cpuid_feature, 2575 .sys_reg = SYS_ID_AA64PFR1_EL1, 2576 .field_pos = ID_AA64PFR1_EL1_MTE_SHIFT, 2577 .field_width = 4, 2578 .min_field_value = ID_AA64PFR1_EL1_MTE_MTE3, 2579 .sign = FTR_UNSIGNED, 2580 }, 2581 #endif /* CONFIG_ARM64_MTE */ 2582 { 2583 .desc = "RCpc load-acquire (LDAPR)", 2584 .capability = ARM64_HAS_LDAPR, 2585 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2586 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2587 .sign = FTR_UNSIGNED, 2588 .field_pos = ID_AA64ISAR1_EL1_LRCPC_SHIFT, 2589 .field_width = 4, 2590 .matches = has_cpuid_feature, 2591 .min_field_value = 1, 2592 }, 2593 #ifdef CONFIG_ARM64_SME 2594 { 2595 .desc = "Scalable Matrix Extension", 2596 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2597 .capability = ARM64_SME, 2598 .sys_reg = SYS_ID_AA64PFR1_EL1, 2599 .sign = FTR_UNSIGNED, 2600 .field_pos = ID_AA64PFR1_EL1_SME_SHIFT, 2601 .field_width = 4, 2602 .min_field_value = ID_AA64PFR1_EL1_SME_IMP, 2603 .matches = has_cpuid_feature, 2604 .cpu_enable = sme_kernel_enable, 2605 }, 2606 /* FA64 should be sorted after the base SME capability */ 2607 { 2608 .desc = "FA64", 2609 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2610 .capability = ARM64_SME_FA64, 2611 .sys_reg = SYS_ID_AA64SMFR0_EL1, 2612 .sign = FTR_UNSIGNED, 2613 .field_pos = ID_AA64SMFR0_EL1_FA64_SHIFT, 2614 .field_width = 1, 2615 .min_field_value = ID_AA64SMFR0_EL1_FA64_IMP, 2616 .matches = has_cpuid_feature, 2617 .cpu_enable = fa64_kernel_enable, 2618 }, 2619 #endif /* CONFIG_ARM64_SME */ 2620 { 2621 .desc = "WFx with timeout", 2622 .capability = ARM64_HAS_WFXT, 2623 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2624 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2625 .sign = FTR_UNSIGNED, 2626 .field_pos = ID_AA64ISAR2_EL1_WFxT_SHIFT, 2627 .field_width = 4, 2628 .matches = has_cpuid_feature, 2629 .min_field_value = ID_AA64ISAR2_EL1_WFxT_IMP, 2630 }, 2631 { 2632 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2633 .capability = ARM64_HAS_TIDCP1, 2634 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2635 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2636 .sign = FTR_UNSIGNED, 2637 .field_pos = ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 2638 .field_width = 4, 2639 .min_field_value = ID_AA64MMFR1_EL1_TIDCP1_IMP, 2640 .matches = has_cpuid_feature, 2641 .cpu_enable = cpu_trap_el0_impdef, 2642 }, 2643 {}, 2644 }; 2645 2646 #define HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ 2647 .matches = has_user_cpuid_feature, \ 2648 .sys_reg = reg, \ 2649 .field_pos = field, \ 2650 .field_width = width, \ 2651 .sign = s, \ 2652 .min_field_value = min_value, 2653 2654 #define __HWCAP_CAP(name, cap_type, cap) \ 2655 .desc = name, \ 2656 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2657 .hwcap_type = cap_type, \ 2658 .hwcap = cap, \ 2659 2660 #define HWCAP_CAP(reg, field, width, s, min_value, cap_type, cap) \ 2661 { \ 2662 __HWCAP_CAP(#cap, cap_type, cap) \ 2663 HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ 2664 } 2665 2666 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2667 { \ 2668 __HWCAP_CAP(#cap, cap_type, cap) \ 2669 .matches = cpucap_multi_entry_cap_matches, \ 2670 .match_list = list, \ 2671 } 2672 2673 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2674 { \ 2675 __HWCAP_CAP(#cap, cap_type, cap) \ 2676 .matches = match, \ 2677 } 2678 2679 #ifdef CONFIG_ARM64_PTR_AUTH 2680 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2681 { 2682 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_APA_SHIFT, 2683 4, FTR_UNSIGNED, 2684 ID_AA64ISAR1_EL1_APA_PAuth) 2685 }, 2686 { 2687 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_APA3_SHIFT, 2688 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_APA3_PAuth) 2689 }, 2690 { 2691 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT, 2692 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_API_PAuth) 2693 }, 2694 {}, 2695 }; 2696 2697 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2698 { 2699 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPA_SHIFT, 2700 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP) 2701 }, 2702 { 2703 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_GPA3_SHIFT, 2704 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_GPA3_IMP) 2705 }, 2706 { 2707 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT, 2708 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPI_IMP) 2709 }, 2710 {}, 2711 }; 2712 #endif 2713 2714 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2715 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2716 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2717 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2718 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2719 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2720 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2721 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2722 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2723 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2724 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2725 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2726 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2727 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2728 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2729 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2730 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2731 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2732 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2733 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2734 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2735 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2736 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2737 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2738 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2739 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2740 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2741 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2742 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2743 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2744 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2745 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_EBF16), 2746 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2747 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2748 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_EL1_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2749 #ifdef CONFIG_ARM64_SVE 2750 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_EL1_SVE_IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 2751 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2752 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2753 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2754 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BitPerm_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2755 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2756 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 2757 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SHA3_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2758 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SM4_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2759 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_I8MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2760 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F32MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2761 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F64MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2762 #endif 2763 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_SSBS_SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2764 #ifdef CONFIG_ARM64_BTI 2765 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_BT_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_BT_IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 2766 #endif 2767 #ifdef CONFIG_ARM64_PTR_AUTH 2768 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2769 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2770 #endif 2771 #ifdef CONFIG_ARM64_MTE 2772 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 2773 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 2774 #endif /* CONFIG_ARM64_MTE */ 2775 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), 2776 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), 2777 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2778 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 2779 #ifdef CONFIG_ARM64_SME 2780 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_SME_IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 2781 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 2782 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I16I64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 2783 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F64F64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 2784 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I8I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 2785 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 2786 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_B16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 2787 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F32F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 2788 #endif /* CONFIG_ARM64_SME */ 2789 {}, 2790 }; 2791 2792 #ifdef CONFIG_COMPAT 2793 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2794 { 2795 /* 2796 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2797 * in line with that of arm32 as in vfp_init(). We make sure that the 2798 * check is future proof, by making sure value is non-zero. 2799 */ 2800 u32 mvfr1; 2801 2802 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2803 if (scope == SCOPE_SYSTEM) 2804 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2805 else 2806 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2807 2808 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2809 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2810 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2811 } 2812 #endif 2813 2814 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2815 #ifdef CONFIG_COMPAT 2816 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2817 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2818 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2819 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2820 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2821 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2822 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2823 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2824 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2825 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2826 #endif 2827 {}, 2828 }; 2829 2830 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2831 { 2832 switch (cap->hwcap_type) { 2833 case CAP_HWCAP: 2834 cpu_set_feature(cap->hwcap); 2835 break; 2836 #ifdef CONFIG_COMPAT 2837 case CAP_COMPAT_HWCAP: 2838 compat_elf_hwcap |= (u32)cap->hwcap; 2839 break; 2840 case CAP_COMPAT_HWCAP2: 2841 compat_elf_hwcap2 |= (u32)cap->hwcap; 2842 break; 2843 #endif 2844 default: 2845 WARN_ON(1); 2846 break; 2847 } 2848 } 2849 2850 /* Check if we have a particular HWCAP enabled */ 2851 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2852 { 2853 bool rc; 2854 2855 switch (cap->hwcap_type) { 2856 case CAP_HWCAP: 2857 rc = cpu_have_feature(cap->hwcap); 2858 break; 2859 #ifdef CONFIG_COMPAT 2860 case CAP_COMPAT_HWCAP: 2861 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2862 break; 2863 case CAP_COMPAT_HWCAP2: 2864 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2865 break; 2866 #endif 2867 default: 2868 WARN_ON(1); 2869 rc = false; 2870 } 2871 2872 return rc; 2873 } 2874 2875 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2876 { 2877 /* We support emulation of accesses to CPU ID feature registers */ 2878 cpu_set_named_feature(CPUID); 2879 for (; hwcaps->matches; hwcaps++) 2880 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2881 cap_set_elf_hwcap(hwcaps); 2882 } 2883 2884 static void update_cpu_capabilities(u16 scope_mask) 2885 { 2886 int i; 2887 const struct arm64_cpu_capabilities *caps; 2888 2889 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2890 for (i = 0; i < ARM64_NCAPS; i++) { 2891 caps = cpu_hwcaps_ptrs[i]; 2892 if (!caps || !(caps->type & scope_mask) || 2893 cpus_have_cap(caps->capability) || 2894 !caps->matches(caps, cpucap_default_scope(caps))) 2895 continue; 2896 2897 if (caps->desc) 2898 pr_info("detected: %s\n", caps->desc); 2899 cpus_set_cap(caps->capability); 2900 2901 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2902 set_bit(caps->capability, boot_capabilities); 2903 } 2904 } 2905 2906 /* 2907 * Enable all the available capabilities on this CPU. The capabilities 2908 * with BOOT_CPU scope are handled separately and hence skipped here. 2909 */ 2910 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2911 { 2912 int i; 2913 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2914 2915 for_each_available_cap(i) { 2916 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2917 2918 if (WARN_ON(!cap)) 2919 continue; 2920 2921 if (!(cap->type & non_boot_scope)) 2922 continue; 2923 2924 if (cap->cpu_enable) 2925 cap->cpu_enable(cap); 2926 } 2927 return 0; 2928 } 2929 2930 /* 2931 * Run through the enabled capabilities and enable() it on all active 2932 * CPUs 2933 */ 2934 static void __init enable_cpu_capabilities(u16 scope_mask) 2935 { 2936 int i; 2937 const struct arm64_cpu_capabilities *caps; 2938 bool boot_scope; 2939 2940 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2941 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2942 2943 for (i = 0; i < ARM64_NCAPS; i++) { 2944 unsigned int num; 2945 2946 caps = cpu_hwcaps_ptrs[i]; 2947 if (!caps || !(caps->type & scope_mask)) 2948 continue; 2949 num = caps->capability; 2950 if (!cpus_have_cap(num)) 2951 continue; 2952 2953 if (boot_scope && caps->cpu_enable) 2954 /* 2955 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2956 * before any secondary CPU boots. Thus, each secondary 2957 * will enable the capability as appropriate via 2958 * check_local_cpu_capabilities(). The only exception is 2959 * the boot CPU, for which the capability must be 2960 * enabled here. This approach avoids costly 2961 * stop_machine() calls for this case. 2962 */ 2963 caps->cpu_enable(caps); 2964 } 2965 2966 /* 2967 * For all non-boot scope capabilities, use stop_machine() 2968 * as it schedules the work allowing us to modify PSTATE, 2969 * instead of on_each_cpu() which uses an IPI, giving us a 2970 * PSTATE that disappears when we return. 2971 */ 2972 if (!boot_scope) 2973 stop_machine(cpu_enable_non_boot_scope_capabilities, 2974 NULL, cpu_online_mask); 2975 } 2976 2977 /* 2978 * Run through the list of capabilities to check for conflicts. 2979 * If the system has already detected a capability, take necessary 2980 * action on this CPU. 2981 */ 2982 static void verify_local_cpu_caps(u16 scope_mask) 2983 { 2984 int i; 2985 bool cpu_has_cap, system_has_cap; 2986 const struct arm64_cpu_capabilities *caps; 2987 2988 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2989 2990 for (i = 0; i < ARM64_NCAPS; i++) { 2991 caps = cpu_hwcaps_ptrs[i]; 2992 if (!caps || !(caps->type & scope_mask)) 2993 continue; 2994 2995 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2996 system_has_cap = cpus_have_cap(caps->capability); 2997 2998 if (system_has_cap) { 2999 /* 3000 * Check if the new CPU misses an advertised feature, 3001 * which is not safe to miss. 3002 */ 3003 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3004 break; 3005 /* 3006 * We have to issue cpu_enable() irrespective of 3007 * whether the CPU has it or not, as it is enabeld 3008 * system wide. It is upto the call back to take 3009 * appropriate action on this CPU. 3010 */ 3011 if (caps->cpu_enable) 3012 caps->cpu_enable(caps); 3013 } else { 3014 /* 3015 * Check if the CPU has this capability if it isn't 3016 * safe to have when the system doesn't. 3017 */ 3018 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3019 break; 3020 } 3021 } 3022 3023 if (i < ARM64_NCAPS) { 3024 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3025 smp_processor_id(), caps->capability, 3026 caps->desc, system_has_cap, cpu_has_cap); 3027 3028 if (cpucap_panic_on_conflict(caps)) 3029 cpu_panic_kernel(); 3030 else 3031 cpu_die_early(); 3032 } 3033 } 3034 3035 /* 3036 * Check for CPU features that are used in early boot 3037 * based on the Boot CPU value. 3038 */ 3039 static void check_early_cpu_features(void) 3040 { 3041 verify_cpu_asid_bits(); 3042 3043 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3044 } 3045 3046 static void 3047 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3048 { 3049 3050 for (; caps->matches; caps++) 3051 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3052 pr_crit("CPU%d: missing HWCAP: %s\n", 3053 smp_processor_id(), caps->desc); 3054 cpu_die_early(); 3055 } 3056 } 3057 3058 static void verify_local_elf_hwcaps(void) 3059 { 3060 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3061 3062 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3063 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3064 } 3065 3066 static void verify_sve_features(void) 3067 { 3068 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 3069 u64 zcr = read_zcr_features(); 3070 3071 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 3072 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 3073 3074 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) { 3075 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3076 smp_processor_id()); 3077 cpu_die_early(); 3078 } 3079 3080 /* Add checks on other ZCR bits here if necessary */ 3081 } 3082 3083 static void verify_sme_features(void) 3084 { 3085 u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1); 3086 u64 smcr = read_smcr_features(); 3087 3088 unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK; 3089 unsigned int len = smcr & SMCR_ELx_LEN_MASK; 3090 3091 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) { 3092 pr_crit("CPU%d: SME: vector length support mismatch\n", 3093 smp_processor_id()); 3094 cpu_die_early(); 3095 } 3096 3097 /* Add checks on other SMCR bits here if necessary */ 3098 } 3099 3100 static void verify_hyp_capabilities(void) 3101 { 3102 u64 safe_mmfr1, mmfr0, mmfr1; 3103 int parange, ipa_max; 3104 unsigned int safe_vmid_bits, vmid_bits; 3105 3106 if (!IS_ENABLED(CONFIG_KVM)) 3107 return; 3108 3109 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3110 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3111 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3112 3113 /* Verify VMID bits */ 3114 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3115 vmid_bits = get_vmid_bits(mmfr1); 3116 if (vmid_bits < safe_vmid_bits) { 3117 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3118 cpu_die_early(); 3119 } 3120 3121 /* Verify IPA range */ 3122 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3123 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3124 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3125 if (ipa_max < get_kvm_ipa_limit()) { 3126 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3127 cpu_die_early(); 3128 } 3129 } 3130 3131 /* 3132 * Run through the enabled system capabilities and enable() it on this CPU. 3133 * The capabilities were decided based on the available CPUs at the boot time. 3134 * Any new CPU should match the system wide status of the capability. If the 3135 * new CPU doesn't have a capability which the system now has enabled, we 3136 * cannot do anything to fix it up and could cause unexpected failures. So 3137 * we park the CPU. 3138 */ 3139 static void verify_local_cpu_capabilities(void) 3140 { 3141 /* 3142 * The capabilities with SCOPE_BOOT_CPU are checked from 3143 * check_early_cpu_features(), as they need to be verified 3144 * on all secondary CPUs. 3145 */ 3146 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3147 verify_local_elf_hwcaps(); 3148 3149 if (system_supports_sve()) 3150 verify_sve_features(); 3151 3152 if (system_supports_sme()) 3153 verify_sme_features(); 3154 3155 if (is_hyp_mode_available()) 3156 verify_hyp_capabilities(); 3157 } 3158 3159 void check_local_cpu_capabilities(void) 3160 { 3161 /* 3162 * All secondary CPUs should conform to the early CPU features 3163 * in use by the kernel based on boot CPU. 3164 */ 3165 check_early_cpu_features(); 3166 3167 /* 3168 * If we haven't finalised the system capabilities, this CPU gets 3169 * a chance to update the errata work arounds and local features. 3170 * Otherwise, this CPU should verify that it has all the system 3171 * advertised capabilities. 3172 */ 3173 if (!system_capabilities_finalized()) 3174 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3175 else 3176 verify_local_cpu_capabilities(); 3177 } 3178 3179 static void __init setup_boot_cpu_capabilities(void) 3180 { 3181 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 3182 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3183 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 3184 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3185 } 3186 3187 bool this_cpu_has_cap(unsigned int n) 3188 { 3189 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3190 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 3191 3192 if (cap) 3193 return cap->matches(cap, SCOPE_LOCAL_CPU); 3194 } 3195 3196 return false; 3197 } 3198 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3199 3200 /* 3201 * This helper function is used in a narrow window when, 3202 * - The system wide safe registers are set with all the SMP CPUs and, 3203 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 3204 * In all other cases cpus_have_{const_}cap() should be used. 3205 */ 3206 static bool __maybe_unused __system_matches_cap(unsigned int n) 3207 { 3208 if (n < ARM64_NCAPS) { 3209 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 3210 3211 if (cap) 3212 return cap->matches(cap, SCOPE_SYSTEM); 3213 } 3214 return false; 3215 } 3216 3217 void cpu_set_feature(unsigned int num) 3218 { 3219 set_bit(num, elf_hwcap); 3220 } 3221 3222 bool cpu_have_feature(unsigned int num) 3223 { 3224 return test_bit(num, elf_hwcap); 3225 } 3226 EXPORT_SYMBOL_GPL(cpu_have_feature); 3227 3228 unsigned long cpu_get_elf_hwcap(void) 3229 { 3230 /* 3231 * We currently only populate the first 32 bits of AT_HWCAP. Please 3232 * note that for userspace compatibility we guarantee that bits 62 3233 * and 63 will always be returned as 0. 3234 */ 3235 return elf_hwcap[0]; 3236 } 3237 3238 unsigned long cpu_get_elf_hwcap2(void) 3239 { 3240 return elf_hwcap[1]; 3241 } 3242 3243 static void __init setup_system_capabilities(void) 3244 { 3245 /* 3246 * We have finalised the system-wide safe feature 3247 * registers, finalise the capabilities that depend 3248 * on it. Also enable all the available capabilities, 3249 * that are not enabled already. 3250 */ 3251 update_cpu_capabilities(SCOPE_SYSTEM); 3252 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3253 } 3254 3255 void __init setup_cpu_features(void) 3256 { 3257 u32 cwg; 3258 3259 setup_system_capabilities(); 3260 setup_elf_hwcaps(arm64_elf_hwcaps); 3261 3262 if (system_supports_32bit_el0()) { 3263 setup_elf_hwcaps(compat_elf_hwcaps); 3264 elf_hwcap_fixup(); 3265 } 3266 3267 if (system_uses_ttbr0_pan()) 3268 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3269 3270 sve_setup(); 3271 sme_setup(); 3272 minsigstksz_setup(); 3273 3274 /* 3275 * Check for sane CTR_EL0.CWG value. 3276 */ 3277 cwg = cache_type_cwg(); 3278 if (!cwg) 3279 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3280 ARCH_DMA_MINALIGN); 3281 } 3282 3283 static int enable_mismatched_32bit_el0(unsigned int cpu) 3284 { 3285 /* 3286 * The first 32-bit-capable CPU we detected and so can no longer 3287 * be offlined by userspace. -1 indicates we haven't yet onlined 3288 * a 32-bit-capable CPU. 3289 */ 3290 static int lucky_winner = -1; 3291 3292 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3293 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3294 3295 if (cpu_32bit) { 3296 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3297 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3298 } 3299 3300 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3301 return 0; 3302 3303 if (lucky_winner >= 0) 3304 return 0; 3305 3306 /* 3307 * We've detected a mismatch. We need to keep one of our CPUs with 3308 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3309 * every CPU in the system for a 32-bit task. 3310 */ 3311 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3312 cpu_active_mask); 3313 get_cpu_device(lucky_winner)->offline_disabled = true; 3314 setup_elf_hwcaps(compat_elf_hwcaps); 3315 elf_hwcap_fixup(); 3316 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3317 cpu, lucky_winner); 3318 return 0; 3319 } 3320 3321 static int __init init_32bit_el0_mask(void) 3322 { 3323 if (!allow_mismatched_32bit_el0) 3324 return 0; 3325 3326 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3327 return -ENOMEM; 3328 3329 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3330 "arm64/mismatched_32bit_el0:online", 3331 enable_mismatched_32bit_el0, NULL); 3332 } 3333 subsys_initcall_sync(init_32bit_el0_mask); 3334 3335 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3336 { 3337 cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir); 3338 } 3339 3340 /* 3341 * We emulate only the following system register space. 3342 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 3343 * See Table C5-6 System instruction encodings for System register accesses, 3344 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3345 */ 3346 static inline bool __attribute_const__ is_emulated(u32 id) 3347 { 3348 return (sys_reg_Op0(id) == 0x3 && 3349 sys_reg_CRn(id) == 0x0 && 3350 sys_reg_Op1(id) == 0x0 && 3351 (sys_reg_CRm(id) == 0 || 3352 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 3353 } 3354 3355 /* 3356 * With CRm == 0, reg should be one of : 3357 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3358 */ 3359 static inline int emulate_id_reg(u32 id, u64 *valp) 3360 { 3361 switch (id) { 3362 case SYS_MIDR_EL1: 3363 *valp = read_cpuid_id(); 3364 break; 3365 case SYS_MPIDR_EL1: 3366 *valp = SYS_MPIDR_SAFE_VAL; 3367 break; 3368 case SYS_REVIDR_EL1: 3369 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3370 *valp = 0; 3371 break; 3372 default: 3373 return -EINVAL; 3374 } 3375 3376 return 0; 3377 } 3378 3379 static int emulate_sys_reg(u32 id, u64 *valp) 3380 { 3381 struct arm64_ftr_reg *regp; 3382 3383 if (!is_emulated(id)) 3384 return -EINVAL; 3385 3386 if (sys_reg_CRm(id) == 0) 3387 return emulate_id_reg(id, valp); 3388 3389 regp = get_arm64_ftr_reg_nowarn(id); 3390 if (regp) 3391 *valp = arm64_ftr_reg_user_value(regp); 3392 else 3393 /* 3394 * The untracked registers are either IMPLEMENTATION DEFINED 3395 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3396 */ 3397 *valp = 0; 3398 return 0; 3399 } 3400 3401 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3402 { 3403 int rc; 3404 u64 val; 3405 3406 rc = emulate_sys_reg(sys_reg, &val); 3407 if (!rc) { 3408 pt_regs_write_reg(regs, rt, val); 3409 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3410 } 3411 return rc; 3412 } 3413 3414 static int emulate_mrs(struct pt_regs *regs, u32 insn) 3415 { 3416 u32 sys_reg, rt; 3417 3418 /* 3419 * sys_reg values are defined as used in mrs/msr instruction. 3420 * shift the imm value to get the encoding. 3421 */ 3422 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3423 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3424 return do_emulate_mrs(regs, sys_reg, rt); 3425 } 3426 3427 static struct undef_hook mrs_hook = { 3428 .instr_mask = 0xffff0000, 3429 .instr_val = 0xd5380000, 3430 .pstate_mask = PSR_AA32_MODE_MASK, 3431 .pstate_val = PSR_MODE_EL0t, 3432 .fn = emulate_mrs, 3433 }; 3434 3435 static int __init enable_mrs_emulation(void) 3436 { 3437 register_undef_hook(&mrs_hook); 3438 return 0; 3439 } 3440 3441 core_initcall(enable_mrs_emulation); 3442 3443 enum mitigation_state arm64_get_meltdown_state(void) 3444 { 3445 if (__meltdown_safe) 3446 return SPECTRE_UNAFFECTED; 3447 3448 if (arm64_kernel_unmapped_at_el0()) 3449 return SPECTRE_MITIGATED; 3450 3451 return SPECTRE_VULNERABLE; 3452 } 3453 3454 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3455 char *buf) 3456 { 3457 switch (arm64_get_meltdown_state()) { 3458 case SPECTRE_UNAFFECTED: 3459 return sprintf(buf, "Not affected\n"); 3460 3461 case SPECTRE_MITIGATED: 3462 return sprintf(buf, "Mitigation: PTI\n"); 3463 3464 default: 3465 return sprintf(buf, "Vulnerable\n"); 3466 } 3467 } 3468