1 /* 2 * Contains CPU feature definitions 3 * 4 * Copyright (C) 2015 ARM Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #define pr_fmt(fmt) "CPU features: " fmt 20 21 #include <linux/bsearch.h> 22 #include <linux/cpumask.h> 23 #include <linux/crash_dump.h> 24 #include <linux/sort.h> 25 #include <linux/stop_machine.h> 26 #include <linux/types.h> 27 #include <linux/mm.h> 28 #include <asm/cpu.h> 29 #include <asm/cpufeature.h> 30 #include <asm/cpu_ops.h> 31 #include <asm/fpsimd.h> 32 #include <asm/mmu_context.h> 33 #include <asm/processor.h> 34 #include <asm/sysreg.h> 35 #include <asm/traps.h> 36 #include <asm/virt.h> 37 38 unsigned long elf_hwcap __read_mostly; 39 EXPORT_SYMBOL_GPL(elf_hwcap); 40 41 #ifdef CONFIG_COMPAT 42 #define COMPAT_ELF_HWCAP_DEFAULT \ 43 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 44 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 45 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ 46 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ 47 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ 48 COMPAT_HWCAP_LPAE) 49 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 50 unsigned int compat_elf_hwcap2 __read_mostly; 51 #endif 52 53 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 54 EXPORT_SYMBOL(cpu_hwcaps); 55 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 56 57 /* 58 * Flag to indicate if we have computed the system wide 59 * capabilities based on the boot time active CPUs. This 60 * will be used to determine if a new booting CPU should 61 * go through the verification process to make sure that it 62 * supports the system capabilities, without using a hotplug 63 * notifier. 64 */ 65 static bool sys_caps_initialised; 66 67 static inline void set_sys_caps_initialised(void) 68 { 69 sys_caps_initialised = true; 70 } 71 72 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p) 73 { 74 /* file-wide pr_fmt adds "CPU features: " prefix */ 75 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 76 return 0; 77 } 78 79 static struct notifier_block cpu_hwcaps_notifier = { 80 .notifier_call = dump_cpu_hwcaps 81 }; 82 83 static int __init register_cpu_hwcaps_dumper(void) 84 { 85 atomic_notifier_chain_register(&panic_notifier_list, 86 &cpu_hwcaps_notifier); 87 return 0; 88 } 89 __initcall(register_cpu_hwcaps_dumper); 90 91 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 92 EXPORT_SYMBOL(cpu_hwcap_keys); 93 94 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 95 { \ 96 .sign = SIGNED, \ 97 .visible = VISIBLE, \ 98 .strict = STRICT, \ 99 .type = TYPE, \ 100 .shift = SHIFT, \ 101 .width = WIDTH, \ 102 .safe_val = SAFE_VAL, \ 103 } 104 105 /* Define a feature with unsigned values */ 106 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 107 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 108 109 /* Define a feature with a signed value */ 110 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 111 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 112 113 #define ARM64_FTR_END \ 114 { \ 115 .width = 0, \ 116 } 117 118 /* meta feature for alternatives */ 119 static bool __maybe_unused 120 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused); 121 122 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 123 124 /* 125 * NOTE: Any changes to the visibility of features should be kept in 126 * sync with the documentation of the CPU feature register ABI. 127 */ 128 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 134 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 136 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 137 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 138 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 139 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 140 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 141 ARM64_FTR_END, 142 }; 143 144 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 145 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 146 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 147 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 148 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 149 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 150 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 151 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 152 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 153 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 154 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0), 155 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 156 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0), 157 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 158 ARM64_FTR_END, 159 }; 160 161 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 162 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 163 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 164 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 165 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 166 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 167 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 169 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 170 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 171 /* Linux doesn't care about the EL3 */ 172 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 173 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 174 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 175 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 176 ARM64_FTR_END, 177 }; 178 179 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 181 ARM64_FTR_END, 182 }; 183 184 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 185 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 186 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 187 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 189 /* Linux shouldn't care about secure memory */ 190 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 192 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 193 /* 194 * Differing PARange is fine as long as all peripherals and memory are mapped 195 * within the minimum PARange of all CPUs 196 */ 197 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 198 ARM64_FTR_END, 199 }; 200 201 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 202 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 208 ARM64_FTR_END, 209 }; 210 211 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 219 ARM64_FTR_END, 220 }; 221 222 static const struct arm64_ftr_bits ftr_ctr[] = { 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 229 /* 230 * Linux can handle differing I-cache policies. Userspace JITs will 231 * make use of *minLine. 232 * If we have differing I-cache policies, report it as the weakest - VIPT. 233 */ 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 236 ARM64_FTR_END, 237 }; 238 239 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 240 .name = "SYS_CTR_EL0", 241 .ftr_bits = ftr_ctr 242 }; 243 244 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 245 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */ 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */ 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */ 248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */ 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */ 250 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */ 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */ 252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */ 253 ARM64_FTR_END, 254 }; 255 256 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 257 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0), 258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 262 /* 263 * We can instantiate multiple PMU instances with different levels 264 * of support. 265 */ 266 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 269 ARM64_FTR_END, 270 }; 271 272 static const struct arm64_ftr_bits ftr_mvfr2[] = { 273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */ 274 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */ 275 ARM64_FTR_END, 276 }; 277 278 static const struct arm64_ftr_bits ftr_dczid[] = { 279 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */ 280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */ 281 ARM64_FTR_END, 282 }; 283 284 285 static const struct arm64_ftr_bits ftr_id_isar5[] = { 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 292 ARM64_FTR_END, 293 }; 294 295 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */ 297 ARM64_FTR_END, 298 }; 299 300 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */ 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */ 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */ 304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */ 305 ARM64_FTR_END, 306 }; 307 308 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 310 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 317 ARM64_FTR_END, 318 }; 319 320 static const struct arm64_ftr_bits ftr_zcr[] = { 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 322 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 323 ARM64_FTR_END, 324 }; 325 326 /* 327 * Common ftr bits for a 32bit register with all hidden, strict 328 * attributes, with 4bit feature fields and a default safe value of 329 * 0. Covers the following 32bit registers: 330 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 331 */ 332 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 339 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 341 ARM64_FTR_END, 342 }; 343 344 /* Table for a single 32bit feature value */ 345 static const struct arm64_ftr_bits ftr_single32[] = { 346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 347 ARM64_FTR_END, 348 }; 349 350 static const struct arm64_ftr_bits ftr_raz[] = { 351 ARM64_FTR_END, 352 }; 353 354 #define ARM64_FTR_REG(id, table) { \ 355 .sys_id = id, \ 356 .reg = &(struct arm64_ftr_reg){ \ 357 .name = #id, \ 358 .ftr_bits = &((table)[0]), \ 359 }} 360 361 static const struct __ftr_reg_entry { 362 u32 sys_id; 363 struct arm64_ftr_reg *reg; 364 } arm64_ftr_regs[] = { 365 366 /* Op1 = 0, CRn = 0, CRm = 1 */ 367 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 368 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits), 369 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 370 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 371 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 372 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 373 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 374 375 /* Op1 = 0, CRn = 0, CRm = 2 */ 376 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits), 377 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 378 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 379 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 380 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits), 381 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 382 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 383 384 /* Op1 = 0, CRn = 0, CRm = 3 */ 385 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 386 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 387 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 388 389 /* Op1 = 0, CRn = 0, CRm = 4 */ 390 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 391 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1), 392 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz), 393 394 /* Op1 = 0, CRn = 0, CRm = 5 */ 395 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 396 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 397 398 /* Op1 = 0, CRn = 0, CRm = 6 */ 399 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 400 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), 401 402 /* Op1 = 0, CRn = 0, CRm = 7 */ 403 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 404 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), 405 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 406 407 /* Op1 = 0, CRn = 1, CRm = 2 */ 408 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 409 410 /* Op1 = 3, CRn = 0, CRm = 0 */ 411 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 412 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 413 414 /* Op1 = 3, CRn = 14, CRm = 0 */ 415 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 416 }; 417 418 static int search_cmp_ftr_reg(const void *id, const void *regp) 419 { 420 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 421 } 422 423 /* 424 * get_arm64_ftr_reg - Lookup a feature register entry using its 425 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the 426 * ascending order of sys_id , we use binary search to find a matching 427 * entry. 428 * 429 * returns - Upon success, matching ftr_reg entry for id. 430 * - NULL on failure. It is upto the caller to decide 431 * the impact of a failure. 432 */ 433 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 434 { 435 const struct __ftr_reg_entry *ret; 436 437 ret = bsearch((const void *)(unsigned long)sys_id, 438 arm64_ftr_regs, 439 ARRAY_SIZE(arm64_ftr_regs), 440 sizeof(arm64_ftr_regs[0]), 441 search_cmp_ftr_reg); 442 if (ret) 443 return ret->reg; 444 return NULL; 445 } 446 447 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 448 s64 ftr_val) 449 { 450 u64 mask = arm64_ftr_mask(ftrp); 451 452 reg &= ~mask; 453 reg |= (ftr_val << ftrp->shift) & mask; 454 return reg; 455 } 456 457 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 458 s64 cur) 459 { 460 s64 ret = 0; 461 462 switch (ftrp->type) { 463 case FTR_EXACT: 464 ret = ftrp->safe_val; 465 break; 466 case FTR_LOWER_SAFE: 467 ret = new < cur ? new : cur; 468 break; 469 case FTR_HIGHER_SAFE: 470 ret = new > cur ? new : cur; 471 break; 472 default: 473 BUG(); 474 } 475 476 return ret; 477 } 478 479 static void __init sort_ftr_regs(void) 480 { 481 int i; 482 483 /* Check that the array is sorted so that we can do the binary search */ 484 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++) 485 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 486 } 487 488 /* 489 * Initialise the CPU feature register from Boot CPU values. 490 * Also initiliases the strict_mask for the register. 491 * Any bits that are not covered by an arm64_ftr_bits entry are considered 492 * RES0 for the system-wide value, and must strictly match. 493 */ 494 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 495 { 496 u64 val = 0; 497 u64 strict_mask = ~0x0ULL; 498 u64 user_mask = 0; 499 u64 valid_mask = 0; 500 501 const struct arm64_ftr_bits *ftrp; 502 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 503 504 BUG_ON(!reg); 505 506 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 507 u64 ftr_mask = arm64_ftr_mask(ftrp); 508 s64 ftr_new = arm64_ftr_value(ftrp, new); 509 510 val = arm64_ftr_set_value(ftrp, val, ftr_new); 511 512 valid_mask |= ftr_mask; 513 if (!ftrp->strict) 514 strict_mask &= ~ftr_mask; 515 if (ftrp->visible) 516 user_mask |= ftr_mask; 517 else 518 reg->user_val = arm64_ftr_set_value(ftrp, 519 reg->user_val, 520 ftrp->safe_val); 521 } 522 523 val &= valid_mask; 524 525 reg->sys_val = val; 526 reg->strict_mask = strict_mask; 527 reg->user_mask = user_mask; 528 } 529 530 extern const struct arm64_cpu_capabilities arm64_errata[]; 531 static const struct arm64_cpu_capabilities arm64_features[]; 532 533 static void __init 534 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 535 { 536 for (; caps->matches; caps++) { 537 if (WARN(caps->capability >= ARM64_NCAPS, 538 "Invalid capability %d\n", caps->capability)) 539 continue; 540 if (WARN(cpu_hwcaps_ptrs[caps->capability], 541 "Duplicate entry for capability %d\n", 542 caps->capability)) 543 continue; 544 cpu_hwcaps_ptrs[caps->capability] = caps; 545 } 546 } 547 548 static void __init init_cpu_hwcaps_indirect_list(void) 549 { 550 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 551 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 552 } 553 554 static void __init setup_boot_cpu_capabilities(void); 555 556 void __init init_cpu_features(struct cpuinfo_arm64 *info) 557 { 558 /* Before we start using the tables, make sure it is sorted */ 559 sort_ftr_regs(); 560 561 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 562 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 563 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 564 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 565 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 566 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 567 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 568 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 569 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 570 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 571 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 572 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 573 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 574 575 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 576 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 577 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 578 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 579 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 580 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 581 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 582 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 583 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 584 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 585 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 586 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 587 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 588 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 589 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 590 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 591 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 592 } 593 594 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 595 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 596 sve_init_vq_map(); 597 } 598 599 /* 600 * Initialize the indirect array of CPU hwcaps capabilities pointers 601 * before we handle the boot CPU below. 602 */ 603 init_cpu_hwcaps_indirect_list(); 604 605 /* 606 * Detect and enable early CPU capabilities based on the boot CPU, 607 * after we have initialised the CPU feature infrastructure. 608 */ 609 setup_boot_cpu_capabilities(); 610 } 611 612 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 613 { 614 const struct arm64_ftr_bits *ftrp; 615 616 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 617 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 618 s64 ftr_new = arm64_ftr_value(ftrp, new); 619 620 if (ftr_cur == ftr_new) 621 continue; 622 /* Find a safe value */ 623 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 624 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 625 } 626 627 } 628 629 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 630 { 631 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 632 633 BUG_ON(!regp); 634 update_cpu_ftr_reg(regp, val); 635 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 636 return 0; 637 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 638 regp->name, boot, cpu, val); 639 return 1; 640 } 641 642 /* 643 * Update system wide CPU feature registers with the values from a 644 * non-boot CPU. Also performs SANITY checks to make sure that there 645 * aren't any insane variations from that of the boot CPU. 646 */ 647 void update_cpu_features(int cpu, 648 struct cpuinfo_arm64 *info, 649 struct cpuinfo_arm64 *boot) 650 { 651 int taint = 0; 652 653 /* 654 * The kernel can handle differing I-cache policies, but otherwise 655 * caches should look identical. Userspace JITs will make use of 656 * *minLine. 657 */ 658 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 659 info->reg_ctr, boot->reg_ctr); 660 661 /* 662 * Userspace may perform DC ZVA instructions. Mismatched block sizes 663 * could result in too much or too little memory being zeroed if a 664 * process is preempted and migrated between CPUs. 665 */ 666 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 667 info->reg_dczid, boot->reg_dczid); 668 669 /* If different, timekeeping will be broken (especially with KVM) */ 670 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 671 info->reg_cntfrq, boot->reg_cntfrq); 672 673 /* 674 * The kernel uses self-hosted debug features and expects CPUs to 675 * support identical debug features. We presently need CTX_CMPs, WRPs, 676 * and BRPs to be identical. 677 * ID_AA64DFR1 is currently RES0. 678 */ 679 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 680 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 681 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 682 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 683 /* 684 * Even in big.LITTLE, processors should be identical instruction-set 685 * wise. 686 */ 687 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 688 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 689 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 690 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 691 692 /* 693 * Differing PARange support is fine as long as all peripherals and 694 * memory are mapped within the minimum PARange of all CPUs. 695 * Linux should not care about secure memory. 696 */ 697 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 698 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 699 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 700 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 701 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 702 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 703 704 /* 705 * EL3 is not our concern. 706 */ 707 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 708 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 709 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 710 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 711 712 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 713 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 714 715 /* 716 * If we have AArch32, we care about 32-bit features for compat. 717 * If the system doesn't support AArch32, don't update them. 718 */ 719 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 720 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 721 722 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 723 info->reg_id_dfr0, boot->reg_id_dfr0); 724 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 725 info->reg_id_isar0, boot->reg_id_isar0); 726 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 727 info->reg_id_isar1, boot->reg_id_isar1); 728 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 729 info->reg_id_isar2, boot->reg_id_isar2); 730 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 731 info->reg_id_isar3, boot->reg_id_isar3); 732 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 733 info->reg_id_isar4, boot->reg_id_isar4); 734 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 735 info->reg_id_isar5, boot->reg_id_isar5); 736 737 /* 738 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 739 * ACTLR formats could differ across CPUs and therefore would have to 740 * be trapped for virtualization anyway. 741 */ 742 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 743 info->reg_id_mmfr0, boot->reg_id_mmfr0); 744 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 745 info->reg_id_mmfr1, boot->reg_id_mmfr1); 746 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 747 info->reg_id_mmfr2, boot->reg_id_mmfr2); 748 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 749 info->reg_id_mmfr3, boot->reg_id_mmfr3); 750 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 751 info->reg_id_pfr0, boot->reg_id_pfr0); 752 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 753 info->reg_id_pfr1, boot->reg_id_pfr1); 754 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 755 info->reg_mvfr0, boot->reg_mvfr0); 756 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 757 info->reg_mvfr1, boot->reg_mvfr1); 758 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 759 info->reg_mvfr2, boot->reg_mvfr2); 760 } 761 762 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 763 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 764 info->reg_zcr, boot->reg_zcr); 765 766 /* Probe vector lengths, unless we already gave up on SVE */ 767 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 768 !sys_caps_initialised) 769 sve_update_vq_map(); 770 } 771 772 /* 773 * Mismatched CPU features are a recipe for disaster. Don't even 774 * pretend to support them. 775 */ 776 if (taint) { 777 pr_warn_once("Unsupported CPU feature variation detected.\n"); 778 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 779 } 780 } 781 782 u64 read_sanitised_ftr_reg(u32 id) 783 { 784 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 785 786 /* We shouldn't get a request for an unsupported register */ 787 BUG_ON(!regp); 788 return regp->sys_val; 789 } 790 791 #define read_sysreg_case(r) \ 792 case r: return read_sysreg_s(r) 793 794 /* 795 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 796 * Read the system register on the current CPU 797 */ 798 static u64 __read_sysreg_by_encoding(u32 sys_id) 799 { 800 switch (sys_id) { 801 read_sysreg_case(SYS_ID_PFR0_EL1); 802 read_sysreg_case(SYS_ID_PFR1_EL1); 803 read_sysreg_case(SYS_ID_DFR0_EL1); 804 read_sysreg_case(SYS_ID_MMFR0_EL1); 805 read_sysreg_case(SYS_ID_MMFR1_EL1); 806 read_sysreg_case(SYS_ID_MMFR2_EL1); 807 read_sysreg_case(SYS_ID_MMFR3_EL1); 808 read_sysreg_case(SYS_ID_ISAR0_EL1); 809 read_sysreg_case(SYS_ID_ISAR1_EL1); 810 read_sysreg_case(SYS_ID_ISAR2_EL1); 811 read_sysreg_case(SYS_ID_ISAR3_EL1); 812 read_sysreg_case(SYS_ID_ISAR4_EL1); 813 read_sysreg_case(SYS_ID_ISAR5_EL1); 814 read_sysreg_case(SYS_MVFR0_EL1); 815 read_sysreg_case(SYS_MVFR1_EL1); 816 read_sysreg_case(SYS_MVFR2_EL1); 817 818 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 819 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 820 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 821 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 822 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 823 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 824 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 825 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 826 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 827 828 read_sysreg_case(SYS_CNTFRQ_EL0); 829 read_sysreg_case(SYS_CTR_EL0); 830 read_sysreg_case(SYS_DCZID_EL0); 831 832 default: 833 BUG(); 834 return 0; 835 } 836 } 837 838 #include <linux/irqchip/arm-gic-v3.h> 839 840 static bool 841 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 842 { 843 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 844 845 return val >= entry->min_field_value; 846 } 847 848 static bool 849 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 850 { 851 u64 val; 852 853 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 854 if (scope == SCOPE_SYSTEM) 855 val = read_sanitised_ftr_reg(entry->sys_reg); 856 else 857 val = __read_sysreg_by_encoding(entry->sys_reg); 858 859 return feature_matches(val, entry); 860 } 861 862 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 863 { 864 bool has_sre; 865 866 if (!has_cpuid_feature(entry, scope)) 867 return false; 868 869 has_sre = gic_enable_sre(); 870 if (!has_sre) 871 pr_warn_once("%s present but disabled by higher exception level\n", 872 entry->desc); 873 874 return has_sre; 875 } 876 877 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 878 { 879 u32 midr = read_cpuid_id(); 880 881 /* Cavium ThunderX pass 1.x and 2.x */ 882 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, 883 MIDR_CPU_VAR_REV(0, 0), 884 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 885 } 886 887 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 888 { 889 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 890 891 return cpuid_feature_extract_signed_field(pfr0, 892 ID_AA64PFR0_FP_SHIFT) < 0; 893 } 894 895 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 896 int scope) 897 { 898 u64 ctr; 899 900 if (scope == SCOPE_SYSTEM) 901 ctr = arm64_ftr_reg_ctrel0.sys_val; 902 else 903 ctr = read_cpuid_effective_cachetype(); 904 905 return ctr & BIT(CTR_IDC_SHIFT); 906 } 907 908 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 909 { 910 /* 911 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 912 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 913 * to the CTR_EL0 on this CPU and emulate it with the real/safe 914 * value. 915 */ 916 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 917 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 918 } 919 920 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 921 int scope) 922 { 923 u64 ctr; 924 925 if (scope == SCOPE_SYSTEM) 926 ctr = arm64_ftr_reg_ctrel0.sys_val; 927 else 928 ctr = read_cpuid_cachetype(); 929 930 return ctr & BIT(CTR_DIC_SHIFT); 931 } 932 933 static bool __maybe_unused 934 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 935 { 936 /* 937 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 938 * may share TLB entries with a CPU stuck in the crashed 939 * kernel. 940 */ 941 if (is_kdump_kernel()) 942 return false; 943 944 return has_cpuid_feature(entry, scope); 945 } 946 947 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 948 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 949 950 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 951 int scope) 952 { 953 /* List of CPUs that are not vulnerable and don't need KPTI */ 954 static const struct midr_range kpti_safe_list[] = { 955 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 956 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 957 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 958 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 959 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 960 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 961 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 962 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 963 { /* sentinel */ } 964 }; 965 char const *str = "command line option"; 966 967 /* 968 * For reasons that aren't entirely clear, enabling KPTI on Cavium 969 * ThunderX leads to apparent I-cache corruption of kernel text, which 970 * ends as well as you might imagine. Don't even try. 971 */ 972 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 973 str = "ARM64_WORKAROUND_CAVIUM_27456"; 974 __kpti_forced = -1; 975 } 976 977 /* Forced? */ 978 if (__kpti_forced) { 979 pr_info_once("kernel page table isolation forced %s by %s\n", 980 __kpti_forced > 0 ? "ON" : "OFF", str); 981 return __kpti_forced > 0; 982 } 983 984 /* Useful for KASLR robustness */ 985 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 986 return kaslr_offset() > 0; 987 988 /* Don't force KPTI for CPUs that are not vulnerable */ 989 if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list)) 990 return false; 991 992 /* Defer to CPU feature registers */ 993 return !has_cpuid_feature(entry, scope); 994 } 995 996 static void 997 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 998 { 999 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1000 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1001 kpti_remap_fn *remap_fn; 1002 1003 static bool kpti_applied = false; 1004 int cpu = smp_processor_id(); 1005 1006 /* 1007 * We don't need to rewrite the page-tables if either we've done 1008 * it already or we have KASLR enabled and therefore have not 1009 * created any global mappings at all. 1010 */ 1011 if (kpti_applied || kaslr_offset() > 0) 1012 return; 1013 1014 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1015 1016 cpu_install_idmap(); 1017 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1018 cpu_uninstall_idmap(); 1019 1020 if (!cpu) 1021 kpti_applied = true; 1022 1023 return; 1024 } 1025 1026 static int __init parse_kpti(char *str) 1027 { 1028 bool enabled; 1029 int ret = strtobool(str, &enabled); 1030 1031 if (ret) 1032 return ret; 1033 1034 __kpti_forced = enabled ? 1 : -1; 1035 return 0; 1036 } 1037 early_param("kpti", parse_kpti); 1038 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1039 1040 #ifdef CONFIG_ARM64_HW_AFDBM 1041 static inline void __cpu_enable_hw_dbm(void) 1042 { 1043 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1044 1045 write_sysreg(tcr, tcr_el1); 1046 isb(); 1047 } 1048 1049 static bool cpu_has_broken_dbm(void) 1050 { 1051 /* List of CPUs which have broken DBM support. */ 1052 static const struct midr_range cpus[] = { 1053 #ifdef CONFIG_ARM64_ERRATUM_1024718 1054 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 1055 #endif 1056 {}, 1057 }; 1058 1059 return is_midr_in_range_list(read_cpuid_id(), cpus); 1060 } 1061 1062 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1063 { 1064 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1065 !cpu_has_broken_dbm(); 1066 } 1067 1068 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1069 { 1070 if (cpu_can_use_dbm(cap)) 1071 __cpu_enable_hw_dbm(); 1072 } 1073 1074 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1075 int __unused) 1076 { 1077 static bool detected = false; 1078 /* 1079 * DBM is a non-conflicting feature. i.e, the kernel can safely 1080 * run a mix of CPUs with and without the feature. So, we 1081 * unconditionally enable the capability to allow any late CPU 1082 * to use the feature. We only enable the control bits on the 1083 * CPU, if it actually supports. 1084 * 1085 * We have to make sure we print the "feature" detection only 1086 * when at least one CPU actually uses it. So check if this CPU 1087 * can actually use it and print the message exactly once. 1088 * 1089 * This is safe as all CPUs (including secondary CPUs - due to the 1090 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1091 * goes through the "matches" check exactly once. Also if a CPU 1092 * matches the criteria, it is guaranteed that the CPU will turn 1093 * the DBM on, as the capability is unconditionally enabled. 1094 */ 1095 if (!detected && cpu_can_use_dbm(cap)) { 1096 detected = true; 1097 pr_info("detected: Hardware dirty bit management\n"); 1098 } 1099 1100 return true; 1101 } 1102 1103 #endif 1104 1105 #ifdef CONFIG_ARM64_VHE 1106 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1107 { 1108 return is_kernel_in_hyp_mode(); 1109 } 1110 1111 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1112 { 1113 /* 1114 * Copy register values that aren't redirected by hardware. 1115 * 1116 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1117 * this value to tpidr_el2 before we patch the code. Once we've done 1118 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1119 * do anything here. 1120 */ 1121 if (!alternatives_applied) 1122 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1123 } 1124 #endif 1125 1126 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1127 { 1128 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1129 1130 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1131 WARN_ON(val & (7 << 27 | 7 << 21)); 1132 } 1133 1134 #ifdef CONFIG_ARM64_SSBD 1135 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr) 1136 { 1137 if (user_mode(regs)) 1138 return 1; 1139 1140 if (instr & BIT(PSTATE_Imm_shift)) 1141 regs->pstate |= PSR_SSBS_BIT; 1142 else 1143 regs->pstate &= ~PSR_SSBS_BIT; 1144 1145 arm64_skip_faulting_instruction(regs, 4); 1146 return 0; 1147 } 1148 1149 static struct undef_hook ssbs_emulation_hook = { 1150 .instr_mask = ~(1U << PSTATE_Imm_shift), 1151 .instr_val = 0xd500401f | PSTATE_SSBS, 1152 .fn = ssbs_emulation_handler, 1153 }; 1154 1155 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused) 1156 { 1157 static bool undef_hook_registered = false; 1158 static DEFINE_SPINLOCK(hook_lock); 1159 1160 spin_lock(&hook_lock); 1161 if (!undef_hook_registered) { 1162 register_undef_hook(&ssbs_emulation_hook); 1163 undef_hook_registered = true; 1164 } 1165 spin_unlock(&hook_lock); 1166 1167 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) { 1168 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS); 1169 arm64_set_ssbd_mitigation(false); 1170 } else { 1171 arm64_set_ssbd_mitigation(true); 1172 } 1173 } 1174 #endif /* CONFIG_ARM64_SSBD */ 1175 1176 #ifdef CONFIG_ARM64_PAN 1177 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1178 { 1179 /* 1180 * We modify PSTATE. This won't work from irq context as the PSTATE 1181 * is discarded once we return from the exception. 1182 */ 1183 WARN_ON_ONCE(in_interrupt()); 1184 1185 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1186 asm(SET_PSTATE_PAN(1)); 1187 } 1188 #endif /* CONFIG_ARM64_PAN */ 1189 1190 #ifdef CONFIG_ARM64_RAS_EXTN 1191 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1192 { 1193 /* Firmware may have left a deferred SError in this register. */ 1194 write_sysreg_s(0, SYS_DISR_EL1); 1195 } 1196 #endif /* CONFIG_ARM64_RAS_EXTN */ 1197 1198 #ifdef CONFIG_ARM64_PTR_AUTH 1199 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap) 1200 { 1201 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | 1202 SCTLR_ELx_ENDA | SCTLR_ELx_ENDB); 1203 } 1204 #endif /* CONFIG_ARM64_PTR_AUTH */ 1205 1206 static const struct arm64_cpu_capabilities arm64_features[] = { 1207 { 1208 .desc = "GIC system register CPU interface", 1209 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1210 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1211 .matches = has_useable_gicv3_cpuif, 1212 .sys_reg = SYS_ID_AA64PFR0_EL1, 1213 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1214 .sign = FTR_UNSIGNED, 1215 .min_field_value = 1, 1216 }, 1217 #ifdef CONFIG_ARM64_PAN 1218 { 1219 .desc = "Privileged Access Never", 1220 .capability = ARM64_HAS_PAN, 1221 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1222 .matches = has_cpuid_feature, 1223 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1224 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1225 .sign = FTR_UNSIGNED, 1226 .min_field_value = 1, 1227 .cpu_enable = cpu_enable_pan, 1228 }, 1229 #endif /* CONFIG_ARM64_PAN */ 1230 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS) 1231 { 1232 .desc = "LSE atomic instructions", 1233 .capability = ARM64_HAS_LSE_ATOMICS, 1234 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1235 .matches = has_cpuid_feature, 1236 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1237 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1238 .sign = FTR_UNSIGNED, 1239 .min_field_value = 2, 1240 }, 1241 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */ 1242 { 1243 .desc = "Software prefetching using PRFM", 1244 .capability = ARM64_HAS_NO_HW_PREFETCH, 1245 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1246 .matches = has_no_hw_prefetch, 1247 }, 1248 #ifdef CONFIG_ARM64_UAO 1249 { 1250 .desc = "User Access Override", 1251 .capability = ARM64_HAS_UAO, 1252 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1253 .matches = has_cpuid_feature, 1254 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1255 .field_pos = ID_AA64MMFR2_UAO_SHIFT, 1256 .min_field_value = 1, 1257 /* 1258 * We rely on stop_machine() calling uao_thread_switch() to set 1259 * UAO immediately after patching. 1260 */ 1261 }, 1262 #endif /* CONFIG_ARM64_UAO */ 1263 #ifdef CONFIG_ARM64_PAN 1264 { 1265 .capability = ARM64_ALT_PAN_NOT_UAO, 1266 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1267 .matches = cpufeature_pan_not_uao, 1268 }, 1269 #endif /* CONFIG_ARM64_PAN */ 1270 #ifdef CONFIG_ARM64_VHE 1271 { 1272 .desc = "Virtualization Host Extensions", 1273 .capability = ARM64_HAS_VIRT_HOST_EXTN, 1274 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1275 .matches = runs_at_el2, 1276 .cpu_enable = cpu_copy_el2regs, 1277 }, 1278 #endif /* CONFIG_ARM64_VHE */ 1279 { 1280 .desc = "32-bit EL0 Support", 1281 .capability = ARM64_HAS_32BIT_EL0, 1282 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1283 .matches = has_cpuid_feature, 1284 .sys_reg = SYS_ID_AA64PFR0_EL1, 1285 .sign = FTR_UNSIGNED, 1286 .field_pos = ID_AA64PFR0_EL0_SHIFT, 1287 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 1288 }, 1289 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1290 { 1291 .desc = "Kernel page table isolation (KPTI)", 1292 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 1293 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1294 /* 1295 * The ID feature fields below are used to indicate that 1296 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 1297 * more details. 1298 */ 1299 .sys_reg = SYS_ID_AA64PFR0_EL1, 1300 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 1301 .min_field_value = 1, 1302 .matches = unmap_kernel_at_el0, 1303 .cpu_enable = kpti_install_ng_mappings, 1304 }, 1305 #endif 1306 { 1307 /* FP/SIMD is not implemented */ 1308 .capability = ARM64_HAS_NO_FPSIMD, 1309 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1310 .min_field_value = 0, 1311 .matches = has_no_fpsimd, 1312 }, 1313 #ifdef CONFIG_ARM64_PMEM 1314 { 1315 .desc = "Data cache clean to Point of Persistence", 1316 .capability = ARM64_HAS_DCPOP, 1317 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1318 .matches = has_cpuid_feature, 1319 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1320 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1321 .min_field_value = 1, 1322 }, 1323 #endif 1324 #ifdef CONFIG_ARM64_SVE 1325 { 1326 .desc = "Scalable Vector Extension", 1327 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1328 .capability = ARM64_SVE, 1329 .sys_reg = SYS_ID_AA64PFR0_EL1, 1330 .sign = FTR_UNSIGNED, 1331 .field_pos = ID_AA64PFR0_SVE_SHIFT, 1332 .min_field_value = ID_AA64PFR0_SVE, 1333 .matches = has_cpuid_feature, 1334 .cpu_enable = sve_kernel_enable, 1335 }, 1336 #endif /* CONFIG_ARM64_SVE */ 1337 #ifdef CONFIG_ARM64_RAS_EXTN 1338 { 1339 .desc = "RAS Extension Support", 1340 .capability = ARM64_HAS_RAS_EXTN, 1341 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1342 .matches = has_cpuid_feature, 1343 .sys_reg = SYS_ID_AA64PFR0_EL1, 1344 .sign = FTR_UNSIGNED, 1345 .field_pos = ID_AA64PFR0_RAS_SHIFT, 1346 .min_field_value = ID_AA64PFR0_RAS_V1, 1347 .cpu_enable = cpu_clear_disr, 1348 }, 1349 #endif /* CONFIG_ARM64_RAS_EXTN */ 1350 { 1351 .desc = "Data cache clean to the PoU not required for I/D coherence", 1352 .capability = ARM64_HAS_CACHE_IDC, 1353 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1354 .matches = has_cache_idc, 1355 .cpu_enable = cpu_emulate_effective_ctr, 1356 }, 1357 { 1358 .desc = "Instruction cache invalidation not required for I/D coherence", 1359 .capability = ARM64_HAS_CACHE_DIC, 1360 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1361 .matches = has_cache_dic, 1362 }, 1363 { 1364 .desc = "Stage-2 Force Write-Back", 1365 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1366 .capability = ARM64_HAS_STAGE2_FWB, 1367 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1368 .sign = FTR_UNSIGNED, 1369 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 1370 .min_field_value = 1, 1371 .matches = has_cpuid_feature, 1372 .cpu_enable = cpu_has_fwb, 1373 }, 1374 #ifdef CONFIG_ARM64_HW_AFDBM 1375 { 1376 /* 1377 * Since we turn this on always, we don't want the user to 1378 * think that the feature is available when it may not be. 1379 * So hide the description. 1380 * 1381 * .desc = "Hardware pagetable Dirty Bit Management", 1382 * 1383 */ 1384 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1385 .capability = ARM64_HW_DBM, 1386 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1387 .sign = FTR_UNSIGNED, 1388 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 1389 .min_field_value = 2, 1390 .matches = has_hw_dbm, 1391 .cpu_enable = cpu_enable_hw_dbm, 1392 }, 1393 #endif 1394 { 1395 .desc = "CRC32 instructions", 1396 .capability = ARM64_HAS_CRC32, 1397 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1398 .matches = has_cpuid_feature, 1399 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1400 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 1401 .min_field_value = 1, 1402 }, 1403 #ifdef CONFIG_ARM64_SSBD 1404 { 1405 .desc = "Speculative Store Bypassing Safe (SSBS)", 1406 .capability = ARM64_SSBS, 1407 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1408 .matches = has_cpuid_feature, 1409 .sys_reg = SYS_ID_AA64PFR1_EL1, 1410 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 1411 .sign = FTR_UNSIGNED, 1412 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 1413 .cpu_enable = cpu_enable_ssbs, 1414 }, 1415 #endif 1416 #ifdef CONFIG_ARM64_CNP 1417 { 1418 .desc = "Common not Private translations", 1419 .capability = ARM64_HAS_CNP, 1420 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1421 .matches = has_useable_cnp, 1422 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1423 .sign = FTR_UNSIGNED, 1424 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 1425 .min_field_value = 1, 1426 .cpu_enable = cpu_enable_cnp, 1427 }, 1428 #endif 1429 { 1430 .desc = "Speculation barrier (SB)", 1431 .capability = ARM64_HAS_SB, 1432 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1433 .matches = has_cpuid_feature, 1434 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1435 .field_pos = ID_AA64ISAR1_SB_SHIFT, 1436 .sign = FTR_UNSIGNED, 1437 .min_field_value = 1, 1438 }, 1439 #ifdef CONFIG_ARM64_PTR_AUTH 1440 { 1441 .desc = "Address authentication (architected algorithm)", 1442 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 1443 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1444 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1445 .sign = FTR_UNSIGNED, 1446 .field_pos = ID_AA64ISAR1_APA_SHIFT, 1447 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 1448 .matches = has_cpuid_feature, 1449 .cpu_enable = cpu_enable_address_auth, 1450 }, 1451 { 1452 .desc = "Address authentication (IMP DEF algorithm)", 1453 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 1454 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1455 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1456 .sign = FTR_UNSIGNED, 1457 .field_pos = ID_AA64ISAR1_API_SHIFT, 1458 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 1459 .matches = has_cpuid_feature, 1460 .cpu_enable = cpu_enable_address_auth, 1461 }, 1462 { 1463 .desc = "Generic authentication (architected algorithm)", 1464 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 1465 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1466 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1467 .sign = FTR_UNSIGNED, 1468 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 1469 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 1470 .matches = has_cpuid_feature, 1471 }, 1472 { 1473 .desc = "Generic authentication (IMP DEF algorithm)", 1474 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 1475 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1476 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1477 .sign = FTR_UNSIGNED, 1478 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 1479 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 1480 .matches = has_cpuid_feature, 1481 }, 1482 #endif /* CONFIG_ARM64_PTR_AUTH */ 1483 {}, 1484 }; 1485 1486 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 1487 .matches = has_cpuid_feature, \ 1488 .sys_reg = reg, \ 1489 .field_pos = field, \ 1490 .sign = s, \ 1491 .min_field_value = min_value, 1492 1493 #define __HWCAP_CAP(name, cap_type, cap) \ 1494 .desc = name, \ 1495 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 1496 .hwcap_type = cap_type, \ 1497 .hwcap = cap, \ 1498 1499 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 1500 { \ 1501 __HWCAP_CAP(#cap, cap_type, cap) \ 1502 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 1503 } 1504 1505 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 1506 { \ 1507 __HWCAP_CAP(#cap, cap_type, cap) \ 1508 .matches = cpucap_multi_entry_cap_matches, \ 1509 .match_list = list, \ 1510 } 1511 1512 #ifdef CONFIG_ARM64_PTR_AUTH 1513 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 1514 { 1515 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 1516 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 1517 }, 1518 { 1519 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 1520 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 1521 }, 1522 {}, 1523 }; 1524 1525 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 1526 { 1527 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 1528 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 1529 }, 1530 { 1531 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 1532 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 1533 }, 1534 {}, 1535 }; 1536 #endif 1537 1538 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 1539 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL), 1540 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES), 1541 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1), 1542 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2), 1543 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512), 1544 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32), 1545 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS), 1546 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM), 1547 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3), 1548 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3), 1549 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4), 1550 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP), 1551 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM), 1552 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM), 1553 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP), 1554 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP), 1555 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD), 1556 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP), 1557 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT), 1558 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP), 1559 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT), 1560 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), 1561 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC), 1562 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC), 1563 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SB), 1564 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT), 1565 #ifdef CONFIG_ARM64_SVE 1566 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE), 1567 #endif 1568 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS), 1569 #ifdef CONFIG_ARM64_PTR_AUTH 1570 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, HWCAP_PACA), 1571 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, HWCAP_PACG), 1572 #endif 1573 {}, 1574 }; 1575 1576 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 1577 #ifdef CONFIG_COMPAT 1578 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 1579 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 1580 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 1581 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 1582 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 1583 #endif 1584 {}, 1585 }; 1586 1587 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 1588 { 1589 switch (cap->hwcap_type) { 1590 case CAP_HWCAP: 1591 elf_hwcap |= cap->hwcap; 1592 break; 1593 #ifdef CONFIG_COMPAT 1594 case CAP_COMPAT_HWCAP: 1595 compat_elf_hwcap |= (u32)cap->hwcap; 1596 break; 1597 case CAP_COMPAT_HWCAP2: 1598 compat_elf_hwcap2 |= (u32)cap->hwcap; 1599 break; 1600 #endif 1601 default: 1602 WARN_ON(1); 1603 break; 1604 } 1605 } 1606 1607 /* Check if we have a particular HWCAP enabled */ 1608 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 1609 { 1610 bool rc; 1611 1612 switch (cap->hwcap_type) { 1613 case CAP_HWCAP: 1614 rc = (elf_hwcap & cap->hwcap) != 0; 1615 break; 1616 #ifdef CONFIG_COMPAT 1617 case CAP_COMPAT_HWCAP: 1618 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 1619 break; 1620 case CAP_COMPAT_HWCAP2: 1621 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 1622 break; 1623 #endif 1624 default: 1625 WARN_ON(1); 1626 rc = false; 1627 } 1628 1629 return rc; 1630 } 1631 1632 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 1633 { 1634 /* We support emulation of accesses to CPU ID feature registers */ 1635 elf_hwcap |= HWCAP_CPUID; 1636 for (; hwcaps->matches; hwcaps++) 1637 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 1638 cap_set_elf_hwcap(hwcaps); 1639 } 1640 1641 static void update_cpu_capabilities(u16 scope_mask) 1642 { 1643 int i; 1644 const struct arm64_cpu_capabilities *caps; 1645 1646 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 1647 for (i = 0; i < ARM64_NCAPS; i++) { 1648 caps = cpu_hwcaps_ptrs[i]; 1649 if (!caps || !(caps->type & scope_mask) || 1650 cpus_have_cap(caps->capability) || 1651 !caps->matches(caps, cpucap_default_scope(caps))) 1652 continue; 1653 1654 if (caps->desc) 1655 pr_info("detected: %s\n", caps->desc); 1656 cpus_set_cap(caps->capability); 1657 } 1658 } 1659 1660 /* 1661 * Enable all the available capabilities on this CPU. The capabilities 1662 * with BOOT_CPU scope are handled separately and hence skipped here. 1663 */ 1664 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 1665 { 1666 int i; 1667 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 1668 1669 for_each_available_cap(i) { 1670 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 1671 1672 if (WARN_ON(!cap)) 1673 continue; 1674 1675 if (!(cap->type & non_boot_scope)) 1676 continue; 1677 1678 if (cap->cpu_enable) 1679 cap->cpu_enable(cap); 1680 } 1681 return 0; 1682 } 1683 1684 /* 1685 * Run through the enabled capabilities and enable() it on all active 1686 * CPUs 1687 */ 1688 static void __init enable_cpu_capabilities(u16 scope_mask) 1689 { 1690 int i; 1691 const struct arm64_cpu_capabilities *caps; 1692 bool boot_scope; 1693 1694 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 1695 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 1696 1697 for (i = 0; i < ARM64_NCAPS; i++) { 1698 unsigned int num; 1699 1700 caps = cpu_hwcaps_ptrs[i]; 1701 if (!caps || !(caps->type & scope_mask)) 1702 continue; 1703 num = caps->capability; 1704 if (!cpus_have_cap(num)) 1705 continue; 1706 1707 /* Ensure cpus_have_const_cap(num) works */ 1708 static_branch_enable(&cpu_hwcap_keys[num]); 1709 1710 if (boot_scope && caps->cpu_enable) 1711 /* 1712 * Capabilities with SCOPE_BOOT_CPU scope are finalised 1713 * before any secondary CPU boots. Thus, each secondary 1714 * will enable the capability as appropriate via 1715 * check_local_cpu_capabilities(). The only exception is 1716 * the boot CPU, for which the capability must be 1717 * enabled here. This approach avoids costly 1718 * stop_machine() calls for this case. 1719 */ 1720 caps->cpu_enable(caps); 1721 } 1722 1723 /* 1724 * For all non-boot scope capabilities, use stop_machine() 1725 * as it schedules the work allowing us to modify PSTATE, 1726 * instead of on_each_cpu() which uses an IPI, giving us a 1727 * PSTATE that disappears when we return. 1728 */ 1729 if (!boot_scope) 1730 stop_machine(cpu_enable_non_boot_scope_capabilities, 1731 NULL, cpu_online_mask); 1732 } 1733 1734 /* 1735 * Run through the list of capabilities to check for conflicts. 1736 * If the system has already detected a capability, take necessary 1737 * action on this CPU. 1738 * 1739 * Returns "false" on conflicts. 1740 */ 1741 static bool verify_local_cpu_caps(u16 scope_mask) 1742 { 1743 int i; 1744 bool cpu_has_cap, system_has_cap; 1745 const struct arm64_cpu_capabilities *caps; 1746 1747 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 1748 1749 for (i = 0; i < ARM64_NCAPS; i++) { 1750 caps = cpu_hwcaps_ptrs[i]; 1751 if (!caps || !(caps->type & scope_mask)) 1752 continue; 1753 1754 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 1755 system_has_cap = cpus_have_cap(caps->capability); 1756 1757 if (system_has_cap) { 1758 /* 1759 * Check if the new CPU misses an advertised feature, 1760 * which is not safe to miss. 1761 */ 1762 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 1763 break; 1764 /* 1765 * We have to issue cpu_enable() irrespective of 1766 * whether the CPU has it or not, as it is enabeld 1767 * system wide. It is upto the call back to take 1768 * appropriate action on this CPU. 1769 */ 1770 if (caps->cpu_enable) 1771 caps->cpu_enable(caps); 1772 } else { 1773 /* 1774 * Check if the CPU has this capability if it isn't 1775 * safe to have when the system doesn't. 1776 */ 1777 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 1778 break; 1779 } 1780 } 1781 1782 if (i < ARM64_NCAPS) { 1783 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 1784 smp_processor_id(), caps->capability, 1785 caps->desc, system_has_cap, cpu_has_cap); 1786 return false; 1787 } 1788 1789 return true; 1790 } 1791 1792 /* 1793 * Check for CPU features that are used in early boot 1794 * based on the Boot CPU value. 1795 */ 1796 static void check_early_cpu_features(void) 1797 { 1798 verify_cpu_asid_bits(); 1799 /* 1800 * Early features are used by the kernel already. If there 1801 * is a conflict, we cannot proceed further. 1802 */ 1803 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU)) 1804 cpu_panic_kernel(); 1805 } 1806 1807 static void 1808 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 1809 { 1810 1811 for (; caps->matches; caps++) 1812 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 1813 pr_crit("CPU%d: missing HWCAP: %s\n", 1814 smp_processor_id(), caps->desc); 1815 cpu_die_early(); 1816 } 1817 } 1818 1819 static void verify_sve_features(void) 1820 { 1821 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 1822 u64 zcr = read_zcr_features(); 1823 1824 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 1825 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 1826 1827 if (len < safe_len || sve_verify_vq_map()) { 1828 pr_crit("CPU%d: SVE: required vector length(s) missing\n", 1829 smp_processor_id()); 1830 cpu_die_early(); 1831 } 1832 1833 /* Add checks on other ZCR bits here if necessary */ 1834 } 1835 1836 1837 /* 1838 * Run through the enabled system capabilities and enable() it on this CPU. 1839 * The capabilities were decided based on the available CPUs at the boot time. 1840 * Any new CPU should match the system wide status of the capability. If the 1841 * new CPU doesn't have a capability which the system now has enabled, we 1842 * cannot do anything to fix it up and could cause unexpected failures. So 1843 * we park the CPU. 1844 */ 1845 static void verify_local_cpu_capabilities(void) 1846 { 1847 /* 1848 * The capabilities with SCOPE_BOOT_CPU are checked from 1849 * check_early_cpu_features(), as they need to be verified 1850 * on all secondary CPUs. 1851 */ 1852 if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU)) 1853 cpu_die_early(); 1854 1855 verify_local_elf_hwcaps(arm64_elf_hwcaps); 1856 1857 if (system_supports_32bit_el0()) 1858 verify_local_elf_hwcaps(compat_elf_hwcaps); 1859 1860 if (system_supports_sve()) 1861 verify_sve_features(); 1862 } 1863 1864 void check_local_cpu_capabilities(void) 1865 { 1866 /* 1867 * All secondary CPUs should conform to the early CPU features 1868 * in use by the kernel based on boot CPU. 1869 */ 1870 check_early_cpu_features(); 1871 1872 /* 1873 * If we haven't finalised the system capabilities, this CPU gets 1874 * a chance to update the errata work arounds and local features. 1875 * Otherwise, this CPU should verify that it has all the system 1876 * advertised capabilities. 1877 */ 1878 if (!sys_caps_initialised) 1879 update_cpu_capabilities(SCOPE_LOCAL_CPU); 1880 else 1881 verify_local_cpu_capabilities(); 1882 } 1883 1884 static void __init setup_boot_cpu_capabilities(void) 1885 { 1886 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 1887 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 1888 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 1889 enable_cpu_capabilities(SCOPE_BOOT_CPU); 1890 } 1891 1892 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 1893 EXPORT_SYMBOL(arm64_const_caps_ready); 1894 1895 static void __init mark_const_caps_ready(void) 1896 { 1897 static_branch_enable(&arm64_const_caps_ready); 1898 } 1899 1900 bool this_cpu_has_cap(unsigned int n) 1901 { 1902 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 1903 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 1904 1905 if (cap) 1906 return cap->matches(cap, SCOPE_LOCAL_CPU); 1907 } 1908 1909 return false; 1910 } 1911 1912 static void __init setup_system_capabilities(void) 1913 { 1914 /* 1915 * We have finalised the system-wide safe feature 1916 * registers, finalise the capabilities that depend 1917 * on it. Also enable all the available capabilities, 1918 * that are not enabled already. 1919 */ 1920 update_cpu_capabilities(SCOPE_SYSTEM); 1921 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 1922 } 1923 1924 void __init setup_cpu_features(void) 1925 { 1926 u32 cwg; 1927 1928 setup_system_capabilities(); 1929 mark_const_caps_ready(); 1930 setup_elf_hwcaps(arm64_elf_hwcaps); 1931 1932 if (system_supports_32bit_el0()) 1933 setup_elf_hwcaps(compat_elf_hwcaps); 1934 1935 if (system_uses_ttbr0_pan()) 1936 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 1937 1938 sve_setup(); 1939 minsigstksz_setup(); 1940 1941 /* Advertise that we have computed the system capabilities */ 1942 set_sys_caps_initialised(); 1943 1944 /* 1945 * Check for sane CTR_EL0.CWG value. 1946 */ 1947 cwg = cache_type_cwg(); 1948 if (!cwg) 1949 pr_warn("No Cache Writeback Granule information, assuming %d\n", 1950 ARCH_DMA_MINALIGN); 1951 } 1952 1953 static bool __maybe_unused 1954 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) 1955 { 1956 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO)); 1957 } 1958 1959 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 1960 { 1961 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 1962 } 1963 1964 /* 1965 * We emulate only the following system register space. 1966 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 1967 * See Table C5-6 System instruction encodings for System register accesses, 1968 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 1969 */ 1970 static inline bool __attribute_const__ is_emulated(u32 id) 1971 { 1972 return (sys_reg_Op0(id) == 0x3 && 1973 sys_reg_CRn(id) == 0x0 && 1974 sys_reg_Op1(id) == 0x0 && 1975 (sys_reg_CRm(id) == 0 || 1976 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 1977 } 1978 1979 /* 1980 * With CRm == 0, reg should be one of : 1981 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 1982 */ 1983 static inline int emulate_id_reg(u32 id, u64 *valp) 1984 { 1985 switch (id) { 1986 case SYS_MIDR_EL1: 1987 *valp = read_cpuid_id(); 1988 break; 1989 case SYS_MPIDR_EL1: 1990 *valp = SYS_MPIDR_SAFE_VAL; 1991 break; 1992 case SYS_REVIDR_EL1: 1993 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 1994 *valp = 0; 1995 break; 1996 default: 1997 return -EINVAL; 1998 } 1999 2000 return 0; 2001 } 2002 2003 static int emulate_sys_reg(u32 id, u64 *valp) 2004 { 2005 struct arm64_ftr_reg *regp; 2006 2007 if (!is_emulated(id)) 2008 return -EINVAL; 2009 2010 if (sys_reg_CRm(id) == 0) 2011 return emulate_id_reg(id, valp); 2012 2013 regp = get_arm64_ftr_reg(id); 2014 if (regp) 2015 *valp = arm64_ftr_reg_user_value(regp); 2016 else 2017 /* 2018 * The untracked registers are either IMPLEMENTATION DEFINED 2019 * (e.g, ID_AFR0_EL1) or reserved RAZ. 2020 */ 2021 *valp = 0; 2022 return 0; 2023 } 2024 2025 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 2026 { 2027 int rc; 2028 u64 val; 2029 2030 rc = emulate_sys_reg(sys_reg, &val); 2031 if (!rc) { 2032 pt_regs_write_reg(regs, rt, val); 2033 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 2034 } 2035 return rc; 2036 } 2037 2038 static int emulate_mrs(struct pt_regs *regs, u32 insn) 2039 { 2040 u32 sys_reg, rt; 2041 2042 /* 2043 * sys_reg values are defined as used in mrs/msr instruction. 2044 * shift the imm value to get the encoding. 2045 */ 2046 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 2047 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 2048 return do_emulate_mrs(regs, sys_reg, rt); 2049 } 2050 2051 static struct undef_hook mrs_hook = { 2052 .instr_mask = 0xfff00000, 2053 .instr_val = 0xd5300000, 2054 .pstate_mask = PSR_AA32_MODE_MASK, 2055 .pstate_val = PSR_MODE_EL0t, 2056 .fn = emulate_mrs, 2057 }; 2058 2059 static int __init enable_mrs_emulation(void) 2060 { 2061 register_undef_hook(&mrs_hook); 2062 return 0; 2063 } 2064 2065 core_initcall(enable_mrs_emulation); 2066