1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/sysfs.h> 71 #include <linux/types.h> 72 #include <linux/minmax.h> 73 #include <linux/mm.h> 74 #include <linux/cpu.h> 75 #include <linux/kasan.h> 76 #include <linux/percpu.h> 77 78 #include <asm/cpu.h> 79 #include <asm/cpufeature.h> 80 #include <asm/cpu_ops.h> 81 #include <asm/fpsimd.h> 82 #include <asm/hwcap.h> 83 #include <asm/insn.h> 84 #include <asm/kvm_host.h> 85 #include <asm/mmu_context.h> 86 #include <asm/mte.h> 87 #include <asm/processor.h> 88 #include <asm/smp.h> 89 #include <asm/sysreg.h> 90 #include <asm/traps.h> 91 #include <asm/vectors.h> 92 #include <asm/virt.h> 93 94 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 95 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 96 97 #ifdef CONFIG_COMPAT 98 #define COMPAT_ELF_HWCAP_DEFAULT \ 99 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 100 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 101 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 102 COMPAT_HWCAP_LPAE) 103 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 104 unsigned int compat_elf_hwcap2 __read_mostly; 105 #endif 106 107 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 108 EXPORT_SYMBOL(cpu_hwcaps); 109 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 110 111 DECLARE_BITMAP(boot_capabilities, ARM64_NCAPS); 112 113 bool arm64_use_ng_mappings = false; 114 EXPORT_SYMBOL(arm64_use_ng_mappings); 115 116 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 117 118 /* 119 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 120 * support it? 121 */ 122 static bool __read_mostly allow_mismatched_32bit_el0; 123 124 /* 125 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 126 * seen at least one CPU capable of 32-bit EL0. 127 */ 128 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 129 130 /* 131 * Mask of CPUs supporting 32-bit EL0. 132 * Only valid if arm64_mismatched_32bit_el0 is enabled. 133 */ 134 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 135 136 void dump_cpu_features(void) 137 { 138 /* file-wide pr_fmt adds "CPU features: " prefix */ 139 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 140 } 141 142 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 143 { \ 144 .sign = SIGNED, \ 145 .visible = VISIBLE, \ 146 .strict = STRICT, \ 147 .type = TYPE, \ 148 .shift = SHIFT, \ 149 .width = WIDTH, \ 150 .safe_val = SAFE_VAL, \ 151 } 152 153 /* Define a feature with unsigned values */ 154 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 155 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 156 157 /* Define a feature with a signed value */ 158 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 159 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 160 161 #define ARM64_FTR_END \ 162 { \ 163 .width = 0, \ 164 } 165 166 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 167 168 static bool __system_matches_cap(unsigned int n); 169 170 /* 171 * NOTE: Any changes to the visibility of features should be kept in 172 * sync with the documentation of the CPU feature register ABI. 173 */ 174 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 175 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 176 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 182 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 184 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 189 ARM64_FTR_END, 190 }; 191 192 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 199 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 200 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 202 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 207 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 208 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 209 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 211 ARM64_FTR_END, 212 }; 213 214 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 215 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 218 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 219 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 220 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 223 ARM64_FTR_END, 224 }; 225 226 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 234 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 237 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 238 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 243 ARM64_FTR_END, 244 }; 245 246 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 247 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 248 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 252 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 256 ARM64_FTR_END, 257 }; 258 259 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 261 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 269 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 271 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 275 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 276 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 277 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 278 ARM64_FTR_END, 279 }; 280 281 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 282 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 283 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 284 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 285 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 286 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 287 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 288 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 289 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 291 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 292 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 293 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 294 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 295 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 296 ARM64_FTR_END, 297 }; 298 299 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 300 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 303 /* 304 * Page size not being supported at Stage-2 is not fatal. You 305 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 306 * your favourite nesting hypervisor. 307 * 308 * There is a small corner case where the hypervisor explicitly 309 * advertises a given granule size at Stage-2 (value 2) on some 310 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 311 * vCPUs. Although this is not forbidden by the architecture, it 312 * indicates that the hypervisor is being silly (or buggy). 313 * 314 * We make no effort to cope with this and pretend that if these 315 * fields are inconsistent across vCPUs, then it isn't worth 316 * trying to bring KVM up. 317 */ 318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 321 /* 322 * We already refuse to boot CPUs that don't support our configured 323 * page size, so we can only detect mismatches for a page size other 324 * than the one we're currently using. Unfortunately, SoCs like this 325 * exist in the wild so, even though we don't like it, we'll have to go 326 * along with it and treat them as non-strict. 327 */ 328 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 329 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 331 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 333 /* Linux shouldn't care about secure memory */ 334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 337 /* 338 * Differing PARange is fine as long as all peripherals and memory are mapped 339 * within the minimum PARange of all CPUs 340 */ 341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 342 ARM64_FTR_END, 343 }; 344 345 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 347 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 357 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 358 ARM64_FTR_END, 359 }; 360 361 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 377 ARM64_FTR_END, 378 }; 379 380 static const struct arm64_ftr_bits ftr_ctr[] = { 381 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 382 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 383 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 384 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 386 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 387 /* 388 * Linux can handle differing I-cache policies. Userspace JITs will 389 * make use of *minLine. 390 * If we have differing I-cache policies, report it as the weakest - VIPT. 391 */ 392 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 393 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 394 ARM64_FTR_END, 395 }; 396 397 static struct arm64_ftr_override __ro_after_init no_override = { }; 398 399 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 400 .name = "SYS_CTR_EL0", 401 .ftr_bits = ftr_ctr, 402 .override = &no_override, 403 }; 404 405 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 406 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 410 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 411 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 414 ARM64_FTR_END, 415 }; 416 417 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 418 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 419 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 423 /* 424 * We can instantiate multiple PMU instances with different levels 425 * of support. 426 */ 427 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 429 ARM64_FTR_END, 430 }; 431 432 static const struct arm64_ftr_bits ftr_mvfr0[] = { 433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPROUND_SHIFT, 4, 0), 434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSHVEC_SHIFT, 4, 0), 435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSQRT_SHIFT, 4, 0), 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDIVIDE_SHIFT, 4, 0), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPTRAP_SHIFT, 4, 0), 438 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDP_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSP_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_SIMD_SHIFT, 4, 0), 441 ARM64_FTR_END, 442 }; 443 444 static const struct arm64_ftr_bits ftr_mvfr1[] = { 445 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDFMAC_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDSP_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDINT_SHIFT, 4, 0), 450 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDLS_SHIFT, 4, 0), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPDNAN_SHIFT, 4, 0), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPFTZ_SHIFT, 4, 0), 453 ARM64_FTR_END, 454 }; 455 456 static const struct arm64_ftr_bits ftr_mvfr2[] = { 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 459 ARM64_FTR_END, 460 }; 461 462 static const struct arm64_ftr_bits ftr_dczid[] = { 463 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 464 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 465 ARM64_FTR_END, 466 }; 467 468 static const struct arm64_ftr_bits ftr_gmid[] = { 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 470 ARM64_FTR_END, 471 }; 472 473 static const struct arm64_ftr_bits ftr_id_isar0[] = { 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 481 ARM64_FTR_END, 482 }; 483 484 static const struct arm64_ftr_bits ftr_id_isar5[] = { 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 491 ARM64_FTR_END, 492 }; 493 494 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 502 503 /* 504 * SpecSEI = 1 indicates that the PE might generate an SError on an 505 * external abort on speculative read. It is safe to assume that an 506 * SError might be generated than it will not be. Hence it has been 507 * classified as FTR_HIGHER_SAFE. 508 */ 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 510 ARM64_FTR_END, 511 }; 512 513 static const struct arm64_ftr_bits ftr_id_isar4[] = { 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 522 ARM64_FTR_END, 523 }; 524 525 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 527 ARM64_FTR_END, 528 }; 529 530 static const struct arm64_ftr_bits ftr_id_isar6[] = { 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 538 ARM64_FTR_END, 539 }; 540 541 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 548 ARM64_FTR_END, 549 }; 550 551 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 560 ARM64_FTR_END, 561 }; 562 563 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 564 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 565 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 566 ARM64_FTR_END, 567 }; 568 569 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 570 /* [31:28] TraceFilt */ 571 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_PERFMON_SHIFT, 4, 0), 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 578 ARM64_FTR_END, 579 }; 580 581 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 582 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 583 ARM64_FTR_END, 584 }; 585 586 static const struct arm64_ftr_bits ftr_zcr[] = { 587 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 588 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0), /* LEN */ 589 ARM64_FTR_END, 590 }; 591 592 static const struct arm64_ftr_bits ftr_smcr[] = { 593 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 594 SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0), /* LEN */ 595 ARM64_FTR_END, 596 }; 597 598 /* 599 * Common ftr bits for a 32bit register with all hidden, strict 600 * attributes, with 4bit feature fields and a default safe value of 601 * 0. Covers the following 32bit registers: 602 * id_isar[1-3], id_mmfr[1-3] 603 */ 604 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 608 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 609 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 610 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 611 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 612 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 613 ARM64_FTR_END, 614 }; 615 616 /* Table for a single 32bit feature value */ 617 static const struct arm64_ftr_bits ftr_single32[] = { 618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 619 ARM64_FTR_END, 620 }; 621 622 static const struct arm64_ftr_bits ftr_raz[] = { 623 ARM64_FTR_END, 624 }; 625 626 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 627 .sys_id = id, \ 628 .reg = &(struct arm64_ftr_reg){ \ 629 .name = id_str, \ 630 .override = (ovr), \ 631 .ftr_bits = &((table)[0]), \ 632 }} 633 634 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 635 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 636 637 #define ARM64_FTR_REG(id, table) \ 638 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 639 640 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 641 struct arm64_ftr_override __ro_after_init id_aa64pfr0_override; 642 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 643 struct arm64_ftr_override __ro_after_init id_aa64zfr0_override; 644 struct arm64_ftr_override __ro_after_init id_aa64smfr0_override; 645 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 646 struct arm64_ftr_override __ro_after_init id_aa64isar2_override; 647 648 static const struct __ftr_reg_entry { 649 u32 sys_id; 650 struct arm64_ftr_reg *reg; 651 } arm64_ftr_regs[] = { 652 653 /* Op1 = 0, CRn = 0, CRm = 1 */ 654 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 655 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 656 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 657 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 658 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 659 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 660 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 661 662 /* Op1 = 0, CRn = 0, CRm = 2 */ 663 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 664 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 665 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 666 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 667 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 668 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 669 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 670 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 671 672 /* Op1 = 0, CRn = 0, CRm = 3 */ 673 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 674 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 675 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 676 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 677 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 678 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 679 680 /* Op1 = 0, CRn = 0, CRm = 4 */ 681 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 682 &id_aa64pfr0_override), 683 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 684 &id_aa64pfr1_override), 685 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 686 &id_aa64zfr0_override), 687 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 688 &id_aa64smfr0_override), 689 690 /* Op1 = 0, CRn = 0, CRm = 5 */ 691 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 692 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 693 694 /* Op1 = 0, CRn = 0, CRm = 6 */ 695 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 696 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 697 &id_aa64isar1_override), 698 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 699 &id_aa64isar2_override), 700 701 /* Op1 = 0, CRn = 0, CRm = 7 */ 702 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 703 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 704 &id_aa64mmfr1_override), 705 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 706 707 /* Op1 = 0, CRn = 1, CRm = 2 */ 708 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 709 ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr), 710 711 /* Op1 = 1, CRn = 0, CRm = 0 */ 712 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 713 714 /* Op1 = 3, CRn = 0, CRm = 0 */ 715 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 716 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 717 718 /* Op1 = 3, CRn = 14, CRm = 0 */ 719 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 720 }; 721 722 static int search_cmp_ftr_reg(const void *id, const void *regp) 723 { 724 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 725 } 726 727 /* 728 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 729 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 730 * ascending order of sys_id, we use binary search to find a matching 731 * entry. 732 * 733 * returns - Upon success, matching ftr_reg entry for id. 734 * - NULL on failure. It is upto the caller to decide 735 * the impact of a failure. 736 */ 737 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 738 { 739 const struct __ftr_reg_entry *ret; 740 741 ret = bsearch((const void *)(unsigned long)sys_id, 742 arm64_ftr_regs, 743 ARRAY_SIZE(arm64_ftr_regs), 744 sizeof(arm64_ftr_regs[0]), 745 search_cmp_ftr_reg); 746 if (ret) 747 return ret->reg; 748 return NULL; 749 } 750 751 /* 752 * get_arm64_ftr_reg - Looks up a feature register entry using 753 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 754 * 755 * returns - Upon success, matching ftr_reg entry for id. 756 * - NULL on failure but with an WARN_ON(). 757 */ 758 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 759 { 760 struct arm64_ftr_reg *reg; 761 762 reg = get_arm64_ftr_reg_nowarn(sys_id); 763 764 /* 765 * Requesting a non-existent register search is an error. Warn 766 * and let the caller handle it. 767 */ 768 WARN_ON(!reg); 769 return reg; 770 } 771 772 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 773 s64 ftr_val) 774 { 775 u64 mask = arm64_ftr_mask(ftrp); 776 777 reg &= ~mask; 778 reg |= (ftr_val << ftrp->shift) & mask; 779 return reg; 780 } 781 782 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 783 s64 cur) 784 { 785 s64 ret = 0; 786 787 switch (ftrp->type) { 788 case FTR_EXACT: 789 ret = ftrp->safe_val; 790 break; 791 case FTR_LOWER_SAFE: 792 ret = min(new, cur); 793 break; 794 case FTR_HIGHER_OR_ZERO_SAFE: 795 if (!cur || !new) 796 break; 797 fallthrough; 798 case FTR_HIGHER_SAFE: 799 ret = max(new, cur); 800 break; 801 default: 802 BUG(); 803 } 804 805 return ret; 806 } 807 808 static void __init sort_ftr_regs(void) 809 { 810 unsigned int i; 811 812 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 813 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 814 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 815 unsigned int j = 0; 816 817 /* 818 * Features here must be sorted in descending order with respect 819 * to their shift values and should not overlap with each other. 820 */ 821 for (; ftr_bits->width != 0; ftr_bits++, j++) { 822 unsigned int width = ftr_reg->ftr_bits[j].width; 823 unsigned int shift = ftr_reg->ftr_bits[j].shift; 824 unsigned int prev_shift; 825 826 WARN((shift + width) > 64, 827 "%s has invalid feature at shift %d\n", 828 ftr_reg->name, shift); 829 830 /* 831 * Skip the first feature. There is nothing to 832 * compare against for now. 833 */ 834 if (j == 0) 835 continue; 836 837 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 838 WARN((shift + width) > prev_shift, 839 "%s has feature overlap at shift %d\n", 840 ftr_reg->name, shift); 841 } 842 843 /* 844 * Skip the first register. There is nothing to 845 * compare against for now. 846 */ 847 if (i == 0) 848 continue; 849 /* 850 * Registers here must be sorted in ascending order with respect 851 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 852 * to work correctly. 853 */ 854 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 855 } 856 } 857 858 /* 859 * Initialise the CPU feature register from Boot CPU values. 860 * Also initiliases the strict_mask for the register. 861 * Any bits that are not covered by an arm64_ftr_bits entry are considered 862 * RES0 for the system-wide value, and must strictly match. 863 */ 864 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 865 { 866 u64 val = 0; 867 u64 strict_mask = ~0x0ULL; 868 u64 user_mask = 0; 869 u64 valid_mask = 0; 870 871 const struct arm64_ftr_bits *ftrp; 872 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 873 874 if (!reg) 875 return; 876 877 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 878 u64 ftr_mask = arm64_ftr_mask(ftrp); 879 s64 ftr_new = arm64_ftr_value(ftrp, new); 880 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 881 882 if ((ftr_mask & reg->override->mask) == ftr_mask) { 883 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 884 char *str = NULL; 885 886 if (ftr_ovr != tmp) { 887 /* Unsafe, remove the override */ 888 reg->override->mask &= ~ftr_mask; 889 reg->override->val &= ~ftr_mask; 890 tmp = ftr_ovr; 891 str = "ignoring override"; 892 } else if (ftr_new != tmp) { 893 /* Override was valid */ 894 ftr_new = tmp; 895 str = "forced"; 896 } else if (ftr_ovr == tmp) { 897 /* Override was the safe value */ 898 str = "already set"; 899 } 900 901 if (str) 902 pr_warn("%s[%d:%d]: %s to %llx\n", 903 reg->name, 904 ftrp->shift + ftrp->width - 1, 905 ftrp->shift, str, tmp); 906 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 907 reg->override->val &= ~ftr_mask; 908 pr_warn("%s[%d:%d]: impossible override, ignored\n", 909 reg->name, 910 ftrp->shift + ftrp->width - 1, 911 ftrp->shift); 912 } 913 914 val = arm64_ftr_set_value(ftrp, val, ftr_new); 915 916 valid_mask |= ftr_mask; 917 if (!ftrp->strict) 918 strict_mask &= ~ftr_mask; 919 if (ftrp->visible) 920 user_mask |= ftr_mask; 921 else 922 reg->user_val = arm64_ftr_set_value(ftrp, 923 reg->user_val, 924 ftrp->safe_val); 925 } 926 927 val &= valid_mask; 928 929 reg->sys_val = val; 930 reg->strict_mask = strict_mask; 931 reg->user_mask = user_mask; 932 } 933 934 extern const struct arm64_cpu_capabilities arm64_errata[]; 935 static const struct arm64_cpu_capabilities arm64_features[]; 936 937 static void __init 938 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 939 { 940 for (; caps->matches; caps++) { 941 if (WARN(caps->capability >= ARM64_NCAPS, 942 "Invalid capability %d\n", caps->capability)) 943 continue; 944 if (WARN(cpu_hwcaps_ptrs[caps->capability], 945 "Duplicate entry for capability %d\n", 946 caps->capability)) 947 continue; 948 cpu_hwcaps_ptrs[caps->capability] = caps; 949 } 950 } 951 952 static void __init init_cpu_hwcaps_indirect_list(void) 953 { 954 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 955 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 956 } 957 958 static void __init setup_boot_cpu_capabilities(void); 959 960 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 961 { 962 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 963 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 964 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 965 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 966 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 967 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 968 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 969 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 970 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 971 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 972 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 973 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 974 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 975 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 976 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 977 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 978 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 979 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 980 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 981 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 982 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 983 } 984 985 void __init init_cpu_features(struct cpuinfo_arm64 *info) 986 { 987 /* Before we start using the tables, make sure it is sorted */ 988 sort_ftr_regs(); 989 990 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 991 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 992 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 993 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 994 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 995 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 996 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 997 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 998 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 999 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1000 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1001 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1002 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1003 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1004 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1005 1006 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1007 init_32bit_cpu_features(&info->aarch32); 1008 1009 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1010 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1011 info->reg_zcr = read_zcr_features(); 1012 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 1013 vec_init_vq_map(ARM64_VEC_SVE); 1014 } 1015 1016 if (IS_ENABLED(CONFIG_ARM64_SME) && 1017 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1018 info->reg_smcr = read_smcr_features(); 1019 /* 1020 * We mask out SMPS since even if the hardware 1021 * supports priorities the kernel does not at present 1022 * and we block access to them. 1023 */ 1024 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1025 init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr); 1026 vec_init_vq_map(ARM64_VEC_SME); 1027 } 1028 1029 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1030 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1031 1032 /* 1033 * Initialize the indirect array of CPU hwcaps capabilities pointers 1034 * before we handle the boot CPU below. 1035 */ 1036 init_cpu_hwcaps_indirect_list(); 1037 1038 /* 1039 * Detect and enable early CPU capabilities based on the boot CPU, 1040 * after we have initialised the CPU feature infrastructure. 1041 */ 1042 setup_boot_cpu_capabilities(); 1043 } 1044 1045 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1046 { 1047 const struct arm64_ftr_bits *ftrp; 1048 1049 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1050 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1051 s64 ftr_new = arm64_ftr_value(ftrp, new); 1052 1053 if (ftr_cur == ftr_new) 1054 continue; 1055 /* Find a safe value */ 1056 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1057 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1058 } 1059 1060 } 1061 1062 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1063 { 1064 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1065 1066 if (!regp) 1067 return 0; 1068 1069 update_cpu_ftr_reg(regp, val); 1070 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1071 return 0; 1072 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1073 regp->name, boot, cpu, val); 1074 return 1; 1075 } 1076 1077 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1078 { 1079 const struct arm64_ftr_bits *ftrp; 1080 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1081 1082 if (!regp) 1083 return; 1084 1085 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1086 if (ftrp->shift == field) { 1087 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1088 break; 1089 } 1090 } 1091 1092 /* Bogus field? */ 1093 WARN_ON(!ftrp->width); 1094 } 1095 1096 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1097 struct cpuinfo_arm64 *boot) 1098 { 1099 static bool boot_cpu_32bit_regs_overridden = false; 1100 1101 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1102 return; 1103 1104 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1105 return; 1106 1107 boot->aarch32 = info->aarch32; 1108 init_32bit_cpu_features(&boot->aarch32); 1109 boot_cpu_32bit_regs_overridden = true; 1110 } 1111 1112 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1113 struct cpuinfo_32bit *boot) 1114 { 1115 int taint = 0; 1116 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1117 1118 /* 1119 * If we don't have AArch32 at EL1, then relax the strictness of 1120 * EL1-dependent register fields to avoid spurious sanity check fails. 1121 */ 1122 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1123 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 1124 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 1125 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 1126 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 1127 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 1128 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 1129 } 1130 1131 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1132 info->reg_id_dfr0, boot->reg_id_dfr0); 1133 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1134 info->reg_id_dfr1, boot->reg_id_dfr1); 1135 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1136 info->reg_id_isar0, boot->reg_id_isar0); 1137 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1138 info->reg_id_isar1, boot->reg_id_isar1); 1139 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1140 info->reg_id_isar2, boot->reg_id_isar2); 1141 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1142 info->reg_id_isar3, boot->reg_id_isar3); 1143 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1144 info->reg_id_isar4, boot->reg_id_isar4); 1145 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1146 info->reg_id_isar5, boot->reg_id_isar5); 1147 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1148 info->reg_id_isar6, boot->reg_id_isar6); 1149 1150 /* 1151 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1152 * ACTLR formats could differ across CPUs and therefore would have to 1153 * be trapped for virtualization anyway. 1154 */ 1155 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1156 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1157 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1158 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1159 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1160 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1161 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1162 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1163 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1164 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1165 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1166 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1167 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1168 info->reg_id_pfr0, boot->reg_id_pfr0); 1169 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1170 info->reg_id_pfr1, boot->reg_id_pfr1); 1171 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1172 info->reg_id_pfr2, boot->reg_id_pfr2); 1173 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1174 info->reg_mvfr0, boot->reg_mvfr0); 1175 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1176 info->reg_mvfr1, boot->reg_mvfr1); 1177 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1178 info->reg_mvfr2, boot->reg_mvfr2); 1179 1180 return taint; 1181 } 1182 1183 /* 1184 * Update system wide CPU feature registers with the values from a 1185 * non-boot CPU. Also performs SANITY checks to make sure that there 1186 * aren't any insane variations from that of the boot CPU. 1187 */ 1188 void update_cpu_features(int cpu, 1189 struct cpuinfo_arm64 *info, 1190 struct cpuinfo_arm64 *boot) 1191 { 1192 int taint = 0; 1193 1194 /* 1195 * The kernel can handle differing I-cache policies, but otherwise 1196 * caches should look identical. Userspace JITs will make use of 1197 * *minLine. 1198 */ 1199 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1200 info->reg_ctr, boot->reg_ctr); 1201 1202 /* 1203 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1204 * could result in too much or too little memory being zeroed if a 1205 * process is preempted and migrated between CPUs. 1206 */ 1207 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1208 info->reg_dczid, boot->reg_dczid); 1209 1210 /* If different, timekeeping will be broken (especially with KVM) */ 1211 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1212 info->reg_cntfrq, boot->reg_cntfrq); 1213 1214 /* 1215 * The kernel uses self-hosted debug features and expects CPUs to 1216 * support identical debug features. We presently need CTX_CMPs, WRPs, 1217 * and BRPs to be identical. 1218 * ID_AA64DFR1 is currently RES0. 1219 */ 1220 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1221 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1222 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1223 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1224 /* 1225 * Even in big.LITTLE, processors should be identical instruction-set 1226 * wise. 1227 */ 1228 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1229 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1230 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1231 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1232 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1233 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1234 1235 /* 1236 * Differing PARange support is fine as long as all peripherals and 1237 * memory are mapped within the minimum PARange of all CPUs. 1238 * Linux should not care about secure memory. 1239 */ 1240 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1241 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1242 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1243 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1244 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1245 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1246 1247 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1248 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1249 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1250 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1251 1252 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1253 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1254 1255 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1256 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1257 1258 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1259 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1260 info->reg_zcr = read_zcr_features(); 1261 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1262 info->reg_zcr, boot->reg_zcr); 1263 1264 /* Probe vector lengths */ 1265 if (!system_capabilities_finalized()) 1266 vec_update_vq_map(ARM64_VEC_SVE); 1267 } 1268 1269 if (IS_ENABLED(CONFIG_ARM64_SME) && 1270 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1271 info->reg_smcr = read_smcr_features(); 1272 /* 1273 * We mask out SMPS since even if the hardware 1274 * supports priorities the kernel does not at present 1275 * and we block access to them. 1276 */ 1277 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1278 taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu, 1279 info->reg_smcr, boot->reg_smcr); 1280 1281 /* Probe vector lengths */ 1282 if (!system_capabilities_finalized()) 1283 vec_update_vq_map(ARM64_VEC_SME); 1284 } 1285 1286 /* 1287 * The kernel uses the LDGM/STGM instructions and the number of tags 1288 * they read/write depends on the GMID_EL1.BS field. Check that the 1289 * value is the same on all CPUs. 1290 */ 1291 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1292 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1293 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1294 info->reg_gmid, boot->reg_gmid); 1295 } 1296 1297 /* 1298 * If we don't have AArch32 at all then skip the checks entirely 1299 * as the register values may be UNKNOWN and we're not going to be 1300 * using them for anything. 1301 * 1302 * This relies on a sanitised view of the AArch64 ID registers 1303 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1304 */ 1305 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1306 lazy_init_32bit_cpu_features(info, boot); 1307 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1308 &boot->aarch32); 1309 } 1310 1311 /* 1312 * Mismatched CPU features are a recipe for disaster. Don't even 1313 * pretend to support them. 1314 */ 1315 if (taint) { 1316 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1317 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1318 } 1319 } 1320 1321 u64 read_sanitised_ftr_reg(u32 id) 1322 { 1323 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1324 1325 if (!regp) 1326 return 0; 1327 return regp->sys_val; 1328 } 1329 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1330 1331 #define read_sysreg_case(r) \ 1332 case r: val = read_sysreg_s(r); break; 1333 1334 /* 1335 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1336 * Read the system register on the current CPU 1337 */ 1338 u64 __read_sysreg_by_encoding(u32 sys_id) 1339 { 1340 struct arm64_ftr_reg *regp; 1341 u64 val; 1342 1343 switch (sys_id) { 1344 read_sysreg_case(SYS_ID_PFR0_EL1); 1345 read_sysreg_case(SYS_ID_PFR1_EL1); 1346 read_sysreg_case(SYS_ID_PFR2_EL1); 1347 read_sysreg_case(SYS_ID_DFR0_EL1); 1348 read_sysreg_case(SYS_ID_DFR1_EL1); 1349 read_sysreg_case(SYS_ID_MMFR0_EL1); 1350 read_sysreg_case(SYS_ID_MMFR1_EL1); 1351 read_sysreg_case(SYS_ID_MMFR2_EL1); 1352 read_sysreg_case(SYS_ID_MMFR3_EL1); 1353 read_sysreg_case(SYS_ID_MMFR4_EL1); 1354 read_sysreg_case(SYS_ID_MMFR5_EL1); 1355 read_sysreg_case(SYS_ID_ISAR0_EL1); 1356 read_sysreg_case(SYS_ID_ISAR1_EL1); 1357 read_sysreg_case(SYS_ID_ISAR2_EL1); 1358 read_sysreg_case(SYS_ID_ISAR3_EL1); 1359 read_sysreg_case(SYS_ID_ISAR4_EL1); 1360 read_sysreg_case(SYS_ID_ISAR5_EL1); 1361 read_sysreg_case(SYS_ID_ISAR6_EL1); 1362 read_sysreg_case(SYS_MVFR0_EL1); 1363 read_sysreg_case(SYS_MVFR1_EL1); 1364 read_sysreg_case(SYS_MVFR2_EL1); 1365 1366 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1367 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1368 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1369 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1370 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1371 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1372 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1373 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1374 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1375 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1376 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1377 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1378 1379 read_sysreg_case(SYS_CNTFRQ_EL0); 1380 read_sysreg_case(SYS_CTR_EL0); 1381 read_sysreg_case(SYS_DCZID_EL0); 1382 1383 default: 1384 BUG(); 1385 return 0; 1386 } 1387 1388 regp = get_arm64_ftr_reg(sys_id); 1389 if (regp) { 1390 val &= ~regp->override->mask; 1391 val |= (regp->override->val & regp->override->mask); 1392 } 1393 1394 return val; 1395 } 1396 1397 #include <linux/irqchip/arm-gic-v3.h> 1398 1399 static bool 1400 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1401 { 1402 return true; 1403 } 1404 1405 static bool 1406 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1407 { 1408 int val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1409 entry->field_width, 1410 entry->sign); 1411 1412 return val >= entry->min_field_value; 1413 } 1414 1415 static u64 1416 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1417 { 1418 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1419 if (scope == SCOPE_SYSTEM) 1420 return read_sanitised_ftr_reg(entry->sys_reg); 1421 else 1422 return __read_sysreg_by_encoding(entry->sys_reg); 1423 } 1424 1425 static bool 1426 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1427 { 1428 int mask; 1429 struct arm64_ftr_reg *regp; 1430 u64 val = read_scoped_sysreg(entry, scope); 1431 1432 regp = get_arm64_ftr_reg(entry->sys_reg); 1433 if (!regp) 1434 return false; 1435 1436 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1437 entry->field_pos, 1438 entry->field_width); 1439 if (!mask) 1440 return false; 1441 1442 return feature_matches(val, entry); 1443 } 1444 1445 static bool 1446 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1447 { 1448 u64 val = read_scoped_sysreg(entry, scope); 1449 return feature_matches(val, entry); 1450 } 1451 1452 const struct cpumask *system_32bit_el0_cpumask(void) 1453 { 1454 if (!system_supports_32bit_el0()) 1455 return cpu_none_mask; 1456 1457 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1458 return cpu_32bit_el0_mask; 1459 1460 return cpu_possible_mask; 1461 } 1462 1463 static int __init parse_32bit_el0_param(char *str) 1464 { 1465 allow_mismatched_32bit_el0 = true; 1466 return 0; 1467 } 1468 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1469 1470 static ssize_t aarch32_el0_show(struct device *dev, 1471 struct device_attribute *attr, char *buf) 1472 { 1473 const struct cpumask *mask = system_32bit_el0_cpumask(); 1474 1475 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1476 } 1477 static const DEVICE_ATTR_RO(aarch32_el0); 1478 1479 static int __init aarch32_el0_sysfs_init(void) 1480 { 1481 if (!allow_mismatched_32bit_el0) 1482 return 0; 1483 1484 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0); 1485 } 1486 device_initcall(aarch32_el0_sysfs_init); 1487 1488 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1489 { 1490 if (!has_cpuid_feature(entry, scope)) 1491 return allow_mismatched_32bit_el0; 1492 1493 if (scope == SCOPE_SYSTEM) 1494 pr_info("detected: 32-bit EL0 Support\n"); 1495 1496 return true; 1497 } 1498 1499 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1500 { 1501 bool has_sre; 1502 1503 if (!has_cpuid_feature(entry, scope)) 1504 return false; 1505 1506 has_sre = gic_enable_sre(); 1507 if (!has_sre) 1508 pr_warn_once("%s present but disabled by higher exception level\n", 1509 entry->desc); 1510 1511 return has_sre; 1512 } 1513 1514 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1515 { 1516 u32 midr = read_cpuid_id(); 1517 1518 /* Cavium ThunderX pass 1.x and 2.x */ 1519 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1520 MIDR_CPU_VAR_REV(0, 0), 1521 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1522 } 1523 1524 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1525 { 1526 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1527 1528 return cpuid_feature_extract_signed_field(pfr0, 1529 ID_AA64PFR0_EL1_FP_SHIFT) < 0; 1530 } 1531 1532 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1533 int scope) 1534 { 1535 u64 ctr; 1536 1537 if (scope == SCOPE_SYSTEM) 1538 ctr = arm64_ftr_reg_ctrel0.sys_val; 1539 else 1540 ctr = read_cpuid_effective_cachetype(); 1541 1542 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1543 } 1544 1545 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1546 { 1547 /* 1548 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1549 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1550 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1551 * value. 1552 */ 1553 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1554 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1555 } 1556 1557 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1558 int scope) 1559 { 1560 u64 ctr; 1561 1562 if (scope == SCOPE_SYSTEM) 1563 ctr = arm64_ftr_reg_ctrel0.sys_val; 1564 else 1565 ctr = read_cpuid_cachetype(); 1566 1567 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1568 } 1569 1570 static bool __maybe_unused 1571 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1572 { 1573 /* 1574 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1575 * may share TLB entries with a CPU stuck in the crashed 1576 * kernel. 1577 */ 1578 if (is_kdump_kernel()) 1579 return false; 1580 1581 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1582 return false; 1583 1584 return has_cpuid_feature(entry, scope); 1585 } 1586 1587 /* 1588 * This check is triggered during the early boot before the cpufeature 1589 * is initialised. Checking the status on the local CPU allows the boot 1590 * CPU to detect the need for non-global mappings and thus avoiding a 1591 * pagetable re-write after all the CPUs are booted. This check will be 1592 * anyway run on individual CPUs, allowing us to get the consistent 1593 * state once the SMP CPUs are up and thus make the switch to non-global 1594 * mappings if required. 1595 */ 1596 bool kaslr_requires_kpti(void) 1597 { 1598 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1599 return false; 1600 1601 /* 1602 * E0PD does a similar job to KPTI so can be used instead 1603 * where available. 1604 */ 1605 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1606 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1607 if (cpuid_feature_extract_unsigned_field(mmfr2, 1608 ID_AA64MMFR2_EL1_E0PD_SHIFT)) 1609 return false; 1610 } 1611 1612 /* 1613 * Systems affected by Cavium erratum 24756 are incompatible 1614 * with KPTI. 1615 */ 1616 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1617 extern const struct midr_range cavium_erratum_27456_cpus[]; 1618 1619 if (is_midr_in_range_list(read_cpuid_id(), 1620 cavium_erratum_27456_cpus)) 1621 return false; 1622 } 1623 1624 return kaslr_offset() > 0; 1625 } 1626 1627 static bool __meltdown_safe = true; 1628 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1629 1630 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1631 int scope) 1632 { 1633 /* List of CPUs that are not vulnerable and don't need KPTI */ 1634 static const struct midr_range kpti_safe_list[] = { 1635 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1636 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1637 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1638 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1639 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1640 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1641 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1642 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1643 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1644 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1645 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1646 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1647 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1648 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1649 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1650 { /* sentinel */ } 1651 }; 1652 char const *str = "kpti command line option"; 1653 bool meltdown_safe; 1654 1655 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1656 1657 /* Defer to CPU feature registers */ 1658 if (has_cpuid_feature(entry, scope)) 1659 meltdown_safe = true; 1660 1661 if (!meltdown_safe) 1662 __meltdown_safe = false; 1663 1664 /* 1665 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1666 * ThunderX leads to apparent I-cache corruption of kernel text, which 1667 * ends as well as you might imagine. Don't even try. We cannot rely 1668 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1669 * because cpucap detection order may change. However, since we know 1670 * affected CPUs are always in a homogeneous configuration, it is 1671 * safe to rely on this_cpu_has_cap() here. 1672 */ 1673 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1674 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1675 __kpti_forced = -1; 1676 } 1677 1678 /* Useful for KASLR robustness */ 1679 if (kaslr_requires_kpti()) { 1680 if (!__kpti_forced) { 1681 str = "KASLR"; 1682 __kpti_forced = 1; 1683 } 1684 } 1685 1686 if (cpu_mitigations_off() && !__kpti_forced) { 1687 str = "mitigations=off"; 1688 __kpti_forced = -1; 1689 } 1690 1691 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1692 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1693 return false; 1694 } 1695 1696 /* Forced? */ 1697 if (__kpti_forced) { 1698 pr_info_once("kernel page table isolation forced %s by %s\n", 1699 __kpti_forced > 0 ? "ON" : "OFF", str); 1700 return __kpti_forced > 0; 1701 } 1702 1703 return !meltdown_safe; 1704 } 1705 1706 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1707 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1708 1709 extern 1710 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1711 phys_addr_t size, pgprot_t prot, 1712 phys_addr_t (*pgtable_alloc)(int), int flags); 1713 1714 static phys_addr_t kpti_ng_temp_alloc; 1715 1716 static phys_addr_t kpti_ng_pgd_alloc(int shift) 1717 { 1718 kpti_ng_temp_alloc -= PAGE_SIZE; 1719 return kpti_ng_temp_alloc; 1720 } 1721 1722 static void 1723 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1724 { 1725 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1726 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1727 kpti_remap_fn *remap_fn; 1728 1729 int cpu = smp_processor_id(); 1730 int levels = CONFIG_PGTABLE_LEVELS; 1731 int order = order_base_2(levels); 1732 u64 kpti_ng_temp_pgd_pa = 0; 1733 pgd_t *kpti_ng_temp_pgd; 1734 u64 alloc = 0; 1735 1736 if (__this_cpu_read(this_cpu_vector) == vectors) { 1737 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1738 1739 __this_cpu_write(this_cpu_vector, v); 1740 } 1741 1742 /* 1743 * We don't need to rewrite the page-tables if either we've done 1744 * it already or we have KASLR enabled and therefore have not 1745 * created any global mappings at all. 1746 */ 1747 if (arm64_use_ng_mappings) 1748 return; 1749 1750 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1751 1752 if (!cpu) { 1753 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1754 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1755 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1756 1757 // 1758 // Create a minimal page table hierarchy that permits us to map 1759 // the swapper page tables temporarily as we traverse them. 1760 // 1761 // The physical pages are laid out as follows: 1762 // 1763 // +--------+-/-------+-/------ +-\\--------+ 1764 // : PTE[] : | PMD[] : | PUD[] : || PGD[] : 1765 // +--------+-\-------+-\------ +-//--------+ 1766 // ^ 1767 // The first page is mapped into this hierarchy at a PMD_SHIFT 1768 // aligned virtual address, so that we can manipulate the PTE 1769 // level entries while the mapping is active. The first entry 1770 // covers the PTE[] page itself, the remaining entries are free 1771 // to be used as a ad-hoc fixmap. 1772 // 1773 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1774 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1775 kpti_ng_pgd_alloc, 0); 1776 } 1777 1778 cpu_install_idmap(); 1779 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1780 cpu_uninstall_idmap(); 1781 1782 if (!cpu) { 1783 free_pages(alloc, order); 1784 arm64_use_ng_mappings = true; 1785 } 1786 } 1787 #else 1788 static void 1789 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1790 { 1791 } 1792 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1793 1794 static int __init parse_kpti(char *str) 1795 { 1796 bool enabled; 1797 int ret = strtobool(str, &enabled); 1798 1799 if (ret) 1800 return ret; 1801 1802 __kpti_forced = enabled ? 1 : -1; 1803 return 0; 1804 } 1805 early_param("kpti", parse_kpti); 1806 1807 #ifdef CONFIG_ARM64_HW_AFDBM 1808 static inline void __cpu_enable_hw_dbm(void) 1809 { 1810 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1811 1812 write_sysreg(tcr, tcr_el1); 1813 isb(); 1814 local_flush_tlb_all(); 1815 } 1816 1817 static bool cpu_has_broken_dbm(void) 1818 { 1819 /* List of CPUs which have broken DBM support. */ 1820 static const struct midr_range cpus[] = { 1821 #ifdef CONFIG_ARM64_ERRATUM_1024718 1822 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1823 /* Kryo4xx Silver (rdpe => r1p0) */ 1824 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1825 #endif 1826 #ifdef CONFIG_ARM64_ERRATUM_2051678 1827 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1828 #endif 1829 {}, 1830 }; 1831 1832 return is_midr_in_range_list(read_cpuid_id(), cpus); 1833 } 1834 1835 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1836 { 1837 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1838 !cpu_has_broken_dbm(); 1839 } 1840 1841 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1842 { 1843 if (cpu_can_use_dbm(cap)) 1844 __cpu_enable_hw_dbm(); 1845 } 1846 1847 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1848 int __unused) 1849 { 1850 static bool detected = false; 1851 /* 1852 * DBM is a non-conflicting feature. i.e, the kernel can safely 1853 * run a mix of CPUs with and without the feature. So, we 1854 * unconditionally enable the capability to allow any late CPU 1855 * to use the feature. We only enable the control bits on the 1856 * CPU, if it actually supports. 1857 * 1858 * We have to make sure we print the "feature" detection only 1859 * when at least one CPU actually uses it. So check if this CPU 1860 * can actually use it and print the message exactly once. 1861 * 1862 * This is safe as all CPUs (including secondary CPUs - due to the 1863 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1864 * goes through the "matches" check exactly once. Also if a CPU 1865 * matches the criteria, it is guaranteed that the CPU will turn 1866 * the DBM on, as the capability is unconditionally enabled. 1867 */ 1868 if (!detected && cpu_can_use_dbm(cap)) { 1869 detected = true; 1870 pr_info("detected: Hardware dirty bit management\n"); 1871 } 1872 1873 return true; 1874 } 1875 1876 #endif 1877 1878 #ifdef CONFIG_ARM64_AMU_EXTN 1879 1880 /* 1881 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1882 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1883 * information regarding all the events that it supports. When a CPU bit is 1884 * set in the cpumask, the user of this feature can only rely on the presence 1885 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1886 * counters are enabled or access to these counters is enabled by code 1887 * executed at higher exception levels (firmware). 1888 */ 1889 static struct cpumask amu_cpus __read_mostly; 1890 1891 bool cpu_has_amu_feat(int cpu) 1892 { 1893 return cpumask_test_cpu(cpu, &amu_cpus); 1894 } 1895 1896 int get_cpu_with_amu_feat(void) 1897 { 1898 return cpumask_any(&amu_cpus); 1899 } 1900 1901 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1902 { 1903 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1904 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1905 smp_processor_id()); 1906 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1907 1908 /* 0 reference values signal broken/disabled counters */ 1909 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 1910 update_freq_counters_refs(); 1911 } 1912 } 1913 1914 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1915 int __unused) 1916 { 1917 /* 1918 * The AMU extension is a non-conflicting feature: the kernel can 1919 * safely run a mix of CPUs with and without support for the 1920 * activity monitors extension. Therefore, unconditionally enable 1921 * the capability to allow any late CPU to use the feature. 1922 * 1923 * With this feature unconditionally enabled, the cpu_enable 1924 * function will be called for all CPUs that match the criteria, 1925 * including secondary and hotplugged, marking this feature as 1926 * present on that respective CPU. The enable function will also 1927 * print a detection message. 1928 */ 1929 1930 return true; 1931 } 1932 #else 1933 int get_cpu_with_amu_feat(void) 1934 { 1935 return nr_cpu_ids; 1936 } 1937 #endif 1938 1939 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1940 { 1941 return is_kernel_in_hyp_mode(); 1942 } 1943 1944 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1945 { 1946 /* 1947 * Copy register values that aren't redirected by hardware. 1948 * 1949 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1950 * this value to tpidr_el2 before we patch the code. Once we've done 1951 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1952 * do anything here. 1953 */ 1954 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1955 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1956 } 1957 1958 #ifdef CONFIG_ARM64_PAN 1959 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1960 { 1961 /* 1962 * We modify PSTATE. This won't work from irq context as the PSTATE 1963 * is discarded once we return from the exception. 1964 */ 1965 WARN_ON_ONCE(in_interrupt()); 1966 1967 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1968 set_pstate_pan(1); 1969 } 1970 #endif /* CONFIG_ARM64_PAN */ 1971 1972 #ifdef CONFIG_ARM64_RAS_EXTN 1973 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1974 { 1975 /* Firmware may have left a deferred SError in this register. */ 1976 write_sysreg_s(0, SYS_DISR_EL1); 1977 } 1978 #endif /* CONFIG_ARM64_RAS_EXTN */ 1979 1980 #ifdef CONFIG_ARM64_PTR_AUTH 1981 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1982 { 1983 int boot_val, sec_val; 1984 1985 /* We don't expect to be called with SCOPE_SYSTEM */ 1986 WARN_ON(scope == SCOPE_SYSTEM); 1987 /* 1988 * The ptr-auth feature levels are not intercompatible with lower 1989 * levels. Hence we must match ptr-auth feature level of the secondary 1990 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1991 * from the sanitised register whereas direct register read is done for 1992 * the secondary CPUs. 1993 * The sanitised feature state is guaranteed to match that of the 1994 * boot CPU as a mismatched secondary CPU is parked before it gets 1995 * a chance to update the state, with the capability. 1996 */ 1997 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1998 entry->field_pos, entry->sign); 1999 if (scope & SCOPE_BOOT_CPU) 2000 return boot_val >= entry->min_field_value; 2001 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2002 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2003 entry->field_pos, entry->sign); 2004 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2005 } 2006 2007 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2008 int scope) 2009 { 2010 bool api = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2011 bool apa = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2012 bool apa3 = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2013 2014 return apa || apa3 || api; 2015 } 2016 2017 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2018 int __unused) 2019 { 2020 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2021 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2022 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2023 2024 return gpa || gpa3 || gpi; 2025 } 2026 #endif /* CONFIG_ARM64_PTR_AUTH */ 2027 2028 #ifdef CONFIG_ARM64_E0PD 2029 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2030 { 2031 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2032 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2033 } 2034 #endif /* CONFIG_ARM64_E0PD */ 2035 2036 #ifdef CONFIG_ARM64_PSEUDO_NMI 2037 static bool enable_pseudo_nmi; 2038 2039 static int __init early_enable_pseudo_nmi(char *p) 2040 { 2041 return strtobool(p, &enable_pseudo_nmi); 2042 } 2043 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 2044 2045 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2046 int scope) 2047 { 2048 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 2049 } 2050 #endif 2051 2052 #ifdef CONFIG_ARM64_BTI 2053 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2054 { 2055 /* 2056 * Use of X16/X17 for tail-calls and trampolines that jump to 2057 * function entry points using BR is a requirement for 2058 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2059 * So, be strict and forbid other BRs using other registers to 2060 * jump onto a PACIxSP instruction: 2061 */ 2062 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2063 isb(); 2064 } 2065 #endif /* CONFIG_ARM64_BTI */ 2066 2067 #ifdef CONFIG_ARM64_MTE 2068 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2069 { 2070 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2071 2072 mte_cpu_setup(); 2073 2074 /* 2075 * Clear the tags in the zero page. This needs to be done via the 2076 * linear map which has the Tagged attribute. 2077 */ 2078 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) 2079 mte_clear_page_tags(lm_alias(empty_zero_page)); 2080 2081 kasan_init_hw_tags_cpu(); 2082 } 2083 #endif /* CONFIG_ARM64_MTE */ 2084 2085 static void elf_hwcap_fixup(void) 2086 { 2087 #ifdef CONFIG_ARM64_ERRATUM_1742098 2088 if (cpus_have_const_cap(ARM64_WORKAROUND_1742098)) 2089 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2090 #endif /* ARM64_ERRATUM_1742098 */ 2091 } 2092 2093 #ifdef CONFIG_KVM 2094 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2095 { 2096 return kvm_get_mode() == KVM_MODE_PROTECTED; 2097 } 2098 #endif /* CONFIG_KVM */ 2099 2100 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2101 { 2102 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2103 } 2104 2105 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2106 { 2107 set_pstate_dit(1); 2108 } 2109 2110 /* Internal helper functions to match cpu capability type */ 2111 static bool 2112 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2113 { 2114 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2115 } 2116 2117 static bool 2118 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2119 { 2120 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2121 } 2122 2123 static bool 2124 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2125 { 2126 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2127 } 2128 2129 static const struct arm64_cpu_capabilities arm64_features[] = { 2130 { 2131 .capability = ARM64_ALWAYS_BOOT, 2132 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2133 .matches = has_always, 2134 }, 2135 { 2136 .capability = ARM64_ALWAYS_SYSTEM, 2137 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2138 .matches = has_always, 2139 }, 2140 { 2141 .desc = "GIC system register CPU interface", 2142 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 2143 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2144 .matches = has_useable_gicv3_cpuif, 2145 .sys_reg = SYS_ID_AA64PFR0_EL1, 2146 .field_pos = ID_AA64PFR0_EL1_GIC_SHIFT, 2147 .field_width = 4, 2148 .sign = FTR_UNSIGNED, 2149 .min_field_value = 1, 2150 }, 2151 { 2152 .desc = "Enhanced Counter Virtualization", 2153 .capability = ARM64_HAS_ECV, 2154 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2155 .matches = has_cpuid_feature, 2156 .sys_reg = SYS_ID_AA64MMFR0_EL1, 2157 .field_pos = ID_AA64MMFR0_EL1_ECV_SHIFT, 2158 .field_width = 4, 2159 .sign = FTR_UNSIGNED, 2160 .min_field_value = 1, 2161 }, 2162 #ifdef CONFIG_ARM64_PAN 2163 { 2164 .desc = "Privileged Access Never", 2165 .capability = ARM64_HAS_PAN, 2166 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2167 .matches = has_cpuid_feature, 2168 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2169 .field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT, 2170 .field_width = 4, 2171 .sign = FTR_UNSIGNED, 2172 .min_field_value = 1, 2173 .cpu_enable = cpu_enable_pan, 2174 }, 2175 #endif /* CONFIG_ARM64_PAN */ 2176 #ifdef CONFIG_ARM64_EPAN 2177 { 2178 .desc = "Enhanced Privileged Access Never", 2179 .capability = ARM64_HAS_EPAN, 2180 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2181 .matches = has_cpuid_feature, 2182 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2183 .field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT, 2184 .field_width = 4, 2185 .sign = FTR_UNSIGNED, 2186 .min_field_value = 3, 2187 }, 2188 #endif /* CONFIG_ARM64_EPAN */ 2189 #ifdef CONFIG_ARM64_LSE_ATOMICS 2190 { 2191 .desc = "LSE atomic instructions", 2192 .capability = ARM64_HAS_LSE_ATOMICS, 2193 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2194 .matches = has_cpuid_feature, 2195 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2196 .field_pos = ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 2197 .field_width = 4, 2198 .sign = FTR_UNSIGNED, 2199 .min_field_value = 2, 2200 }, 2201 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2202 { 2203 .desc = "Software prefetching using PRFM", 2204 .capability = ARM64_HAS_NO_HW_PREFETCH, 2205 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2206 .matches = has_no_hw_prefetch, 2207 }, 2208 { 2209 .desc = "Virtualization Host Extensions", 2210 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2211 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2212 .matches = runs_at_el2, 2213 .cpu_enable = cpu_copy_el2regs, 2214 }, 2215 { 2216 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2217 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2218 .matches = has_32bit_el0, 2219 .sys_reg = SYS_ID_AA64PFR0_EL1, 2220 .sign = FTR_UNSIGNED, 2221 .field_pos = ID_AA64PFR0_EL1_EL0_SHIFT, 2222 .field_width = 4, 2223 .min_field_value = ID_AA64PFR0_EL1_ELx_32BIT_64BIT, 2224 }, 2225 #ifdef CONFIG_KVM 2226 { 2227 .desc = "32-bit EL1 Support", 2228 .capability = ARM64_HAS_32BIT_EL1, 2229 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2230 .matches = has_cpuid_feature, 2231 .sys_reg = SYS_ID_AA64PFR0_EL1, 2232 .sign = FTR_UNSIGNED, 2233 .field_pos = ID_AA64PFR0_EL1_EL1_SHIFT, 2234 .field_width = 4, 2235 .min_field_value = ID_AA64PFR0_EL1_ELx_32BIT_64BIT, 2236 }, 2237 { 2238 .desc = "Protected KVM", 2239 .capability = ARM64_KVM_PROTECTED_MODE, 2240 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2241 .matches = is_kvm_protected_mode, 2242 }, 2243 #endif 2244 { 2245 .desc = "Kernel page table isolation (KPTI)", 2246 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2247 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2248 /* 2249 * The ID feature fields below are used to indicate that 2250 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2251 * more details. 2252 */ 2253 .sys_reg = SYS_ID_AA64PFR0_EL1, 2254 .field_pos = ID_AA64PFR0_EL1_CSV3_SHIFT, 2255 .field_width = 4, 2256 .min_field_value = 1, 2257 .matches = unmap_kernel_at_el0, 2258 .cpu_enable = kpti_install_ng_mappings, 2259 }, 2260 { 2261 /* FP/SIMD is not implemented */ 2262 .capability = ARM64_HAS_NO_FPSIMD, 2263 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2264 .min_field_value = 0, 2265 .matches = has_no_fpsimd, 2266 }, 2267 #ifdef CONFIG_ARM64_PMEM 2268 { 2269 .desc = "Data cache clean to Point of Persistence", 2270 .capability = ARM64_HAS_DCPOP, 2271 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2272 .matches = has_cpuid_feature, 2273 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2274 .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT, 2275 .field_width = 4, 2276 .min_field_value = 1, 2277 }, 2278 { 2279 .desc = "Data cache clean to Point of Deep Persistence", 2280 .capability = ARM64_HAS_DCPODP, 2281 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2282 .matches = has_cpuid_feature, 2283 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2284 .sign = FTR_UNSIGNED, 2285 .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT, 2286 .field_width = 4, 2287 .min_field_value = 2, 2288 }, 2289 #endif 2290 #ifdef CONFIG_ARM64_SVE 2291 { 2292 .desc = "Scalable Vector Extension", 2293 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2294 .capability = ARM64_SVE, 2295 .sys_reg = SYS_ID_AA64PFR0_EL1, 2296 .sign = FTR_UNSIGNED, 2297 .field_pos = ID_AA64PFR0_EL1_SVE_SHIFT, 2298 .field_width = 4, 2299 .min_field_value = ID_AA64PFR0_EL1_SVE_IMP, 2300 .matches = has_cpuid_feature, 2301 .cpu_enable = sve_kernel_enable, 2302 }, 2303 #endif /* CONFIG_ARM64_SVE */ 2304 #ifdef CONFIG_ARM64_RAS_EXTN 2305 { 2306 .desc = "RAS Extension Support", 2307 .capability = ARM64_HAS_RAS_EXTN, 2308 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2309 .matches = has_cpuid_feature, 2310 .sys_reg = SYS_ID_AA64PFR0_EL1, 2311 .sign = FTR_UNSIGNED, 2312 .field_pos = ID_AA64PFR0_EL1_RAS_SHIFT, 2313 .field_width = 4, 2314 .min_field_value = ID_AA64PFR0_EL1_RAS_IMP, 2315 .cpu_enable = cpu_clear_disr, 2316 }, 2317 #endif /* CONFIG_ARM64_RAS_EXTN */ 2318 #ifdef CONFIG_ARM64_AMU_EXTN 2319 { 2320 /* 2321 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 2322 * Therefore, don't provide .desc as we don't want the detection 2323 * message to be shown until at least one CPU is detected to 2324 * support the feature. 2325 */ 2326 .capability = ARM64_HAS_AMU_EXTN, 2327 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2328 .matches = has_amu, 2329 .sys_reg = SYS_ID_AA64PFR0_EL1, 2330 .sign = FTR_UNSIGNED, 2331 .field_pos = ID_AA64PFR0_EL1_AMU_SHIFT, 2332 .field_width = 4, 2333 .min_field_value = ID_AA64PFR0_EL1_AMU_IMP, 2334 .cpu_enable = cpu_amu_enable, 2335 }, 2336 #endif /* CONFIG_ARM64_AMU_EXTN */ 2337 { 2338 .desc = "Data cache clean to the PoU not required for I/D coherence", 2339 .capability = ARM64_HAS_CACHE_IDC, 2340 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2341 .matches = has_cache_idc, 2342 .cpu_enable = cpu_emulate_effective_ctr, 2343 }, 2344 { 2345 .desc = "Instruction cache invalidation not required for I/D coherence", 2346 .capability = ARM64_HAS_CACHE_DIC, 2347 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2348 .matches = has_cache_dic, 2349 }, 2350 { 2351 .desc = "Stage-2 Force Write-Back", 2352 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2353 .capability = ARM64_HAS_STAGE2_FWB, 2354 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2355 .sign = FTR_UNSIGNED, 2356 .field_pos = ID_AA64MMFR2_EL1_FWB_SHIFT, 2357 .field_width = 4, 2358 .min_field_value = 1, 2359 .matches = has_cpuid_feature, 2360 }, 2361 { 2362 .desc = "ARMv8.4 Translation Table Level", 2363 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2364 .capability = ARM64_HAS_ARMv8_4_TTL, 2365 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2366 .sign = FTR_UNSIGNED, 2367 .field_pos = ID_AA64MMFR2_EL1_TTL_SHIFT, 2368 .field_width = 4, 2369 .min_field_value = 1, 2370 .matches = has_cpuid_feature, 2371 }, 2372 { 2373 .desc = "TLB range maintenance instructions", 2374 .capability = ARM64_HAS_TLB_RANGE, 2375 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2376 .matches = has_cpuid_feature, 2377 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2378 .field_pos = ID_AA64ISAR0_EL1_TLB_SHIFT, 2379 .field_width = 4, 2380 .sign = FTR_UNSIGNED, 2381 .min_field_value = ID_AA64ISAR0_EL1_TLB_RANGE, 2382 }, 2383 #ifdef CONFIG_ARM64_HW_AFDBM 2384 { 2385 /* 2386 * Since we turn this on always, we don't want the user to 2387 * think that the feature is available when it may not be. 2388 * So hide the description. 2389 * 2390 * .desc = "Hardware pagetable Dirty Bit Management", 2391 * 2392 */ 2393 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2394 .capability = ARM64_HW_DBM, 2395 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2396 .sign = FTR_UNSIGNED, 2397 .field_pos = ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 2398 .field_width = 4, 2399 .min_field_value = 2, 2400 .matches = has_hw_dbm, 2401 .cpu_enable = cpu_enable_hw_dbm, 2402 }, 2403 #endif 2404 { 2405 .desc = "CRC32 instructions", 2406 .capability = ARM64_HAS_CRC32, 2407 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2408 .matches = has_cpuid_feature, 2409 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2410 .field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT, 2411 .field_width = 4, 2412 .min_field_value = 1, 2413 }, 2414 { 2415 .desc = "Speculative Store Bypassing Safe (SSBS)", 2416 .capability = ARM64_SSBS, 2417 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2418 .matches = has_cpuid_feature, 2419 .sys_reg = SYS_ID_AA64PFR1_EL1, 2420 .field_pos = ID_AA64PFR1_EL1_SSBS_SHIFT, 2421 .field_width = 4, 2422 .sign = FTR_UNSIGNED, 2423 .min_field_value = ID_AA64PFR1_EL1_SSBS_IMP, 2424 }, 2425 #ifdef CONFIG_ARM64_CNP 2426 { 2427 .desc = "Common not Private translations", 2428 .capability = ARM64_HAS_CNP, 2429 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2430 .matches = has_useable_cnp, 2431 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2432 .sign = FTR_UNSIGNED, 2433 .field_pos = ID_AA64MMFR2_EL1_CnP_SHIFT, 2434 .field_width = 4, 2435 .min_field_value = 1, 2436 .cpu_enable = cpu_enable_cnp, 2437 }, 2438 #endif 2439 { 2440 .desc = "Speculation barrier (SB)", 2441 .capability = ARM64_HAS_SB, 2442 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2443 .matches = has_cpuid_feature, 2444 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2445 .field_pos = ID_AA64ISAR1_EL1_SB_SHIFT, 2446 .field_width = 4, 2447 .sign = FTR_UNSIGNED, 2448 .min_field_value = 1, 2449 }, 2450 #ifdef CONFIG_ARM64_PTR_AUTH 2451 { 2452 .desc = "Address authentication (architected QARMA5 algorithm)", 2453 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2454 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2455 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2456 .sign = FTR_UNSIGNED, 2457 .field_pos = ID_AA64ISAR1_EL1_APA_SHIFT, 2458 .field_width = 4, 2459 .min_field_value = ID_AA64ISAR1_EL1_APA_PAuth, 2460 .matches = has_address_auth_cpucap, 2461 }, 2462 { 2463 .desc = "Address authentication (architected QARMA3 algorithm)", 2464 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2465 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2466 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2467 .sign = FTR_UNSIGNED, 2468 .field_pos = ID_AA64ISAR2_EL1_APA3_SHIFT, 2469 .field_width = 4, 2470 .min_field_value = ID_AA64ISAR2_EL1_APA3_PAuth, 2471 .matches = has_address_auth_cpucap, 2472 }, 2473 { 2474 .desc = "Address authentication (IMP DEF algorithm)", 2475 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2476 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2477 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2478 .sign = FTR_UNSIGNED, 2479 .field_pos = ID_AA64ISAR1_EL1_API_SHIFT, 2480 .field_width = 4, 2481 .min_field_value = ID_AA64ISAR1_EL1_API_PAuth, 2482 .matches = has_address_auth_cpucap, 2483 }, 2484 { 2485 .capability = ARM64_HAS_ADDRESS_AUTH, 2486 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2487 .matches = has_address_auth_metacap, 2488 }, 2489 { 2490 .desc = "Generic authentication (architected QARMA5 algorithm)", 2491 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2492 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2493 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2494 .sign = FTR_UNSIGNED, 2495 .field_pos = ID_AA64ISAR1_EL1_GPA_SHIFT, 2496 .field_width = 4, 2497 .min_field_value = ID_AA64ISAR1_EL1_GPA_IMP, 2498 .matches = has_cpuid_feature, 2499 }, 2500 { 2501 .desc = "Generic authentication (architected QARMA3 algorithm)", 2502 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2503 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2504 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2505 .sign = FTR_UNSIGNED, 2506 .field_pos = ID_AA64ISAR2_EL1_GPA3_SHIFT, 2507 .field_width = 4, 2508 .min_field_value = ID_AA64ISAR2_EL1_GPA3_IMP, 2509 .matches = has_cpuid_feature, 2510 }, 2511 { 2512 .desc = "Generic authentication (IMP DEF algorithm)", 2513 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2514 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2515 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2516 .sign = FTR_UNSIGNED, 2517 .field_pos = ID_AA64ISAR1_EL1_GPI_SHIFT, 2518 .field_width = 4, 2519 .min_field_value = ID_AA64ISAR1_EL1_GPI_IMP, 2520 .matches = has_cpuid_feature, 2521 }, 2522 { 2523 .capability = ARM64_HAS_GENERIC_AUTH, 2524 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2525 .matches = has_generic_auth, 2526 }, 2527 #endif /* CONFIG_ARM64_PTR_AUTH */ 2528 #ifdef CONFIG_ARM64_PSEUDO_NMI 2529 { 2530 /* 2531 * Depends on having GICv3 2532 */ 2533 .desc = "IRQ priority masking", 2534 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2535 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2536 .matches = can_use_gic_priorities, 2537 .sys_reg = SYS_ID_AA64PFR0_EL1, 2538 .field_pos = ID_AA64PFR0_EL1_GIC_SHIFT, 2539 .field_width = 4, 2540 .sign = FTR_UNSIGNED, 2541 .min_field_value = 1, 2542 }, 2543 #endif 2544 #ifdef CONFIG_ARM64_E0PD 2545 { 2546 .desc = "E0PD", 2547 .capability = ARM64_HAS_E0PD, 2548 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2549 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2550 .sign = FTR_UNSIGNED, 2551 .field_width = 4, 2552 .field_pos = ID_AA64MMFR2_EL1_E0PD_SHIFT, 2553 .matches = has_cpuid_feature, 2554 .min_field_value = 1, 2555 .cpu_enable = cpu_enable_e0pd, 2556 }, 2557 #endif 2558 { 2559 .desc = "Random Number Generator", 2560 .capability = ARM64_HAS_RNG, 2561 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2562 .matches = has_cpuid_feature, 2563 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2564 .field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT, 2565 .field_width = 4, 2566 .sign = FTR_UNSIGNED, 2567 .min_field_value = 1, 2568 }, 2569 #ifdef CONFIG_ARM64_BTI 2570 { 2571 .desc = "Branch Target Identification", 2572 .capability = ARM64_BTI, 2573 #ifdef CONFIG_ARM64_BTI_KERNEL 2574 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2575 #else 2576 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2577 #endif 2578 .matches = has_cpuid_feature, 2579 .cpu_enable = bti_enable, 2580 .sys_reg = SYS_ID_AA64PFR1_EL1, 2581 .field_pos = ID_AA64PFR1_EL1_BT_SHIFT, 2582 .field_width = 4, 2583 .min_field_value = ID_AA64PFR1_EL1_BT_IMP, 2584 .sign = FTR_UNSIGNED, 2585 }, 2586 #endif 2587 #ifdef CONFIG_ARM64_MTE 2588 { 2589 .desc = "Memory Tagging Extension", 2590 .capability = ARM64_MTE, 2591 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2592 .matches = has_cpuid_feature, 2593 .sys_reg = SYS_ID_AA64PFR1_EL1, 2594 .field_pos = ID_AA64PFR1_EL1_MTE_SHIFT, 2595 .field_width = 4, 2596 .min_field_value = ID_AA64PFR1_EL1_MTE_MTE2, 2597 .sign = FTR_UNSIGNED, 2598 .cpu_enable = cpu_enable_mte, 2599 }, 2600 { 2601 .desc = "Asymmetric MTE Tag Check Fault", 2602 .capability = ARM64_MTE_ASYMM, 2603 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2604 .matches = has_cpuid_feature, 2605 .sys_reg = SYS_ID_AA64PFR1_EL1, 2606 .field_pos = ID_AA64PFR1_EL1_MTE_SHIFT, 2607 .field_width = 4, 2608 .min_field_value = ID_AA64PFR1_EL1_MTE_MTE3, 2609 .sign = FTR_UNSIGNED, 2610 }, 2611 #endif /* CONFIG_ARM64_MTE */ 2612 { 2613 .desc = "RCpc load-acquire (LDAPR)", 2614 .capability = ARM64_HAS_LDAPR, 2615 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2616 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2617 .sign = FTR_UNSIGNED, 2618 .field_pos = ID_AA64ISAR1_EL1_LRCPC_SHIFT, 2619 .field_width = 4, 2620 .matches = has_cpuid_feature, 2621 .min_field_value = 1, 2622 }, 2623 #ifdef CONFIG_ARM64_SME 2624 { 2625 .desc = "Scalable Matrix Extension", 2626 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2627 .capability = ARM64_SME, 2628 .sys_reg = SYS_ID_AA64PFR1_EL1, 2629 .sign = FTR_UNSIGNED, 2630 .field_pos = ID_AA64PFR1_EL1_SME_SHIFT, 2631 .field_width = 4, 2632 .min_field_value = ID_AA64PFR1_EL1_SME_IMP, 2633 .matches = has_cpuid_feature, 2634 .cpu_enable = sme_kernel_enable, 2635 }, 2636 /* FA64 should be sorted after the base SME capability */ 2637 { 2638 .desc = "FA64", 2639 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2640 .capability = ARM64_SME_FA64, 2641 .sys_reg = SYS_ID_AA64SMFR0_EL1, 2642 .sign = FTR_UNSIGNED, 2643 .field_pos = ID_AA64SMFR0_EL1_FA64_SHIFT, 2644 .field_width = 1, 2645 .min_field_value = ID_AA64SMFR0_EL1_FA64_IMP, 2646 .matches = has_cpuid_feature, 2647 .cpu_enable = fa64_kernel_enable, 2648 }, 2649 #endif /* CONFIG_ARM64_SME */ 2650 { 2651 .desc = "WFx with timeout", 2652 .capability = ARM64_HAS_WFXT, 2653 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2654 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2655 .sign = FTR_UNSIGNED, 2656 .field_pos = ID_AA64ISAR2_EL1_WFxT_SHIFT, 2657 .field_width = 4, 2658 .matches = has_cpuid_feature, 2659 .min_field_value = ID_AA64ISAR2_EL1_WFxT_IMP, 2660 }, 2661 { 2662 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2663 .capability = ARM64_HAS_TIDCP1, 2664 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2665 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2666 .sign = FTR_UNSIGNED, 2667 .field_pos = ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 2668 .field_width = 4, 2669 .min_field_value = ID_AA64MMFR1_EL1_TIDCP1_IMP, 2670 .matches = has_cpuid_feature, 2671 .cpu_enable = cpu_trap_el0_impdef, 2672 }, 2673 { 2674 .desc = "Data independent timing control (DIT)", 2675 .capability = ARM64_HAS_DIT, 2676 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2677 .sys_reg = SYS_ID_AA64PFR0_EL1, 2678 .sign = FTR_UNSIGNED, 2679 .field_pos = ID_AA64PFR0_EL1_DIT_SHIFT, 2680 .field_width = 4, 2681 .min_field_value = ID_AA64PFR0_EL1_DIT_IMP, 2682 .matches = has_cpuid_feature, 2683 .cpu_enable = cpu_enable_dit, 2684 }, 2685 {}, 2686 }; 2687 2688 #define HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ 2689 .matches = has_user_cpuid_feature, \ 2690 .sys_reg = reg, \ 2691 .field_pos = field, \ 2692 .field_width = width, \ 2693 .sign = s, \ 2694 .min_field_value = min_value, 2695 2696 #define __HWCAP_CAP(name, cap_type, cap) \ 2697 .desc = name, \ 2698 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2699 .hwcap_type = cap_type, \ 2700 .hwcap = cap, \ 2701 2702 #define HWCAP_CAP(reg, field, width, s, min_value, cap_type, cap) \ 2703 { \ 2704 __HWCAP_CAP(#cap, cap_type, cap) \ 2705 HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ 2706 } 2707 2708 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2709 { \ 2710 __HWCAP_CAP(#cap, cap_type, cap) \ 2711 .matches = cpucap_multi_entry_cap_matches, \ 2712 .match_list = list, \ 2713 } 2714 2715 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2716 { \ 2717 __HWCAP_CAP(#cap, cap_type, cap) \ 2718 .matches = match, \ 2719 } 2720 2721 #ifdef CONFIG_ARM64_PTR_AUTH 2722 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2723 { 2724 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_APA_SHIFT, 2725 4, FTR_UNSIGNED, 2726 ID_AA64ISAR1_EL1_APA_PAuth) 2727 }, 2728 { 2729 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_APA3_SHIFT, 2730 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_APA3_PAuth) 2731 }, 2732 { 2733 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT, 2734 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_API_PAuth) 2735 }, 2736 {}, 2737 }; 2738 2739 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2740 { 2741 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPA_SHIFT, 2742 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP) 2743 }, 2744 { 2745 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_GPA3_SHIFT, 2746 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_GPA3_IMP) 2747 }, 2748 { 2749 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT, 2750 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPI_IMP) 2751 }, 2752 {}, 2753 }; 2754 #endif 2755 2756 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2757 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2758 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2759 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2760 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2761 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2762 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2763 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2764 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2765 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2766 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2767 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2768 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2769 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2770 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2771 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2772 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2773 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2774 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2775 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2776 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2777 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2778 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2779 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2780 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2781 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2782 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2783 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2784 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2785 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2786 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2787 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_EBF16), 2788 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2789 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2790 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_EL1_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2791 #ifdef CONFIG_ARM64_SVE 2792 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_EL1_SVE_IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 2793 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2794 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2795 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2796 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BitPerm_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2797 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2798 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 2799 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SHA3_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2800 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SM4_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2801 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_I8MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2802 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F32MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2803 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F64MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2804 #endif 2805 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_SSBS_SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2806 #ifdef CONFIG_ARM64_BTI 2807 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_BT_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_BT_IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 2808 #endif 2809 #ifdef CONFIG_ARM64_PTR_AUTH 2810 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2811 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2812 #endif 2813 #ifdef CONFIG_ARM64_MTE 2814 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 2815 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 2816 #endif /* CONFIG_ARM64_MTE */ 2817 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), 2818 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), 2819 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_CSSC_IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 2820 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2821 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 2822 #ifdef CONFIG_ARM64_SME 2823 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_SME_IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 2824 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 2825 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I16I64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 2826 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F64F64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 2827 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I8I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 2828 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 2829 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_B16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 2830 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F32F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 2831 #endif /* CONFIG_ARM64_SME */ 2832 {}, 2833 }; 2834 2835 #ifdef CONFIG_COMPAT 2836 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2837 { 2838 /* 2839 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2840 * in line with that of arm32 as in vfp_init(). We make sure that the 2841 * check is future proof, by making sure value is non-zero. 2842 */ 2843 u32 mvfr1; 2844 2845 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2846 if (scope == SCOPE_SYSTEM) 2847 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2848 else 2849 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2850 2851 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2852 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2853 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2854 } 2855 #endif 2856 2857 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2858 #ifdef CONFIG_COMPAT 2859 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2860 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2861 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2862 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2863 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2864 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2865 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2866 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2867 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2868 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2869 #endif 2870 {}, 2871 }; 2872 2873 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2874 { 2875 switch (cap->hwcap_type) { 2876 case CAP_HWCAP: 2877 cpu_set_feature(cap->hwcap); 2878 break; 2879 #ifdef CONFIG_COMPAT 2880 case CAP_COMPAT_HWCAP: 2881 compat_elf_hwcap |= (u32)cap->hwcap; 2882 break; 2883 case CAP_COMPAT_HWCAP2: 2884 compat_elf_hwcap2 |= (u32)cap->hwcap; 2885 break; 2886 #endif 2887 default: 2888 WARN_ON(1); 2889 break; 2890 } 2891 } 2892 2893 /* Check if we have a particular HWCAP enabled */ 2894 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2895 { 2896 bool rc; 2897 2898 switch (cap->hwcap_type) { 2899 case CAP_HWCAP: 2900 rc = cpu_have_feature(cap->hwcap); 2901 break; 2902 #ifdef CONFIG_COMPAT 2903 case CAP_COMPAT_HWCAP: 2904 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2905 break; 2906 case CAP_COMPAT_HWCAP2: 2907 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2908 break; 2909 #endif 2910 default: 2911 WARN_ON(1); 2912 rc = false; 2913 } 2914 2915 return rc; 2916 } 2917 2918 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2919 { 2920 /* We support emulation of accesses to CPU ID feature registers */ 2921 cpu_set_named_feature(CPUID); 2922 for (; hwcaps->matches; hwcaps++) 2923 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2924 cap_set_elf_hwcap(hwcaps); 2925 } 2926 2927 static void update_cpu_capabilities(u16 scope_mask) 2928 { 2929 int i; 2930 const struct arm64_cpu_capabilities *caps; 2931 2932 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2933 for (i = 0; i < ARM64_NCAPS; i++) { 2934 caps = cpu_hwcaps_ptrs[i]; 2935 if (!caps || !(caps->type & scope_mask) || 2936 cpus_have_cap(caps->capability) || 2937 !caps->matches(caps, cpucap_default_scope(caps))) 2938 continue; 2939 2940 if (caps->desc) 2941 pr_info("detected: %s\n", caps->desc); 2942 cpus_set_cap(caps->capability); 2943 2944 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2945 set_bit(caps->capability, boot_capabilities); 2946 } 2947 } 2948 2949 /* 2950 * Enable all the available capabilities on this CPU. The capabilities 2951 * with BOOT_CPU scope are handled separately and hence skipped here. 2952 */ 2953 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2954 { 2955 int i; 2956 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2957 2958 for_each_available_cap(i) { 2959 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2960 2961 if (WARN_ON(!cap)) 2962 continue; 2963 2964 if (!(cap->type & non_boot_scope)) 2965 continue; 2966 2967 if (cap->cpu_enable) 2968 cap->cpu_enable(cap); 2969 } 2970 return 0; 2971 } 2972 2973 /* 2974 * Run through the enabled capabilities and enable() it on all active 2975 * CPUs 2976 */ 2977 static void __init enable_cpu_capabilities(u16 scope_mask) 2978 { 2979 int i; 2980 const struct arm64_cpu_capabilities *caps; 2981 bool boot_scope; 2982 2983 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2984 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2985 2986 for (i = 0; i < ARM64_NCAPS; i++) { 2987 unsigned int num; 2988 2989 caps = cpu_hwcaps_ptrs[i]; 2990 if (!caps || !(caps->type & scope_mask)) 2991 continue; 2992 num = caps->capability; 2993 if (!cpus_have_cap(num)) 2994 continue; 2995 2996 if (boot_scope && caps->cpu_enable) 2997 /* 2998 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2999 * before any secondary CPU boots. Thus, each secondary 3000 * will enable the capability as appropriate via 3001 * check_local_cpu_capabilities(). The only exception is 3002 * the boot CPU, for which the capability must be 3003 * enabled here. This approach avoids costly 3004 * stop_machine() calls for this case. 3005 */ 3006 caps->cpu_enable(caps); 3007 } 3008 3009 /* 3010 * For all non-boot scope capabilities, use stop_machine() 3011 * as it schedules the work allowing us to modify PSTATE, 3012 * instead of on_each_cpu() which uses an IPI, giving us a 3013 * PSTATE that disappears when we return. 3014 */ 3015 if (!boot_scope) 3016 stop_machine(cpu_enable_non_boot_scope_capabilities, 3017 NULL, cpu_online_mask); 3018 } 3019 3020 /* 3021 * Run through the list of capabilities to check for conflicts. 3022 * If the system has already detected a capability, take necessary 3023 * action on this CPU. 3024 */ 3025 static void verify_local_cpu_caps(u16 scope_mask) 3026 { 3027 int i; 3028 bool cpu_has_cap, system_has_cap; 3029 const struct arm64_cpu_capabilities *caps; 3030 3031 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3032 3033 for (i = 0; i < ARM64_NCAPS; i++) { 3034 caps = cpu_hwcaps_ptrs[i]; 3035 if (!caps || !(caps->type & scope_mask)) 3036 continue; 3037 3038 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3039 system_has_cap = cpus_have_cap(caps->capability); 3040 3041 if (system_has_cap) { 3042 /* 3043 * Check if the new CPU misses an advertised feature, 3044 * which is not safe to miss. 3045 */ 3046 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3047 break; 3048 /* 3049 * We have to issue cpu_enable() irrespective of 3050 * whether the CPU has it or not, as it is enabeld 3051 * system wide. It is upto the call back to take 3052 * appropriate action on this CPU. 3053 */ 3054 if (caps->cpu_enable) 3055 caps->cpu_enable(caps); 3056 } else { 3057 /* 3058 * Check if the CPU has this capability if it isn't 3059 * safe to have when the system doesn't. 3060 */ 3061 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3062 break; 3063 } 3064 } 3065 3066 if (i < ARM64_NCAPS) { 3067 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3068 smp_processor_id(), caps->capability, 3069 caps->desc, system_has_cap, cpu_has_cap); 3070 3071 if (cpucap_panic_on_conflict(caps)) 3072 cpu_panic_kernel(); 3073 else 3074 cpu_die_early(); 3075 } 3076 } 3077 3078 /* 3079 * Check for CPU features that are used in early boot 3080 * based on the Boot CPU value. 3081 */ 3082 static void check_early_cpu_features(void) 3083 { 3084 verify_cpu_asid_bits(); 3085 3086 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3087 } 3088 3089 static void 3090 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3091 { 3092 3093 for (; caps->matches; caps++) 3094 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3095 pr_crit("CPU%d: missing HWCAP: %s\n", 3096 smp_processor_id(), caps->desc); 3097 cpu_die_early(); 3098 } 3099 } 3100 3101 static void verify_local_elf_hwcaps(void) 3102 { 3103 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3104 3105 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3106 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3107 } 3108 3109 static void verify_sve_features(void) 3110 { 3111 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 3112 u64 zcr = read_zcr_features(); 3113 3114 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 3115 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 3116 3117 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) { 3118 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3119 smp_processor_id()); 3120 cpu_die_early(); 3121 } 3122 3123 /* Add checks on other ZCR bits here if necessary */ 3124 } 3125 3126 static void verify_sme_features(void) 3127 { 3128 u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1); 3129 u64 smcr = read_smcr_features(); 3130 3131 unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK; 3132 unsigned int len = smcr & SMCR_ELx_LEN_MASK; 3133 3134 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) { 3135 pr_crit("CPU%d: SME: vector length support mismatch\n", 3136 smp_processor_id()); 3137 cpu_die_early(); 3138 } 3139 3140 /* Add checks on other SMCR bits here if necessary */ 3141 } 3142 3143 static void verify_hyp_capabilities(void) 3144 { 3145 u64 safe_mmfr1, mmfr0, mmfr1; 3146 int parange, ipa_max; 3147 unsigned int safe_vmid_bits, vmid_bits; 3148 3149 if (!IS_ENABLED(CONFIG_KVM)) 3150 return; 3151 3152 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3153 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3154 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3155 3156 /* Verify VMID bits */ 3157 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3158 vmid_bits = get_vmid_bits(mmfr1); 3159 if (vmid_bits < safe_vmid_bits) { 3160 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3161 cpu_die_early(); 3162 } 3163 3164 /* Verify IPA range */ 3165 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3166 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3167 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3168 if (ipa_max < get_kvm_ipa_limit()) { 3169 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3170 cpu_die_early(); 3171 } 3172 } 3173 3174 /* 3175 * Run through the enabled system capabilities and enable() it on this CPU. 3176 * The capabilities were decided based on the available CPUs at the boot time. 3177 * Any new CPU should match the system wide status of the capability. If the 3178 * new CPU doesn't have a capability which the system now has enabled, we 3179 * cannot do anything to fix it up and could cause unexpected failures. So 3180 * we park the CPU. 3181 */ 3182 static void verify_local_cpu_capabilities(void) 3183 { 3184 /* 3185 * The capabilities with SCOPE_BOOT_CPU are checked from 3186 * check_early_cpu_features(), as they need to be verified 3187 * on all secondary CPUs. 3188 */ 3189 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3190 verify_local_elf_hwcaps(); 3191 3192 if (system_supports_sve()) 3193 verify_sve_features(); 3194 3195 if (system_supports_sme()) 3196 verify_sme_features(); 3197 3198 if (is_hyp_mode_available()) 3199 verify_hyp_capabilities(); 3200 } 3201 3202 void check_local_cpu_capabilities(void) 3203 { 3204 /* 3205 * All secondary CPUs should conform to the early CPU features 3206 * in use by the kernel based on boot CPU. 3207 */ 3208 check_early_cpu_features(); 3209 3210 /* 3211 * If we haven't finalised the system capabilities, this CPU gets 3212 * a chance to update the errata work arounds and local features. 3213 * Otherwise, this CPU should verify that it has all the system 3214 * advertised capabilities. 3215 */ 3216 if (!system_capabilities_finalized()) 3217 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3218 else 3219 verify_local_cpu_capabilities(); 3220 } 3221 3222 static void __init setup_boot_cpu_capabilities(void) 3223 { 3224 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 3225 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3226 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 3227 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3228 } 3229 3230 bool this_cpu_has_cap(unsigned int n) 3231 { 3232 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3233 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 3234 3235 if (cap) 3236 return cap->matches(cap, SCOPE_LOCAL_CPU); 3237 } 3238 3239 return false; 3240 } 3241 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3242 3243 /* 3244 * This helper function is used in a narrow window when, 3245 * - The system wide safe registers are set with all the SMP CPUs and, 3246 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 3247 * In all other cases cpus_have_{const_}cap() should be used. 3248 */ 3249 static bool __maybe_unused __system_matches_cap(unsigned int n) 3250 { 3251 if (n < ARM64_NCAPS) { 3252 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 3253 3254 if (cap) 3255 return cap->matches(cap, SCOPE_SYSTEM); 3256 } 3257 return false; 3258 } 3259 3260 void cpu_set_feature(unsigned int num) 3261 { 3262 set_bit(num, elf_hwcap); 3263 } 3264 3265 bool cpu_have_feature(unsigned int num) 3266 { 3267 return test_bit(num, elf_hwcap); 3268 } 3269 EXPORT_SYMBOL_GPL(cpu_have_feature); 3270 3271 unsigned long cpu_get_elf_hwcap(void) 3272 { 3273 /* 3274 * We currently only populate the first 32 bits of AT_HWCAP. Please 3275 * note that for userspace compatibility we guarantee that bits 62 3276 * and 63 will always be returned as 0. 3277 */ 3278 return elf_hwcap[0]; 3279 } 3280 3281 unsigned long cpu_get_elf_hwcap2(void) 3282 { 3283 return elf_hwcap[1]; 3284 } 3285 3286 static void __init setup_system_capabilities(void) 3287 { 3288 /* 3289 * We have finalised the system-wide safe feature 3290 * registers, finalise the capabilities that depend 3291 * on it. Also enable all the available capabilities, 3292 * that are not enabled already. 3293 */ 3294 update_cpu_capabilities(SCOPE_SYSTEM); 3295 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3296 } 3297 3298 void __init setup_cpu_features(void) 3299 { 3300 u32 cwg; 3301 3302 setup_system_capabilities(); 3303 setup_elf_hwcaps(arm64_elf_hwcaps); 3304 3305 if (system_supports_32bit_el0()) { 3306 setup_elf_hwcaps(compat_elf_hwcaps); 3307 elf_hwcap_fixup(); 3308 } 3309 3310 if (system_uses_ttbr0_pan()) 3311 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3312 3313 sve_setup(); 3314 sme_setup(); 3315 minsigstksz_setup(); 3316 3317 /* 3318 * Check for sane CTR_EL0.CWG value. 3319 */ 3320 cwg = cache_type_cwg(); 3321 if (!cwg) 3322 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3323 ARCH_DMA_MINALIGN); 3324 } 3325 3326 static int enable_mismatched_32bit_el0(unsigned int cpu) 3327 { 3328 /* 3329 * The first 32-bit-capable CPU we detected and so can no longer 3330 * be offlined by userspace. -1 indicates we haven't yet onlined 3331 * a 32-bit-capable CPU. 3332 */ 3333 static int lucky_winner = -1; 3334 3335 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3336 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3337 3338 if (cpu_32bit) { 3339 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3340 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3341 } 3342 3343 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3344 return 0; 3345 3346 if (lucky_winner >= 0) 3347 return 0; 3348 3349 /* 3350 * We've detected a mismatch. We need to keep one of our CPUs with 3351 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3352 * every CPU in the system for a 32-bit task. 3353 */ 3354 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3355 cpu_active_mask); 3356 get_cpu_device(lucky_winner)->offline_disabled = true; 3357 setup_elf_hwcaps(compat_elf_hwcaps); 3358 elf_hwcap_fixup(); 3359 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3360 cpu, lucky_winner); 3361 return 0; 3362 } 3363 3364 static int __init init_32bit_el0_mask(void) 3365 { 3366 if (!allow_mismatched_32bit_el0) 3367 return 0; 3368 3369 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3370 return -ENOMEM; 3371 3372 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3373 "arm64/mismatched_32bit_el0:online", 3374 enable_mismatched_32bit_el0, NULL); 3375 } 3376 subsys_initcall_sync(init_32bit_el0_mask); 3377 3378 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3379 { 3380 cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir); 3381 } 3382 3383 /* 3384 * We emulate only the following system register space. 3385 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3386 * See Table C5-6 System instruction encodings for System register accesses, 3387 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3388 */ 3389 static inline bool __attribute_const__ is_emulated(u32 id) 3390 { 3391 return (sys_reg_Op0(id) == 0x3 && 3392 sys_reg_CRn(id) == 0x0 && 3393 sys_reg_Op1(id) == 0x0 && 3394 (sys_reg_CRm(id) == 0 || 3395 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3396 } 3397 3398 /* 3399 * With CRm == 0, reg should be one of : 3400 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3401 */ 3402 static inline int emulate_id_reg(u32 id, u64 *valp) 3403 { 3404 switch (id) { 3405 case SYS_MIDR_EL1: 3406 *valp = read_cpuid_id(); 3407 break; 3408 case SYS_MPIDR_EL1: 3409 *valp = SYS_MPIDR_SAFE_VAL; 3410 break; 3411 case SYS_REVIDR_EL1: 3412 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3413 *valp = 0; 3414 break; 3415 default: 3416 return -EINVAL; 3417 } 3418 3419 return 0; 3420 } 3421 3422 static int emulate_sys_reg(u32 id, u64 *valp) 3423 { 3424 struct arm64_ftr_reg *regp; 3425 3426 if (!is_emulated(id)) 3427 return -EINVAL; 3428 3429 if (sys_reg_CRm(id) == 0) 3430 return emulate_id_reg(id, valp); 3431 3432 regp = get_arm64_ftr_reg_nowarn(id); 3433 if (regp) 3434 *valp = arm64_ftr_reg_user_value(regp); 3435 else 3436 /* 3437 * The untracked registers are either IMPLEMENTATION DEFINED 3438 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3439 */ 3440 *valp = 0; 3441 return 0; 3442 } 3443 3444 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3445 { 3446 int rc; 3447 u64 val; 3448 3449 rc = emulate_sys_reg(sys_reg, &val); 3450 if (!rc) { 3451 pt_regs_write_reg(regs, rt, val); 3452 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3453 } 3454 return rc; 3455 } 3456 3457 static int emulate_mrs(struct pt_regs *regs, u32 insn) 3458 { 3459 u32 sys_reg, rt; 3460 3461 /* 3462 * sys_reg values are defined as used in mrs/msr instruction. 3463 * shift the imm value to get the encoding. 3464 */ 3465 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3466 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3467 return do_emulate_mrs(regs, sys_reg, rt); 3468 } 3469 3470 static struct undef_hook mrs_hook = { 3471 .instr_mask = 0xffff0000, 3472 .instr_val = 0xd5380000, 3473 .pstate_mask = PSR_AA32_MODE_MASK, 3474 .pstate_val = PSR_MODE_EL0t, 3475 .fn = emulate_mrs, 3476 }; 3477 3478 static int __init enable_mrs_emulation(void) 3479 { 3480 register_undef_hook(&mrs_hook); 3481 return 0; 3482 } 3483 3484 core_initcall(enable_mrs_emulation); 3485 3486 enum mitigation_state arm64_get_meltdown_state(void) 3487 { 3488 if (__meltdown_safe) 3489 return SPECTRE_UNAFFECTED; 3490 3491 if (arm64_kernel_unmapped_at_el0()) 3492 return SPECTRE_MITIGATED; 3493 3494 return SPECTRE_VULNERABLE; 3495 } 3496 3497 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3498 char *buf) 3499 { 3500 switch (arm64_get_meltdown_state()) { 3501 case SPECTRE_UNAFFECTED: 3502 return sprintf(buf, "Not affected\n"); 3503 3504 case SPECTRE_MITIGATED: 3505 return sprintf(buf, "Mitigation: PTI\n"); 3506 3507 default: 3508 return sprintf(buf, "Vulnerable\n"); 3509 } 3510 } 3511