1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/types.h> 71 #include <linux/mm.h> 72 #include <linux/cpu.h> 73 #include <asm/cpu.h> 74 #include <asm/cpufeature.h> 75 #include <asm/cpu_ops.h> 76 #include <asm/fpsimd.h> 77 #include <asm/mmu_context.h> 78 #include <asm/processor.h> 79 #include <asm/sysreg.h> 80 #include <asm/traps.h> 81 #include <asm/virt.h> 82 83 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 84 static unsigned long elf_hwcap __read_mostly; 85 86 #ifdef CONFIG_COMPAT 87 #define COMPAT_ELF_HWCAP_DEFAULT \ 88 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 89 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 90 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 91 COMPAT_HWCAP_LPAE) 92 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 93 unsigned int compat_elf_hwcap2 __read_mostly; 94 #endif 95 96 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 97 EXPORT_SYMBOL(cpu_hwcaps); 98 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 99 100 /* Need also bit for ARM64_CB_PATCH */ 101 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 102 103 bool arm64_use_ng_mappings = false; 104 EXPORT_SYMBOL(arm64_use_ng_mappings); 105 106 /* 107 * Flag to indicate if we have computed the system wide 108 * capabilities based on the boot time active CPUs. This 109 * will be used to determine if a new booting CPU should 110 * go through the verification process to make sure that it 111 * supports the system capabilities, without using a hotplug 112 * notifier. This is also used to decide if we could use 113 * the fast path for checking constant CPU caps. 114 */ 115 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 116 EXPORT_SYMBOL(arm64_const_caps_ready); 117 static inline void finalize_system_capabilities(void) 118 { 119 static_branch_enable(&arm64_const_caps_ready); 120 } 121 122 void dump_cpu_features(void) 123 { 124 /* file-wide pr_fmt adds "CPU features: " prefix */ 125 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 126 } 127 128 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 129 EXPORT_SYMBOL(cpu_hwcap_keys); 130 131 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 132 { \ 133 .sign = SIGNED, \ 134 .visible = VISIBLE, \ 135 .strict = STRICT, \ 136 .type = TYPE, \ 137 .shift = SHIFT, \ 138 .width = WIDTH, \ 139 .safe_val = SAFE_VAL, \ 140 } 141 142 /* Define a feature with unsigned values */ 143 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 144 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 145 146 /* Define a feature with a signed value */ 147 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 148 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 149 150 #define ARM64_FTR_END \ 151 { \ 152 .width = 0, \ 153 } 154 155 /* meta feature for alternatives */ 156 static bool __maybe_unused 157 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused); 158 159 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 160 161 static bool __system_matches_cap(unsigned int n); 162 163 /* 164 * NOTE: Any changes to the visibility of features should be kept in 165 * sync with the documentation of the CPU feature register ABI. 166 */ 167 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 168 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), 169 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0), 170 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 171 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 172 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 173 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 174 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 175 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 176 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 182 ARM64_FTR_END, 183 }; 184 185 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 192 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 193 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 195 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 199 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 200 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 202 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 204 ARM64_FTR_END, 205 }; 206 207 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 208 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 215 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 218 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 219 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 224 ARM64_FTR_END, 225 }; 226 227 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 231 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 232 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 233 ARM64_FTR_END, 234 }; 235 236 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 237 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 238 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 240 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 242 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 244 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 246 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 248 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 250 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 252 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 254 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 255 ARM64_FTR_END, 256 }; 257 258 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), 262 /* 263 * Page size not being supported at Stage-2 is not fatal. You 264 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 265 * your favourite nesting hypervisor. 266 * 267 * There is a small corner case where the hypervisor explicitly 268 * advertises a given granule size at Stage-2 (value 2) on some 269 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 270 * vCPUs. Although this is not forbidden by the architecture, it 271 * indicates that the hypervisor is being silly (or buggy). 272 * 273 * We make no effort to cope with this and pretend that if these 274 * fields are inconsistent across vCPUs, then it isn't worth 275 * trying to bring KVM up. 276 */ 277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 280 /* 281 * We already refuse to boot CPUs that don't support our configured 282 * page size, so we can only detect mismatches for a page size other 283 * than the one we're currently using. Unfortunately, SoCs like this 284 * exist in the wild so, even though we don't like it, we'll have to go 285 * along with it and treat them as non-strict. 286 */ 287 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 288 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 290 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 292 /* Linux shouldn't care about secure memory */ 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 296 /* 297 * Differing PARange is fine as long as all peripherals and memory are mapped 298 * within the minimum PARange of all CPUs 299 */ 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 301 ARM64_FTR_END, 302 }; 303 304 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 315 ARM64_FTR_END, 316 }; 317 318 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0), 325 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0), 327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0), 329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 334 ARM64_FTR_END, 335 }; 336 337 static const struct arm64_ftr_bits ftr_ctr[] = { 338 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 339 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 340 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 341 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 342 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 344 /* 345 * Linux can handle differing I-cache policies. Userspace JITs will 346 * make use of *minLine. 347 * If we have differing I-cache policies, report it as the weakest - VIPT. 348 */ 349 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 350 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 351 ARM64_FTR_END, 352 }; 353 354 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 355 .name = "SYS_CTR_EL0", 356 .ftr_bits = ftr_ctr 357 }; 358 359 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 360 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 361 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 365 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 368 ARM64_FTR_END, 369 }; 370 371 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 372 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 377 /* 378 * We can instantiate multiple PMU instances with different levels 379 * of support. 380 */ 381 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 382 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), 383 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 384 ARM64_FTR_END, 385 }; 386 387 static const struct arm64_ftr_bits ftr_mvfr2[] = { 388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 390 ARM64_FTR_END, 391 }; 392 393 static const struct arm64_ftr_bits ftr_dczid[] = { 394 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), 395 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), 396 ARM64_FTR_END, 397 }; 398 399 static const struct arm64_ftr_bits ftr_id_isar0[] = { 400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 401 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 403 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 407 ARM64_FTR_END, 408 }; 409 410 static const struct arm64_ftr_bits ftr_id_isar5[] = { 411 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 417 ARM64_FTR_END, 418 }; 419 420 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 423 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 428 429 /* 430 * SpecSEI = 1 indicates that the PE might generate an SError on an 431 * external abort on speculative read. It is safe to assume that an 432 * SError might be generated than it will not be. Hence it has been 433 * classified as FTR_HIGHER_SAFE. 434 */ 435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 436 ARM64_FTR_END, 437 }; 438 439 static const struct arm64_ftr_bits ftr_id_isar4[] = { 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 448 ARM64_FTR_END, 449 }; 450 451 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 453 ARM64_FTR_END, 454 }; 455 456 static const struct arm64_ftr_bits ftr_id_isar6[] = { 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 464 ARM64_FTR_END, 465 }; 466 467 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 474 ARM64_FTR_END, 475 }; 476 477 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 486 ARM64_FTR_END, 487 }; 488 489 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 492 ARM64_FTR_END, 493 }; 494 495 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 496 /* [31:28] TraceFilt */ 497 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 504 ARM64_FTR_END, 505 }; 506 507 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 508 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 509 ARM64_FTR_END, 510 }; 511 512 static const struct arm64_ftr_bits ftr_zcr[] = { 513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 514 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 515 ARM64_FTR_END, 516 }; 517 518 /* 519 * Common ftr bits for a 32bit register with all hidden, strict 520 * attributes, with 4bit feature fields and a default safe value of 521 * 0. Covers the following 32bit registers: 522 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 523 */ 524 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 533 ARM64_FTR_END, 534 }; 535 536 /* Table for a single 32bit feature value */ 537 static const struct arm64_ftr_bits ftr_single32[] = { 538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 539 ARM64_FTR_END, 540 }; 541 542 static const struct arm64_ftr_bits ftr_raz[] = { 543 ARM64_FTR_END, 544 }; 545 546 #define ARM64_FTR_REG(id, table) { \ 547 .sys_id = id, \ 548 .reg = &(struct arm64_ftr_reg){ \ 549 .name = #id, \ 550 .ftr_bits = &((table)[0]), \ 551 }} 552 553 static const struct __ftr_reg_entry { 554 u32 sys_id; 555 struct arm64_ftr_reg *reg; 556 } arm64_ftr_regs[] = { 557 558 /* Op1 = 0, CRn = 0, CRm = 1 */ 559 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 560 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 561 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 562 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 563 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 564 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 565 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 566 567 /* Op1 = 0, CRn = 0, CRm = 2 */ 568 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 569 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 570 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 571 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 572 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 573 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 574 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 575 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 576 577 /* Op1 = 0, CRn = 0, CRm = 3 */ 578 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 579 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 580 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 581 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 582 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 583 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 584 585 /* Op1 = 0, CRn = 0, CRm = 4 */ 586 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 587 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1), 588 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 589 590 /* Op1 = 0, CRn = 0, CRm = 5 */ 591 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 592 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 593 594 /* Op1 = 0, CRn = 0, CRm = 6 */ 595 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 596 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), 597 598 /* Op1 = 0, CRn = 0, CRm = 7 */ 599 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 600 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), 601 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 602 603 /* Op1 = 0, CRn = 1, CRm = 2 */ 604 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 605 606 /* Op1 = 3, CRn = 0, CRm = 0 */ 607 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 608 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 609 610 /* Op1 = 3, CRn = 14, CRm = 0 */ 611 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 612 }; 613 614 static int search_cmp_ftr_reg(const void *id, const void *regp) 615 { 616 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 617 } 618 619 /* 620 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 621 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 622 * ascending order of sys_id, we use binary search to find a matching 623 * entry. 624 * 625 * returns - Upon success, matching ftr_reg entry for id. 626 * - NULL on failure. It is upto the caller to decide 627 * the impact of a failure. 628 */ 629 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 630 { 631 const struct __ftr_reg_entry *ret; 632 633 ret = bsearch((const void *)(unsigned long)sys_id, 634 arm64_ftr_regs, 635 ARRAY_SIZE(arm64_ftr_regs), 636 sizeof(arm64_ftr_regs[0]), 637 search_cmp_ftr_reg); 638 if (ret) 639 return ret->reg; 640 return NULL; 641 } 642 643 /* 644 * get_arm64_ftr_reg - Looks up a feature register entry using 645 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 646 * 647 * returns - Upon success, matching ftr_reg entry for id. 648 * - NULL on failure but with an WARN_ON(). 649 */ 650 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 651 { 652 struct arm64_ftr_reg *reg; 653 654 reg = get_arm64_ftr_reg_nowarn(sys_id); 655 656 /* 657 * Requesting a non-existent register search is an error. Warn 658 * and let the caller handle it. 659 */ 660 WARN_ON(!reg); 661 return reg; 662 } 663 664 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 665 s64 ftr_val) 666 { 667 u64 mask = arm64_ftr_mask(ftrp); 668 669 reg &= ~mask; 670 reg |= (ftr_val << ftrp->shift) & mask; 671 return reg; 672 } 673 674 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 675 s64 cur) 676 { 677 s64 ret = 0; 678 679 switch (ftrp->type) { 680 case FTR_EXACT: 681 ret = ftrp->safe_val; 682 break; 683 case FTR_LOWER_SAFE: 684 ret = new < cur ? new : cur; 685 break; 686 case FTR_HIGHER_OR_ZERO_SAFE: 687 if (!cur || !new) 688 break; 689 /* Fallthrough */ 690 case FTR_HIGHER_SAFE: 691 ret = new > cur ? new : cur; 692 break; 693 default: 694 BUG(); 695 } 696 697 return ret; 698 } 699 700 static void __init sort_ftr_regs(void) 701 { 702 unsigned int i; 703 704 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 705 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 706 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 707 unsigned int j = 0; 708 709 /* 710 * Features here must be sorted in descending order with respect 711 * to their shift values and should not overlap with each other. 712 */ 713 for (; ftr_bits->width != 0; ftr_bits++, j++) { 714 unsigned int width = ftr_reg->ftr_bits[j].width; 715 unsigned int shift = ftr_reg->ftr_bits[j].shift; 716 unsigned int prev_shift; 717 718 WARN((shift + width) > 64, 719 "%s has invalid feature at shift %d\n", 720 ftr_reg->name, shift); 721 722 /* 723 * Skip the first feature. There is nothing to 724 * compare against for now. 725 */ 726 if (j == 0) 727 continue; 728 729 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 730 WARN((shift + width) > prev_shift, 731 "%s has feature overlap at shift %d\n", 732 ftr_reg->name, shift); 733 } 734 735 /* 736 * Skip the first register. There is nothing to 737 * compare against for now. 738 */ 739 if (i == 0) 740 continue; 741 /* 742 * Registers here must be sorted in ascending order with respect 743 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 744 * to work correctly. 745 */ 746 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 747 } 748 } 749 750 /* 751 * Initialise the CPU feature register from Boot CPU values. 752 * Also initiliases the strict_mask for the register. 753 * Any bits that are not covered by an arm64_ftr_bits entry are considered 754 * RES0 for the system-wide value, and must strictly match. 755 */ 756 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 757 { 758 u64 val = 0; 759 u64 strict_mask = ~0x0ULL; 760 u64 user_mask = 0; 761 u64 valid_mask = 0; 762 763 const struct arm64_ftr_bits *ftrp; 764 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 765 766 if (!reg) 767 return; 768 769 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 770 u64 ftr_mask = arm64_ftr_mask(ftrp); 771 s64 ftr_new = arm64_ftr_value(ftrp, new); 772 773 val = arm64_ftr_set_value(ftrp, val, ftr_new); 774 775 valid_mask |= ftr_mask; 776 if (!ftrp->strict) 777 strict_mask &= ~ftr_mask; 778 if (ftrp->visible) 779 user_mask |= ftr_mask; 780 else 781 reg->user_val = arm64_ftr_set_value(ftrp, 782 reg->user_val, 783 ftrp->safe_val); 784 } 785 786 val &= valid_mask; 787 788 reg->sys_val = val; 789 reg->strict_mask = strict_mask; 790 reg->user_mask = user_mask; 791 } 792 793 extern const struct arm64_cpu_capabilities arm64_errata[]; 794 static const struct arm64_cpu_capabilities arm64_features[]; 795 796 static void __init 797 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 798 { 799 for (; caps->matches; caps++) { 800 if (WARN(caps->capability >= ARM64_NCAPS, 801 "Invalid capability %d\n", caps->capability)) 802 continue; 803 if (WARN(cpu_hwcaps_ptrs[caps->capability], 804 "Duplicate entry for capability %d\n", 805 caps->capability)) 806 continue; 807 cpu_hwcaps_ptrs[caps->capability] = caps; 808 } 809 } 810 811 static void __init init_cpu_hwcaps_indirect_list(void) 812 { 813 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 814 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 815 } 816 817 static void __init setup_boot_cpu_capabilities(void); 818 819 void __init init_cpu_features(struct cpuinfo_arm64 *info) 820 { 821 /* Before we start using the tables, make sure it is sorted */ 822 sort_ftr_regs(); 823 824 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 825 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 826 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 827 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 828 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 829 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 830 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 831 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 832 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 833 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 834 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 835 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 836 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 837 838 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 839 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 840 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 841 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 842 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 843 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 844 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 845 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 846 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 847 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 848 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 849 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 850 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 851 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 852 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 853 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 854 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 855 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 856 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 857 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 858 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 859 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 860 } 861 862 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 863 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 864 sve_init_vq_map(); 865 } 866 867 /* 868 * Initialize the indirect array of CPU hwcaps capabilities pointers 869 * before we handle the boot CPU below. 870 */ 871 init_cpu_hwcaps_indirect_list(); 872 873 /* 874 * Detect and enable early CPU capabilities based on the boot CPU, 875 * after we have initialised the CPU feature infrastructure. 876 */ 877 setup_boot_cpu_capabilities(); 878 } 879 880 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 881 { 882 const struct arm64_ftr_bits *ftrp; 883 884 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 885 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 886 s64 ftr_new = arm64_ftr_value(ftrp, new); 887 888 if (ftr_cur == ftr_new) 889 continue; 890 /* Find a safe value */ 891 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 892 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 893 } 894 895 } 896 897 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 898 { 899 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 900 901 if (!regp) 902 return 0; 903 904 update_cpu_ftr_reg(regp, val); 905 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 906 return 0; 907 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 908 regp->name, boot, cpu, val); 909 return 1; 910 } 911 912 static void relax_cpu_ftr_reg(u32 sys_id, int field) 913 { 914 const struct arm64_ftr_bits *ftrp; 915 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 916 917 if (!regp) 918 return; 919 920 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 921 if (ftrp->shift == field) { 922 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 923 break; 924 } 925 } 926 927 /* Bogus field? */ 928 WARN_ON(!ftrp->width); 929 } 930 931 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info, 932 struct cpuinfo_arm64 *boot) 933 { 934 int taint = 0; 935 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 936 937 /* 938 * If we don't have AArch32 at all then skip the checks entirely 939 * as the register values may be UNKNOWN and we're not going to be 940 * using them for anything. 941 */ 942 if (!id_aa64pfr0_32bit_el0(pfr0)) 943 return taint; 944 945 /* 946 * If we don't have AArch32 at EL1, then relax the strictness of 947 * EL1-dependent register fields to avoid spurious sanity check fails. 948 */ 949 if (!id_aa64pfr0_32bit_el1(pfr0)) { 950 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 951 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 952 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 953 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 954 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 955 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 956 } 957 958 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 959 info->reg_id_dfr0, boot->reg_id_dfr0); 960 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 961 info->reg_id_dfr1, boot->reg_id_dfr1); 962 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 963 info->reg_id_isar0, boot->reg_id_isar0); 964 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 965 info->reg_id_isar1, boot->reg_id_isar1); 966 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 967 info->reg_id_isar2, boot->reg_id_isar2); 968 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 969 info->reg_id_isar3, boot->reg_id_isar3); 970 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 971 info->reg_id_isar4, boot->reg_id_isar4); 972 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 973 info->reg_id_isar5, boot->reg_id_isar5); 974 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 975 info->reg_id_isar6, boot->reg_id_isar6); 976 977 /* 978 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 979 * ACTLR formats could differ across CPUs and therefore would have to 980 * be trapped for virtualization anyway. 981 */ 982 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 983 info->reg_id_mmfr0, boot->reg_id_mmfr0); 984 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 985 info->reg_id_mmfr1, boot->reg_id_mmfr1); 986 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 987 info->reg_id_mmfr2, boot->reg_id_mmfr2); 988 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 989 info->reg_id_mmfr3, boot->reg_id_mmfr3); 990 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 991 info->reg_id_mmfr4, boot->reg_id_mmfr4); 992 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 993 info->reg_id_mmfr5, boot->reg_id_mmfr5); 994 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 995 info->reg_id_pfr0, boot->reg_id_pfr0); 996 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 997 info->reg_id_pfr1, boot->reg_id_pfr1); 998 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 999 info->reg_id_pfr2, boot->reg_id_pfr2); 1000 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1001 info->reg_mvfr0, boot->reg_mvfr0); 1002 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1003 info->reg_mvfr1, boot->reg_mvfr1); 1004 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1005 info->reg_mvfr2, boot->reg_mvfr2); 1006 1007 return taint; 1008 } 1009 1010 /* 1011 * Update system wide CPU feature registers with the values from a 1012 * non-boot CPU. Also performs SANITY checks to make sure that there 1013 * aren't any insane variations from that of the boot CPU. 1014 */ 1015 void update_cpu_features(int cpu, 1016 struct cpuinfo_arm64 *info, 1017 struct cpuinfo_arm64 *boot) 1018 { 1019 int taint = 0; 1020 1021 /* 1022 * The kernel can handle differing I-cache policies, but otherwise 1023 * caches should look identical. Userspace JITs will make use of 1024 * *minLine. 1025 */ 1026 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1027 info->reg_ctr, boot->reg_ctr); 1028 1029 /* 1030 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1031 * could result in too much or too little memory being zeroed if a 1032 * process is preempted and migrated between CPUs. 1033 */ 1034 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1035 info->reg_dczid, boot->reg_dczid); 1036 1037 /* If different, timekeeping will be broken (especially with KVM) */ 1038 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1039 info->reg_cntfrq, boot->reg_cntfrq); 1040 1041 /* 1042 * The kernel uses self-hosted debug features and expects CPUs to 1043 * support identical debug features. We presently need CTX_CMPs, WRPs, 1044 * and BRPs to be identical. 1045 * ID_AA64DFR1 is currently RES0. 1046 */ 1047 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1048 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1049 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1050 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1051 /* 1052 * Even in big.LITTLE, processors should be identical instruction-set 1053 * wise. 1054 */ 1055 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1056 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1057 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1058 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1059 1060 /* 1061 * Differing PARange support is fine as long as all peripherals and 1062 * memory are mapped within the minimum PARange of all CPUs. 1063 * Linux should not care about secure memory. 1064 */ 1065 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1066 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1067 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1068 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1069 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1070 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1071 1072 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1073 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1074 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1075 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1076 1077 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1078 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1079 1080 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 1081 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1082 info->reg_zcr, boot->reg_zcr); 1083 1084 /* Probe vector lengths, unless we already gave up on SVE */ 1085 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 1086 !system_capabilities_finalized()) 1087 sve_update_vq_map(); 1088 } 1089 1090 /* 1091 * This relies on a sanitised view of the AArch64 ID registers 1092 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1093 */ 1094 taint |= update_32bit_cpu_features(cpu, info, boot); 1095 1096 /* 1097 * Mismatched CPU features are a recipe for disaster. Don't even 1098 * pretend to support them. 1099 */ 1100 if (taint) { 1101 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1102 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1103 } 1104 } 1105 1106 u64 read_sanitised_ftr_reg(u32 id) 1107 { 1108 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1109 1110 if (!regp) 1111 return 0; 1112 return regp->sys_val; 1113 } 1114 1115 #define read_sysreg_case(r) \ 1116 case r: return read_sysreg_s(r) 1117 1118 /* 1119 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1120 * Read the system register on the current CPU 1121 */ 1122 static u64 __read_sysreg_by_encoding(u32 sys_id) 1123 { 1124 switch (sys_id) { 1125 read_sysreg_case(SYS_ID_PFR0_EL1); 1126 read_sysreg_case(SYS_ID_PFR1_EL1); 1127 read_sysreg_case(SYS_ID_PFR2_EL1); 1128 read_sysreg_case(SYS_ID_DFR0_EL1); 1129 read_sysreg_case(SYS_ID_DFR1_EL1); 1130 read_sysreg_case(SYS_ID_MMFR0_EL1); 1131 read_sysreg_case(SYS_ID_MMFR1_EL1); 1132 read_sysreg_case(SYS_ID_MMFR2_EL1); 1133 read_sysreg_case(SYS_ID_MMFR3_EL1); 1134 read_sysreg_case(SYS_ID_MMFR4_EL1); 1135 read_sysreg_case(SYS_ID_MMFR5_EL1); 1136 read_sysreg_case(SYS_ID_ISAR0_EL1); 1137 read_sysreg_case(SYS_ID_ISAR1_EL1); 1138 read_sysreg_case(SYS_ID_ISAR2_EL1); 1139 read_sysreg_case(SYS_ID_ISAR3_EL1); 1140 read_sysreg_case(SYS_ID_ISAR4_EL1); 1141 read_sysreg_case(SYS_ID_ISAR5_EL1); 1142 read_sysreg_case(SYS_ID_ISAR6_EL1); 1143 read_sysreg_case(SYS_MVFR0_EL1); 1144 read_sysreg_case(SYS_MVFR1_EL1); 1145 read_sysreg_case(SYS_MVFR2_EL1); 1146 1147 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1148 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1149 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1150 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1151 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1152 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1153 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1154 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1155 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1156 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1157 1158 read_sysreg_case(SYS_CNTFRQ_EL0); 1159 read_sysreg_case(SYS_CTR_EL0); 1160 read_sysreg_case(SYS_DCZID_EL0); 1161 1162 default: 1163 BUG(); 1164 return 0; 1165 } 1166 } 1167 1168 #include <linux/irqchip/arm-gic-v3.h> 1169 1170 static bool 1171 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1172 { 1173 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 1174 1175 return val >= entry->min_field_value; 1176 } 1177 1178 static bool 1179 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1180 { 1181 u64 val; 1182 1183 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1184 if (scope == SCOPE_SYSTEM) 1185 val = read_sanitised_ftr_reg(entry->sys_reg); 1186 else 1187 val = __read_sysreg_by_encoding(entry->sys_reg); 1188 1189 return feature_matches(val, entry); 1190 } 1191 1192 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1193 { 1194 bool has_sre; 1195 1196 if (!has_cpuid_feature(entry, scope)) 1197 return false; 1198 1199 has_sre = gic_enable_sre(); 1200 if (!has_sre) 1201 pr_warn_once("%s present but disabled by higher exception level\n", 1202 entry->desc); 1203 1204 return has_sre; 1205 } 1206 1207 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1208 { 1209 u32 midr = read_cpuid_id(); 1210 1211 /* Cavium ThunderX pass 1.x and 2.x */ 1212 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1213 MIDR_CPU_VAR_REV(0, 0), 1214 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1215 } 1216 1217 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1218 { 1219 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1220 1221 return cpuid_feature_extract_signed_field(pfr0, 1222 ID_AA64PFR0_FP_SHIFT) < 0; 1223 } 1224 1225 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1226 int scope) 1227 { 1228 u64 ctr; 1229 1230 if (scope == SCOPE_SYSTEM) 1231 ctr = arm64_ftr_reg_ctrel0.sys_val; 1232 else 1233 ctr = read_cpuid_effective_cachetype(); 1234 1235 return ctr & BIT(CTR_IDC_SHIFT); 1236 } 1237 1238 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1239 { 1240 /* 1241 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1242 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1243 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1244 * value. 1245 */ 1246 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 1247 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1248 } 1249 1250 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1251 int scope) 1252 { 1253 u64 ctr; 1254 1255 if (scope == SCOPE_SYSTEM) 1256 ctr = arm64_ftr_reg_ctrel0.sys_val; 1257 else 1258 ctr = read_cpuid_cachetype(); 1259 1260 return ctr & BIT(CTR_DIC_SHIFT); 1261 } 1262 1263 static bool __maybe_unused 1264 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1265 { 1266 /* 1267 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1268 * may share TLB entries with a CPU stuck in the crashed 1269 * kernel. 1270 */ 1271 if (is_kdump_kernel()) 1272 return false; 1273 1274 return has_cpuid_feature(entry, scope); 1275 } 1276 1277 /* 1278 * This check is triggered during the early boot before the cpufeature 1279 * is initialised. Checking the status on the local CPU allows the boot 1280 * CPU to detect the need for non-global mappings and thus avoiding a 1281 * pagetable re-write after all the CPUs are booted. This check will be 1282 * anyway run on individual CPUs, allowing us to get the consistent 1283 * state once the SMP CPUs are up and thus make the switch to non-global 1284 * mappings if required. 1285 */ 1286 bool kaslr_requires_kpti(void) 1287 { 1288 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1289 return false; 1290 1291 /* 1292 * E0PD does a similar job to KPTI so can be used instead 1293 * where available. 1294 */ 1295 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1296 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1297 if (cpuid_feature_extract_unsigned_field(mmfr2, 1298 ID_AA64MMFR2_E0PD_SHIFT)) 1299 return false; 1300 } 1301 1302 /* 1303 * Systems affected by Cavium erratum 24756 are incompatible 1304 * with KPTI. 1305 */ 1306 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1307 extern const struct midr_range cavium_erratum_27456_cpus[]; 1308 1309 if (is_midr_in_range_list(read_cpuid_id(), 1310 cavium_erratum_27456_cpus)) 1311 return false; 1312 } 1313 1314 return kaslr_offset() > 0; 1315 } 1316 1317 static bool __meltdown_safe = true; 1318 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1319 1320 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1321 int scope) 1322 { 1323 /* List of CPUs that are not vulnerable and don't need KPTI */ 1324 static const struct midr_range kpti_safe_list[] = { 1325 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1326 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1327 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1328 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1329 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1330 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1331 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1332 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1333 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1334 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1335 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1336 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1337 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1338 { /* sentinel */ } 1339 }; 1340 char const *str = "kpti command line option"; 1341 bool meltdown_safe; 1342 1343 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1344 1345 /* Defer to CPU feature registers */ 1346 if (has_cpuid_feature(entry, scope)) 1347 meltdown_safe = true; 1348 1349 if (!meltdown_safe) 1350 __meltdown_safe = false; 1351 1352 /* 1353 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1354 * ThunderX leads to apparent I-cache corruption of kernel text, which 1355 * ends as well as you might imagine. Don't even try. 1356 */ 1357 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1358 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1359 __kpti_forced = -1; 1360 } 1361 1362 /* Useful for KASLR robustness */ 1363 if (kaslr_requires_kpti()) { 1364 if (!__kpti_forced) { 1365 str = "KASLR"; 1366 __kpti_forced = 1; 1367 } 1368 } 1369 1370 if (cpu_mitigations_off() && !__kpti_forced) { 1371 str = "mitigations=off"; 1372 __kpti_forced = -1; 1373 } 1374 1375 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1376 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1377 return false; 1378 } 1379 1380 /* Forced? */ 1381 if (__kpti_forced) { 1382 pr_info_once("kernel page table isolation forced %s by %s\n", 1383 __kpti_forced > 0 ? "ON" : "OFF", str); 1384 return __kpti_forced > 0; 1385 } 1386 1387 return !meltdown_safe; 1388 } 1389 1390 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1391 static void 1392 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1393 { 1394 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1395 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1396 kpti_remap_fn *remap_fn; 1397 1398 int cpu = smp_processor_id(); 1399 1400 /* 1401 * We don't need to rewrite the page-tables if either we've done 1402 * it already or we have KASLR enabled and therefore have not 1403 * created any global mappings at all. 1404 */ 1405 if (arm64_use_ng_mappings) 1406 return; 1407 1408 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1409 1410 cpu_install_idmap(); 1411 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1412 cpu_uninstall_idmap(); 1413 1414 if (!cpu) 1415 arm64_use_ng_mappings = true; 1416 1417 return; 1418 } 1419 #else 1420 static void 1421 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1422 { 1423 } 1424 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1425 1426 static int __init parse_kpti(char *str) 1427 { 1428 bool enabled; 1429 int ret = strtobool(str, &enabled); 1430 1431 if (ret) 1432 return ret; 1433 1434 __kpti_forced = enabled ? 1 : -1; 1435 return 0; 1436 } 1437 early_param("kpti", parse_kpti); 1438 1439 #ifdef CONFIG_ARM64_HW_AFDBM 1440 static inline void __cpu_enable_hw_dbm(void) 1441 { 1442 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1443 1444 write_sysreg(tcr, tcr_el1); 1445 isb(); 1446 } 1447 1448 static bool cpu_has_broken_dbm(void) 1449 { 1450 /* List of CPUs which have broken DBM support. */ 1451 static const struct midr_range cpus[] = { 1452 #ifdef CONFIG_ARM64_ERRATUM_1024718 1453 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 1454 /* Kryo4xx Silver (rdpe => r1p0) */ 1455 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1456 #endif 1457 {}, 1458 }; 1459 1460 return is_midr_in_range_list(read_cpuid_id(), cpus); 1461 } 1462 1463 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1464 { 1465 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1466 !cpu_has_broken_dbm(); 1467 } 1468 1469 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1470 { 1471 if (cpu_can_use_dbm(cap)) 1472 __cpu_enable_hw_dbm(); 1473 } 1474 1475 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1476 int __unused) 1477 { 1478 static bool detected = false; 1479 /* 1480 * DBM is a non-conflicting feature. i.e, the kernel can safely 1481 * run a mix of CPUs with and without the feature. So, we 1482 * unconditionally enable the capability to allow any late CPU 1483 * to use the feature. We only enable the control bits on the 1484 * CPU, if it actually supports. 1485 * 1486 * We have to make sure we print the "feature" detection only 1487 * when at least one CPU actually uses it. So check if this CPU 1488 * can actually use it and print the message exactly once. 1489 * 1490 * This is safe as all CPUs (including secondary CPUs - due to the 1491 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1492 * goes through the "matches" check exactly once. Also if a CPU 1493 * matches the criteria, it is guaranteed that the CPU will turn 1494 * the DBM on, as the capability is unconditionally enabled. 1495 */ 1496 if (!detected && cpu_can_use_dbm(cap)) { 1497 detected = true; 1498 pr_info("detected: Hardware dirty bit management\n"); 1499 } 1500 1501 return true; 1502 } 1503 1504 #endif 1505 1506 #ifdef CONFIG_ARM64_AMU_EXTN 1507 1508 /* 1509 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1510 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1511 * information regarding all the events that it supports. When a CPU bit is 1512 * set in the cpumask, the user of this feature can only rely on the presence 1513 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1514 * counters are enabled or access to these counters is enabled by code 1515 * executed at higher exception levels (firmware). 1516 */ 1517 static struct cpumask amu_cpus __read_mostly; 1518 1519 bool cpu_has_amu_feat(int cpu) 1520 { 1521 return cpumask_test_cpu(cpu, &amu_cpus); 1522 } 1523 1524 /* Initialize the use of AMU counters for frequency invariance */ 1525 extern void init_cpu_freq_invariance_counters(void); 1526 1527 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1528 { 1529 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1530 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1531 smp_processor_id()); 1532 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1533 init_cpu_freq_invariance_counters(); 1534 } 1535 } 1536 1537 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1538 int __unused) 1539 { 1540 /* 1541 * The AMU extension is a non-conflicting feature: the kernel can 1542 * safely run a mix of CPUs with and without support for the 1543 * activity monitors extension. Therefore, unconditionally enable 1544 * the capability to allow any late CPU to use the feature. 1545 * 1546 * With this feature unconditionally enabled, the cpu_enable 1547 * function will be called for all CPUs that match the criteria, 1548 * including secondary and hotplugged, marking this feature as 1549 * present on that respective CPU. The enable function will also 1550 * print a detection message. 1551 */ 1552 1553 return true; 1554 } 1555 #endif 1556 1557 #ifdef CONFIG_ARM64_VHE 1558 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1559 { 1560 return is_kernel_in_hyp_mode(); 1561 } 1562 1563 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1564 { 1565 /* 1566 * Copy register values that aren't redirected by hardware. 1567 * 1568 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1569 * this value to tpidr_el2 before we patch the code. Once we've done 1570 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1571 * do anything here. 1572 */ 1573 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1574 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1575 } 1576 #endif 1577 1578 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1579 { 1580 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1581 1582 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1583 WARN_ON(val & (7 << 27 | 7 << 21)); 1584 } 1585 1586 #ifdef CONFIG_ARM64_SSBD 1587 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr) 1588 { 1589 if (user_mode(regs)) 1590 return 1; 1591 1592 if (instr & BIT(PSTATE_Imm_shift)) 1593 regs->pstate |= PSR_SSBS_BIT; 1594 else 1595 regs->pstate &= ~PSR_SSBS_BIT; 1596 1597 arm64_skip_faulting_instruction(regs, 4); 1598 return 0; 1599 } 1600 1601 static struct undef_hook ssbs_emulation_hook = { 1602 .instr_mask = ~(1U << PSTATE_Imm_shift), 1603 .instr_val = 0xd500401f | PSTATE_SSBS, 1604 .fn = ssbs_emulation_handler, 1605 }; 1606 1607 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused) 1608 { 1609 static bool undef_hook_registered = false; 1610 static DEFINE_RAW_SPINLOCK(hook_lock); 1611 1612 raw_spin_lock(&hook_lock); 1613 if (!undef_hook_registered) { 1614 register_undef_hook(&ssbs_emulation_hook); 1615 undef_hook_registered = true; 1616 } 1617 raw_spin_unlock(&hook_lock); 1618 1619 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) { 1620 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS); 1621 arm64_set_ssbd_mitigation(false); 1622 } else { 1623 arm64_set_ssbd_mitigation(true); 1624 } 1625 } 1626 #endif /* CONFIG_ARM64_SSBD */ 1627 1628 #ifdef CONFIG_ARM64_PAN 1629 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1630 { 1631 /* 1632 * We modify PSTATE. This won't work from irq context as the PSTATE 1633 * is discarded once we return from the exception. 1634 */ 1635 WARN_ON_ONCE(in_interrupt()); 1636 1637 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1638 asm(SET_PSTATE_PAN(1)); 1639 } 1640 #endif /* CONFIG_ARM64_PAN */ 1641 1642 #ifdef CONFIG_ARM64_RAS_EXTN 1643 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1644 { 1645 /* Firmware may have left a deferred SError in this register. */ 1646 write_sysreg_s(0, SYS_DISR_EL1); 1647 } 1648 #endif /* CONFIG_ARM64_RAS_EXTN */ 1649 1650 #ifdef CONFIG_ARM64_PTR_AUTH 1651 static bool has_address_auth(const struct arm64_cpu_capabilities *entry, 1652 int __unused) 1653 { 1654 return __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_ARCH) || 1655 __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_IMP_DEF); 1656 } 1657 1658 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1659 int __unused) 1660 { 1661 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) || 1662 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1663 } 1664 #endif /* CONFIG_ARM64_PTR_AUTH */ 1665 1666 #ifdef CONFIG_ARM64_E0PD 1667 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1668 { 1669 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1670 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1671 } 1672 #endif /* CONFIG_ARM64_E0PD */ 1673 1674 #ifdef CONFIG_ARM64_PSEUDO_NMI 1675 static bool enable_pseudo_nmi; 1676 1677 static int __init early_enable_pseudo_nmi(char *p) 1678 { 1679 return strtobool(p, &enable_pseudo_nmi); 1680 } 1681 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1682 1683 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1684 int scope) 1685 { 1686 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1687 } 1688 #endif 1689 1690 #ifdef CONFIG_ARM64_BTI 1691 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 1692 { 1693 /* 1694 * Use of X16/X17 for tail-calls and trampolines that jump to 1695 * function entry points using BR is a requirement for 1696 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 1697 * So, be strict and forbid other BRs using other registers to 1698 * jump onto a PACIxSP instruction: 1699 */ 1700 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 1701 isb(); 1702 } 1703 #endif /* CONFIG_ARM64_BTI */ 1704 1705 /* Internal helper functions to match cpu capability type */ 1706 static bool 1707 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1708 { 1709 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1710 } 1711 1712 static bool 1713 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1714 { 1715 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1716 } 1717 1718 static bool 1719 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 1720 { 1721 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 1722 } 1723 1724 static const struct arm64_cpu_capabilities arm64_features[] = { 1725 { 1726 .desc = "GIC system register CPU interface", 1727 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1728 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1729 .matches = has_useable_gicv3_cpuif, 1730 .sys_reg = SYS_ID_AA64PFR0_EL1, 1731 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1732 .sign = FTR_UNSIGNED, 1733 .min_field_value = 1, 1734 }, 1735 #ifdef CONFIG_ARM64_PAN 1736 { 1737 .desc = "Privileged Access Never", 1738 .capability = ARM64_HAS_PAN, 1739 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1740 .matches = has_cpuid_feature, 1741 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1742 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1743 .sign = FTR_UNSIGNED, 1744 .min_field_value = 1, 1745 .cpu_enable = cpu_enable_pan, 1746 }, 1747 #endif /* CONFIG_ARM64_PAN */ 1748 #ifdef CONFIG_ARM64_LSE_ATOMICS 1749 { 1750 .desc = "LSE atomic instructions", 1751 .capability = ARM64_HAS_LSE_ATOMICS, 1752 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1753 .matches = has_cpuid_feature, 1754 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1755 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1756 .sign = FTR_UNSIGNED, 1757 .min_field_value = 2, 1758 }, 1759 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 1760 { 1761 .desc = "Software prefetching using PRFM", 1762 .capability = ARM64_HAS_NO_HW_PREFETCH, 1763 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1764 .matches = has_no_hw_prefetch, 1765 }, 1766 #ifdef CONFIG_ARM64_UAO 1767 { 1768 .desc = "User Access Override", 1769 .capability = ARM64_HAS_UAO, 1770 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1771 .matches = has_cpuid_feature, 1772 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1773 .field_pos = ID_AA64MMFR2_UAO_SHIFT, 1774 .min_field_value = 1, 1775 /* 1776 * We rely on stop_machine() calling uao_thread_switch() to set 1777 * UAO immediately after patching. 1778 */ 1779 }, 1780 #endif /* CONFIG_ARM64_UAO */ 1781 #ifdef CONFIG_ARM64_PAN 1782 { 1783 .capability = ARM64_ALT_PAN_NOT_UAO, 1784 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1785 .matches = cpufeature_pan_not_uao, 1786 }, 1787 #endif /* CONFIG_ARM64_PAN */ 1788 #ifdef CONFIG_ARM64_VHE 1789 { 1790 .desc = "Virtualization Host Extensions", 1791 .capability = ARM64_HAS_VIRT_HOST_EXTN, 1792 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1793 .matches = runs_at_el2, 1794 .cpu_enable = cpu_copy_el2regs, 1795 }, 1796 #endif /* CONFIG_ARM64_VHE */ 1797 { 1798 .desc = "32-bit EL0 Support", 1799 .capability = ARM64_HAS_32BIT_EL0, 1800 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1801 .matches = has_cpuid_feature, 1802 .sys_reg = SYS_ID_AA64PFR0_EL1, 1803 .sign = FTR_UNSIGNED, 1804 .field_pos = ID_AA64PFR0_EL0_SHIFT, 1805 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 1806 }, 1807 #ifdef CONFIG_KVM 1808 { 1809 .desc = "32-bit EL1 Support", 1810 .capability = ARM64_HAS_32BIT_EL1, 1811 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1812 .matches = has_cpuid_feature, 1813 .sys_reg = SYS_ID_AA64PFR0_EL1, 1814 .sign = FTR_UNSIGNED, 1815 .field_pos = ID_AA64PFR0_EL1_SHIFT, 1816 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT, 1817 }, 1818 #endif 1819 { 1820 .desc = "Kernel page table isolation (KPTI)", 1821 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 1822 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1823 /* 1824 * The ID feature fields below are used to indicate that 1825 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 1826 * more details. 1827 */ 1828 .sys_reg = SYS_ID_AA64PFR0_EL1, 1829 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 1830 .min_field_value = 1, 1831 .matches = unmap_kernel_at_el0, 1832 .cpu_enable = kpti_install_ng_mappings, 1833 }, 1834 { 1835 /* FP/SIMD is not implemented */ 1836 .capability = ARM64_HAS_NO_FPSIMD, 1837 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1838 .min_field_value = 0, 1839 .matches = has_no_fpsimd, 1840 }, 1841 #ifdef CONFIG_ARM64_PMEM 1842 { 1843 .desc = "Data cache clean to Point of Persistence", 1844 .capability = ARM64_HAS_DCPOP, 1845 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1846 .matches = has_cpuid_feature, 1847 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1848 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1849 .min_field_value = 1, 1850 }, 1851 { 1852 .desc = "Data cache clean to Point of Deep Persistence", 1853 .capability = ARM64_HAS_DCPODP, 1854 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1855 .matches = has_cpuid_feature, 1856 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1857 .sign = FTR_UNSIGNED, 1858 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1859 .min_field_value = 2, 1860 }, 1861 #endif 1862 #ifdef CONFIG_ARM64_SVE 1863 { 1864 .desc = "Scalable Vector Extension", 1865 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1866 .capability = ARM64_SVE, 1867 .sys_reg = SYS_ID_AA64PFR0_EL1, 1868 .sign = FTR_UNSIGNED, 1869 .field_pos = ID_AA64PFR0_SVE_SHIFT, 1870 .min_field_value = ID_AA64PFR0_SVE, 1871 .matches = has_cpuid_feature, 1872 .cpu_enable = sve_kernel_enable, 1873 }, 1874 #endif /* CONFIG_ARM64_SVE */ 1875 #ifdef CONFIG_ARM64_RAS_EXTN 1876 { 1877 .desc = "RAS Extension Support", 1878 .capability = ARM64_HAS_RAS_EXTN, 1879 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1880 .matches = has_cpuid_feature, 1881 .sys_reg = SYS_ID_AA64PFR0_EL1, 1882 .sign = FTR_UNSIGNED, 1883 .field_pos = ID_AA64PFR0_RAS_SHIFT, 1884 .min_field_value = ID_AA64PFR0_RAS_V1, 1885 .cpu_enable = cpu_clear_disr, 1886 }, 1887 #endif /* CONFIG_ARM64_RAS_EXTN */ 1888 #ifdef CONFIG_ARM64_AMU_EXTN 1889 { 1890 /* 1891 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 1892 * Therefore, don't provide .desc as we don't want the detection 1893 * message to be shown until at least one CPU is detected to 1894 * support the feature. 1895 */ 1896 .capability = ARM64_HAS_AMU_EXTN, 1897 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1898 .matches = has_amu, 1899 .sys_reg = SYS_ID_AA64PFR0_EL1, 1900 .sign = FTR_UNSIGNED, 1901 .field_pos = ID_AA64PFR0_AMU_SHIFT, 1902 .min_field_value = ID_AA64PFR0_AMU, 1903 .cpu_enable = cpu_amu_enable, 1904 }, 1905 #endif /* CONFIG_ARM64_AMU_EXTN */ 1906 { 1907 .desc = "Data cache clean to the PoU not required for I/D coherence", 1908 .capability = ARM64_HAS_CACHE_IDC, 1909 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1910 .matches = has_cache_idc, 1911 .cpu_enable = cpu_emulate_effective_ctr, 1912 }, 1913 { 1914 .desc = "Instruction cache invalidation not required for I/D coherence", 1915 .capability = ARM64_HAS_CACHE_DIC, 1916 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1917 .matches = has_cache_dic, 1918 }, 1919 { 1920 .desc = "Stage-2 Force Write-Back", 1921 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1922 .capability = ARM64_HAS_STAGE2_FWB, 1923 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1924 .sign = FTR_UNSIGNED, 1925 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 1926 .min_field_value = 1, 1927 .matches = has_cpuid_feature, 1928 .cpu_enable = cpu_has_fwb, 1929 }, 1930 { 1931 .desc = "ARMv8.4 Translation Table Level", 1932 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1933 .capability = ARM64_HAS_ARMv8_4_TTL, 1934 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1935 .sign = FTR_UNSIGNED, 1936 .field_pos = ID_AA64MMFR2_TTL_SHIFT, 1937 .min_field_value = 1, 1938 .matches = has_cpuid_feature, 1939 }, 1940 { 1941 .desc = "TLB range maintenance instructions", 1942 .capability = ARM64_HAS_TLB_RANGE, 1943 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1944 .matches = has_cpuid_feature, 1945 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1946 .field_pos = ID_AA64ISAR0_TLB_SHIFT, 1947 .sign = FTR_UNSIGNED, 1948 .min_field_value = ID_AA64ISAR0_TLB_RANGE, 1949 }, 1950 #ifdef CONFIG_ARM64_HW_AFDBM 1951 { 1952 /* 1953 * Since we turn this on always, we don't want the user to 1954 * think that the feature is available when it may not be. 1955 * So hide the description. 1956 * 1957 * .desc = "Hardware pagetable Dirty Bit Management", 1958 * 1959 */ 1960 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1961 .capability = ARM64_HW_DBM, 1962 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1963 .sign = FTR_UNSIGNED, 1964 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 1965 .min_field_value = 2, 1966 .matches = has_hw_dbm, 1967 .cpu_enable = cpu_enable_hw_dbm, 1968 }, 1969 #endif 1970 { 1971 .desc = "CRC32 instructions", 1972 .capability = ARM64_HAS_CRC32, 1973 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1974 .matches = has_cpuid_feature, 1975 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1976 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 1977 .min_field_value = 1, 1978 }, 1979 #ifdef CONFIG_ARM64_SSBD 1980 { 1981 .desc = "Speculative Store Bypassing Safe (SSBS)", 1982 .capability = ARM64_SSBS, 1983 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1984 .matches = has_cpuid_feature, 1985 .sys_reg = SYS_ID_AA64PFR1_EL1, 1986 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 1987 .sign = FTR_UNSIGNED, 1988 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 1989 .cpu_enable = cpu_enable_ssbs, 1990 }, 1991 #endif 1992 #ifdef CONFIG_ARM64_CNP 1993 { 1994 .desc = "Common not Private translations", 1995 .capability = ARM64_HAS_CNP, 1996 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1997 .matches = has_useable_cnp, 1998 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1999 .sign = FTR_UNSIGNED, 2000 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 2001 .min_field_value = 1, 2002 .cpu_enable = cpu_enable_cnp, 2003 }, 2004 #endif 2005 { 2006 .desc = "Speculation barrier (SB)", 2007 .capability = ARM64_HAS_SB, 2008 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2009 .matches = has_cpuid_feature, 2010 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2011 .field_pos = ID_AA64ISAR1_SB_SHIFT, 2012 .sign = FTR_UNSIGNED, 2013 .min_field_value = 1, 2014 }, 2015 #ifdef CONFIG_ARM64_PTR_AUTH 2016 { 2017 .desc = "Address authentication (architected algorithm)", 2018 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 2019 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2020 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2021 .sign = FTR_UNSIGNED, 2022 .field_pos = ID_AA64ISAR1_APA_SHIFT, 2023 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 2024 .matches = has_cpuid_feature, 2025 }, 2026 { 2027 .desc = "Address authentication (IMP DEF algorithm)", 2028 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2029 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2030 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2031 .sign = FTR_UNSIGNED, 2032 .field_pos = ID_AA64ISAR1_API_SHIFT, 2033 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 2034 .matches = has_cpuid_feature, 2035 }, 2036 { 2037 .capability = ARM64_HAS_ADDRESS_AUTH, 2038 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2039 .matches = has_address_auth, 2040 }, 2041 { 2042 .desc = "Generic authentication (architected algorithm)", 2043 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 2044 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2045 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2046 .sign = FTR_UNSIGNED, 2047 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 2048 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 2049 .matches = has_cpuid_feature, 2050 }, 2051 { 2052 .desc = "Generic authentication (IMP DEF algorithm)", 2053 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2054 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2055 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2056 .sign = FTR_UNSIGNED, 2057 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 2058 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 2059 .matches = has_cpuid_feature, 2060 }, 2061 { 2062 .capability = ARM64_HAS_GENERIC_AUTH, 2063 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2064 .matches = has_generic_auth, 2065 }, 2066 #endif /* CONFIG_ARM64_PTR_AUTH */ 2067 #ifdef CONFIG_ARM64_PSEUDO_NMI 2068 { 2069 /* 2070 * Depends on having GICv3 2071 */ 2072 .desc = "IRQ priority masking", 2073 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2074 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2075 .matches = can_use_gic_priorities, 2076 .sys_reg = SYS_ID_AA64PFR0_EL1, 2077 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2078 .sign = FTR_UNSIGNED, 2079 .min_field_value = 1, 2080 }, 2081 #endif 2082 #ifdef CONFIG_ARM64_E0PD 2083 { 2084 .desc = "E0PD", 2085 .capability = ARM64_HAS_E0PD, 2086 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2087 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2088 .sign = FTR_UNSIGNED, 2089 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2090 .matches = has_cpuid_feature, 2091 .min_field_value = 1, 2092 .cpu_enable = cpu_enable_e0pd, 2093 }, 2094 #endif 2095 #ifdef CONFIG_ARCH_RANDOM 2096 { 2097 .desc = "Random Number Generator", 2098 .capability = ARM64_HAS_RNG, 2099 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2100 .matches = has_cpuid_feature, 2101 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2102 .field_pos = ID_AA64ISAR0_RNDR_SHIFT, 2103 .sign = FTR_UNSIGNED, 2104 .min_field_value = 1, 2105 }, 2106 #endif 2107 #ifdef CONFIG_ARM64_BTI 2108 { 2109 .desc = "Branch Target Identification", 2110 .capability = ARM64_BTI, 2111 #ifdef CONFIG_ARM64_BTI_KERNEL 2112 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2113 #else 2114 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2115 #endif 2116 .matches = has_cpuid_feature, 2117 .cpu_enable = bti_enable, 2118 .sys_reg = SYS_ID_AA64PFR1_EL1, 2119 .field_pos = ID_AA64PFR1_BT_SHIFT, 2120 .min_field_value = ID_AA64PFR1_BT_BTI, 2121 .sign = FTR_UNSIGNED, 2122 }, 2123 #endif 2124 {}, 2125 }; 2126 2127 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2128 .matches = has_cpuid_feature, \ 2129 .sys_reg = reg, \ 2130 .field_pos = field, \ 2131 .sign = s, \ 2132 .min_field_value = min_value, 2133 2134 #define __HWCAP_CAP(name, cap_type, cap) \ 2135 .desc = name, \ 2136 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2137 .hwcap_type = cap_type, \ 2138 .hwcap = cap, \ 2139 2140 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 2141 { \ 2142 __HWCAP_CAP(#cap, cap_type, cap) \ 2143 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2144 } 2145 2146 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2147 { \ 2148 __HWCAP_CAP(#cap, cap_type, cap) \ 2149 .matches = cpucap_multi_entry_cap_matches, \ 2150 .match_list = list, \ 2151 } 2152 2153 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2154 { \ 2155 __HWCAP_CAP(#cap, cap_type, cap) \ 2156 .matches = match, \ 2157 } 2158 2159 #ifdef CONFIG_ARM64_PTR_AUTH 2160 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2161 { 2162 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 2163 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 2164 }, 2165 { 2166 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 2167 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 2168 }, 2169 {}, 2170 }; 2171 2172 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2173 { 2174 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 2175 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 2176 }, 2177 { 2178 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 2179 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 2180 }, 2181 {}, 2182 }; 2183 #endif 2184 2185 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2186 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2187 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2188 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2189 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2190 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2191 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2192 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2193 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2194 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2195 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2196 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2197 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2198 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2199 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2200 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2201 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2202 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2203 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2204 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2205 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2206 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2207 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2208 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2209 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2210 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2211 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2212 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2213 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2214 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2215 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2216 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2217 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2218 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2219 #ifdef CONFIG_ARM64_SVE 2220 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2221 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2222 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2223 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2224 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2225 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2226 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2227 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2228 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2229 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2230 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2231 #endif 2232 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2233 #ifdef CONFIG_ARM64_BTI 2234 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2235 #endif 2236 #ifdef CONFIG_ARM64_PTR_AUTH 2237 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2238 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2239 #endif 2240 {}, 2241 }; 2242 2243 #ifdef CONFIG_COMPAT 2244 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2245 { 2246 /* 2247 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2248 * in line with that of arm32 as in vfp_init(). We make sure that the 2249 * check is future proof, by making sure value is non-zero. 2250 */ 2251 u32 mvfr1; 2252 2253 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2254 if (scope == SCOPE_SYSTEM) 2255 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2256 else 2257 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2258 2259 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2260 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2261 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2262 } 2263 #endif 2264 2265 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2266 #ifdef CONFIG_COMPAT 2267 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2268 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2269 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2270 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2271 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2272 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2273 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2274 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2275 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2276 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2277 #endif 2278 {}, 2279 }; 2280 2281 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2282 { 2283 switch (cap->hwcap_type) { 2284 case CAP_HWCAP: 2285 cpu_set_feature(cap->hwcap); 2286 break; 2287 #ifdef CONFIG_COMPAT 2288 case CAP_COMPAT_HWCAP: 2289 compat_elf_hwcap |= (u32)cap->hwcap; 2290 break; 2291 case CAP_COMPAT_HWCAP2: 2292 compat_elf_hwcap2 |= (u32)cap->hwcap; 2293 break; 2294 #endif 2295 default: 2296 WARN_ON(1); 2297 break; 2298 } 2299 } 2300 2301 /* Check if we have a particular HWCAP enabled */ 2302 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2303 { 2304 bool rc; 2305 2306 switch (cap->hwcap_type) { 2307 case CAP_HWCAP: 2308 rc = cpu_have_feature(cap->hwcap); 2309 break; 2310 #ifdef CONFIG_COMPAT 2311 case CAP_COMPAT_HWCAP: 2312 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2313 break; 2314 case CAP_COMPAT_HWCAP2: 2315 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2316 break; 2317 #endif 2318 default: 2319 WARN_ON(1); 2320 rc = false; 2321 } 2322 2323 return rc; 2324 } 2325 2326 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2327 { 2328 /* We support emulation of accesses to CPU ID feature registers */ 2329 cpu_set_named_feature(CPUID); 2330 for (; hwcaps->matches; hwcaps++) 2331 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2332 cap_set_elf_hwcap(hwcaps); 2333 } 2334 2335 static void update_cpu_capabilities(u16 scope_mask) 2336 { 2337 int i; 2338 const struct arm64_cpu_capabilities *caps; 2339 2340 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2341 for (i = 0; i < ARM64_NCAPS; i++) { 2342 caps = cpu_hwcaps_ptrs[i]; 2343 if (!caps || !(caps->type & scope_mask) || 2344 cpus_have_cap(caps->capability) || 2345 !caps->matches(caps, cpucap_default_scope(caps))) 2346 continue; 2347 2348 if (caps->desc) 2349 pr_info("detected: %s\n", caps->desc); 2350 cpus_set_cap(caps->capability); 2351 2352 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2353 set_bit(caps->capability, boot_capabilities); 2354 } 2355 } 2356 2357 /* 2358 * Enable all the available capabilities on this CPU. The capabilities 2359 * with BOOT_CPU scope are handled separately and hence skipped here. 2360 */ 2361 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2362 { 2363 int i; 2364 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2365 2366 for_each_available_cap(i) { 2367 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2368 2369 if (WARN_ON(!cap)) 2370 continue; 2371 2372 if (!(cap->type & non_boot_scope)) 2373 continue; 2374 2375 if (cap->cpu_enable) 2376 cap->cpu_enable(cap); 2377 } 2378 return 0; 2379 } 2380 2381 /* 2382 * Run through the enabled capabilities and enable() it on all active 2383 * CPUs 2384 */ 2385 static void __init enable_cpu_capabilities(u16 scope_mask) 2386 { 2387 int i; 2388 const struct arm64_cpu_capabilities *caps; 2389 bool boot_scope; 2390 2391 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2392 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2393 2394 for (i = 0; i < ARM64_NCAPS; i++) { 2395 unsigned int num; 2396 2397 caps = cpu_hwcaps_ptrs[i]; 2398 if (!caps || !(caps->type & scope_mask)) 2399 continue; 2400 num = caps->capability; 2401 if (!cpus_have_cap(num)) 2402 continue; 2403 2404 /* Ensure cpus_have_const_cap(num) works */ 2405 static_branch_enable(&cpu_hwcap_keys[num]); 2406 2407 if (boot_scope && caps->cpu_enable) 2408 /* 2409 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2410 * before any secondary CPU boots. Thus, each secondary 2411 * will enable the capability as appropriate via 2412 * check_local_cpu_capabilities(). The only exception is 2413 * the boot CPU, for which the capability must be 2414 * enabled here. This approach avoids costly 2415 * stop_machine() calls for this case. 2416 */ 2417 caps->cpu_enable(caps); 2418 } 2419 2420 /* 2421 * For all non-boot scope capabilities, use stop_machine() 2422 * as it schedules the work allowing us to modify PSTATE, 2423 * instead of on_each_cpu() which uses an IPI, giving us a 2424 * PSTATE that disappears when we return. 2425 */ 2426 if (!boot_scope) 2427 stop_machine(cpu_enable_non_boot_scope_capabilities, 2428 NULL, cpu_online_mask); 2429 } 2430 2431 /* 2432 * Run through the list of capabilities to check for conflicts. 2433 * If the system has already detected a capability, take necessary 2434 * action on this CPU. 2435 */ 2436 static void verify_local_cpu_caps(u16 scope_mask) 2437 { 2438 int i; 2439 bool cpu_has_cap, system_has_cap; 2440 const struct arm64_cpu_capabilities *caps; 2441 2442 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2443 2444 for (i = 0; i < ARM64_NCAPS; i++) { 2445 caps = cpu_hwcaps_ptrs[i]; 2446 if (!caps || !(caps->type & scope_mask)) 2447 continue; 2448 2449 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2450 system_has_cap = cpus_have_cap(caps->capability); 2451 2452 if (system_has_cap) { 2453 /* 2454 * Check if the new CPU misses an advertised feature, 2455 * which is not safe to miss. 2456 */ 2457 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2458 break; 2459 /* 2460 * We have to issue cpu_enable() irrespective of 2461 * whether the CPU has it or not, as it is enabeld 2462 * system wide. It is upto the call back to take 2463 * appropriate action on this CPU. 2464 */ 2465 if (caps->cpu_enable) 2466 caps->cpu_enable(caps); 2467 } else { 2468 /* 2469 * Check if the CPU has this capability if it isn't 2470 * safe to have when the system doesn't. 2471 */ 2472 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2473 break; 2474 } 2475 } 2476 2477 if (i < ARM64_NCAPS) { 2478 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2479 smp_processor_id(), caps->capability, 2480 caps->desc, system_has_cap, cpu_has_cap); 2481 2482 if (cpucap_panic_on_conflict(caps)) 2483 cpu_panic_kernel(); 2484 else 2485 cpu_die_early(); 2486 } 2487 } 2488 2489 /* 2490 * Check for CPU features that are used in early boot 2491 * based on the Boot CPU value. 2492 */ 2493 static void check_early_cpu_features(void) 2494 { 2495 verify_cpu_asid_bits(); 2496 2497 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2498 } 2499 2500 static void 2501 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2502 { 2503 2504 for (; caps->matches; caps++) 2505 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2506 pr_crit("CPU%d: missing HWCAP: %s\n", 2507 smp_processor_id(), caps->desc); 2508 cpu_die_early(); 2509 } 2510 } 2511 2512 static void verify_sve_features(void) 2513 { 2514 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2515 u64 zcr = read_zcr_features(); 2516 2517 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2518 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2519 2520 if (len < safe_len || sve_verify_vq_map()) { 2521 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2522 smp_processor_id()); 2523 cpu_die_early(); 2524 } 2525 2526 /* Add checks on other ZCR bits here if necessary */ 2527 } 2528 2529 static void verify_hyp_capabilities(void) 2530 { 2531 u64 safe_mmfr1, mmfr0, mmfr1; 2532 int parange, ipa_max; 2533 unsigned int safe_vmid_bits, vmid_bits; 2534 2535 if (!IS_ENABLED(CONFIG_KVM) || !IS_ENABLED(CONFIG_KVM_ARM_HOST)) 2536 return; 2537 2538 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 2539 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 2540 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 2541 2542 /* Verify VMID bits */ 2543 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 2544 vmid_bits = get_vmid_bits(mmfr1); 2545 if (vmid_bits < safe_vmid_bits) { 2546 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 2547 cpu_die_early(); 2548 } 2549 2550 /* Verify IPA range */ 2551 parange = cpuid_feature_extract_unsigned_field(mmfr0, 2552 ID_AA64MMFR0_PARANGE_SHIFT); 2553 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 2554 if (ipa_max < get_kvm_ipa_limit()) { 2555 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 2556 cpu_die_early(); 2557 } 2558 } 2559 2560 /* 2561 * Run through the enabled system capabilities and enable() it on this CPU. 2562 * The capabilities were decided based on the available CPUs at the boot time. 2563 * Any new CPU should match the system wide status of the capability. If the 2564 * new CPU doesn't have a capability which the system now has enabled, we 2565 * cannot do anything to fix it up and could cause unexpected failures. So 2566 * we park the CPU. 2567 */ 2568 static void verify_local_cpu_capabilities(void) 2569 { 2570 /* 2571 * The capabilities with SCOPE_BOOT_CPU are checked from 2572 * check_early_cpu_features(), as they need to be verified 2573 * on all secondary CPUs. 2574 */ 2575 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2576 2577 verify_local_elf_hwcaps(arm64_elf_hwcaps); 2578 2579 if (system_supports_32bit_el0()) 2580 verify_local_elf_hwcaps(compat_elf_hwcaps); 2581 2582 if (system_supports_sve()) 2583 verify_sve_features(); 2584 2585 if (is_hyp_mode_available()) 2586 verify_hyp_capabilities(); 2587 } 2588 2589 void check_local_cpu_capabilities(void) 2590 { 2591 /* 2592 * All secondary CPUs should conform to the early CPU features 2593 * in use by the kernel based on boot CPU. 2594 */ 2595 check_early_cpu_features(); 2596 2597 /* 2598 * If we haven't finalised the system capabilities, this CPU gets 2599 * a chance to update the errata work arounds and local features. 2600 * Otherwise, this CPU should verify that it has all the system 2601 * advertised capabilities. 2602 */ 2603 if (!system_capabilities_finalized()) 2604 update_cpu_capabilities(SCOPE_LOCAL_CPU); 2605 else 2606 verify_local_cpu_capabilities(); 2607 } 2608 2609 static void __init setup_boot_cpu_capabilities(void) 2610 { 2611 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 2612 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 2613 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 2614 enable_cpu_capabilities(SCOPE_BOOT_CPU); 2615 } 2616 2617 bool this_cpu_has_cap(unsigned int n) 2618 { 2619 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 2620 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2621 2622 if (cap) 2623 return cap->matches(cap, SCOPE_LOCAL_CPU); 2624 } 2625 2626 return false; 2627 } 2628 2629 /* 2630 * This helper function is used in a narrow window when, 2631 * - The system wide safe registers are set with all the SMP CPUs and, 2632 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 2633 * In all other cases cpus_have_{const_}cap() should be used. 2634 */ 2635 static bool __system_matches_cap(unsigned int n) 2636 { 2637 if (n < ARM64_NCAPS) { 2638 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2639 2640 if (cap) 2641 return cap->matches(cap, SCOPE_SYSTEM); 2642 } 2643 return false; 2644 } 2645 2646 void cpu_set_feature(unsigned int num) 2647 { 2648 WARN_ON(num >= MAX_CPU_FEATURES); 2649 elf_hwcap |= BIT(num); 2650 } 2651 EXPORT_SYMBOL_GPL(cpu_set_feature); 2652 2653 bool cpu_have_feature(unsigned int num) 2654 { 2655 WARN_ON(num >= MAX_CPU_FEATURES); 2656 return elf_hwcap & BIT(num); 2657 } 2658 EXPORT_SYMBOL_GPL(cpu_have_feature); 2659 2660 unsigned long cpu_get_elf_hwcap(void) 2661 { 2662 /* 2663 * We currently only populate the first 32 bits of AT_HWCAP. Please 2664 * note that for userspace compatibility we guarantee that bits 62 2665 * and 63 will always be returned as 0. 2666 */ 2667 return lower_32_bits(elf_hwcap); 2668 } 2669 2670 unsigned long cpu_get_elf_hwcap2(void) 2671 { 2672 return upper_32_bits(elf_hwcap); 2673 } 2674 2675 static void __init setup_system_capabilities(void) 2676 { 2677 /* 2678 * We have finalised the system-wide safe feature 2679 * registers, finalise the capabilities that depend 2680 * on it. Also enable all the available capabilities, 2681 * that are not enabled already. 2682 */ 2683 update_cpu_capabilities(SCOPE_SYSTEM); 2684 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2685 } 2686 2687 void __init setup_cpu_features(void) 2688 { 2689 u32 cwg; 2690 2691 setup_system_capabilities(); 2692 setup_elf_hwcaps(arm64_elf_hwcaps); 2693 2694 if (system_supports_32bit_el0()) 2695 setup_elf_hwcaps(compat_elf_hwcaps); 2696 2697 if (system_uses_ttbr0_pan()) 2698 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2699 2700 sve_setup(); 2701 minsigstksz_setup(); 2702 2703 /* Advertise that we have computed the system capabilities */ 2704 finalize_system_capabilities(); 2705 2706 /* 2707 * Check for sane CTR_EL0.CWG value. 2708 */ 2709 cwg = cache_type_cwg(); 2710 if (!cwg) 2711 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2712 ARCH_DMA_MINALIGN); 2713 } 2714 2715 static bool __maybe_unused 2716 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) 2717 { 2718 return (__system_matches_cap(ARM64_HAS_PAN) && !__system_matches_cap(ARM64_HAS_UAO)); 2719 } 2720 2721 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 2722 { 2723 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 2724 } 2725 2726 /* 2727 * We emulate only the following system register space. 2728 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 2729 * See Table C5-6 System instruction encodings for System register accesses, 2730 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 2731 */ 2732 static inline bool __attribute_const__ is_emulated(u32 id) 2733 { 2734 return (sys_reg_Op0(id) == 0x3 && 2735 sys_reg_CRn(id) == 0x0 && 2736 sys_reg_Op1(id) == 0x0 && 2737 (sys_reg_CRm(id) == 0 || 2738 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 2739 } 2740 2741 /* 2742 * With CRm == 0, reg should be one of : 2743 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 2744 */ 2745 static inline int emulate_id_reg(u32 id, u64 *valp) 2746 { 2747 switch (id) { 2748 case SYS_MIDR_EL1: 2749 *valp = read_cpuid_id(); 2750 break; 2751 case SYS_MPIDR_EL1: 2752 *valp = SYS_MPIDR_SAFE_VAL; 2753 break; 2754 case SYS_REVIDR_EL1: 2755 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 2756 *valp = 0; 2757 break; 2758 default: 2759 return -EINVAL; 2760 } 2761 2762 return 0; 2763 } 2764 2765 static int emulate_sys_reg(u32 id, u64 *valp) 2766 { 2767 struct arm64_ftr_reg *regp; 2768 2769 if (!is_emulated(id)) 2770 return -EINVAL; 2771 2772 if (sys_reg_CRm(id) == 0) 2773 return emulate_id_reg(id, valp); 2774 2775 regp = get_arm64_ftr_reg_nowarn(id); 2776 if (regp) 2777 *valp = arm64_ftr_reg_user_value(regp); 2778 else 2779 /* 2780 * The untracked registers are either IMPLEMENTATION DEFINED 2781 * (e.g, ID_AFR0_EL1) or reserved RAZ. 2782 */ 2783 *valp = 0; 2784 return 0; 2785 } 2786 2787 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 2788 { 2789 int rc; 2790 u64 val; 2791 2792 rc = emulate_sys_reg(sys_reg, &val); 2793 if (!rc) { 2794 pt_regs_write_reg(regs, rt, val); 2795 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 2796 } 2797 return rc; 2798 } 2799 2800 static int emulate_mrs(struct pt_regs *regs, u32 insn) 2801 { 2802 u32 sys_reg, rt; 2803 2804 /* 2805 * sys_reg values are defined as used in mrs/msr instruction. 2806 * shift the imm value to get the encoding. 2807 */ 2808 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 2809 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 2810 return do_emulate_mrs(regs, sys_reg, rt); 2811 } 2812 2813 static struct undef_hook mrs_hook = { 2814 .instr_mask = 0xfff00000, 2815 .instr_val = 0xd5300000, 2816 .pstate_mask = PSR_AA32_MODE_MASK, 2817 .pstate_val = PSR_MODE_EL0t, 2818 .fn = emulate_mrs, 2819 }; 2820 2821 static int __init enable_mrs_emulation(void) 2822 { 2823 register_undef_hook(&mrs_hook); 2824 return 0; 2825 } 2826 2827 core_initcall(enable_mrs_emulation); 2828 2829 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 2830 char *buf) 2831 { 2832 if (__meltdown_safe) 2833 return sprintf(buf, "Not affected\n"); 2834 2835 if (arm64_kernel_unmapped_at_el0()) 2836 return sprintf(buf, "Mitigation: PTI\n"); 2837 2838 return sprintf(buf, "Vulnerable\n"); 2839 } 2840