1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/sysfs.h> 71 #include <linux/types.h> 72 #include <linux/minmax.h> 73 #include <linux/mm.h> 74 #include <linux/cpu.h> 75 #include <linux/kasan.h> 76 #include <linux/percpu.h> 77 78 #include <asm/cpu.h> 79 #include <asm/cpufeature.h> 80 #include <asm/cpu_ops.h> 81 #include <asm/fpsimd.h> 82 #include <asm/insn.h> 83 #include <asm/kvm_host.h> 84 #include <asm/mmu_context.h> 85 #include <asm/mte.h> 86 #include <asm/processor.h> 87 #include <asm/smp.h> 88 #include <asm/sysreg.h> 89 #include <asm/traps.h> 90 #include <asm/vectors.h> 91 #include <asm/virt.h> 92 93 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 94 static unsigned long elf_hwcap __read_mostly; 95 96 #ifdef CONFIG_COMPAT 97 #define COMPAT_ELF_HWCAP_DEFAULT \ 98 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 99 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 100 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 101 COMPAT_HWCAP_LPAE) 102 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 103 unsigned int compat_elf_hwcap2 __read_mostly; 104 #endif 105 106 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 107 EXPORT_SYMBOL(cpu_hwcaps); 108 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 109 110 /* Need also bit for ARM64_CB_PATCH */ 111 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 112 113 bool arm64_use_ng_mappings = false; 114 EXPORT_SYMBOL(arm64_use_ng_mappings); 115 116 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 117 118 /* 119 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 120 * support it? 121 */ 122 static bool __read_mostly allow_mismatched_32bit_el0; 123 124 /* 125 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 126 * seen at least one CPU capable of 32-bit EL0. 127 */ 128 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 129 130 /* 131 * Mask of CPUs supporting 32-bit EL0. 132 * Only valid if arm64_mismatched_32bit_el0 is enabled. 133 */ 134 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 135 136 /* 137 * Flag to indicate if we have computed the system wide 138 * capabilities based on the boot time active CPUs. This 139 * will be used to determine if a new booting CPU should 140 * go through the verification process to make sure that it 141 * supports the system capabilities, without using a hotplug 142 * notifier. This is also used to decide if we could use 143 * the fast path for checking constant CPU caps. 144 */ 145 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 146 EXPORT_SYMBOL(arm64_const_caps_ready); 147 static inline void finalize_system_capabilities(void) 148 { 149 static_branch_enable(&arm64_const_caps_ready); 150 } 151 152 void dump_cpu_features(void) 153 { 154 /* file-wide pr_fmt adds "CPU features: " prefix */ 155 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 156 } 157 158 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 159 EXPORT_SYMBOL(cpu_hwcap_keys); 160 161 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 162 { \ 163 .sign = SIGNED, \ 164 .visible = VISIBLE, \ 165 .strict = STRICT, \ 166 .type = TYPE, \ 167 .shift = SHIFT, \ 168 .width = WIDTH, \ 169 .safe_val = SAFE_VAL, \ 170 } 171 172 /* Define a feature with unsigned values */ 173 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 174 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 175 176 /* Define a feature with a signed value */ 177 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 178 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 179 180 #define ARM64_FTR_END \ 181 { \ 182 .width = 0, \ 183 } 184 185 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 186 187 static bool __system_matches_cap(unsigned int n); 188 189 /* 190 * NOTE: Any changes to the visibility of features should be kept in 191 * sync with the documentation of the CPU feature register ABI. 192 */ 193 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 208 ARM64_FTR_END, 209 }; 210 211 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 219 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 221 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 226 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 228 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 230 ARM64_FTR_END, 231 }; 232 233 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0), 236 ARM64_FTR_END, 237 }; 238 239 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 247 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 250 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 251 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), 255 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), 256 ARM64_FTR_END, 257 }; 258 259 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI), 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 265 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 266 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 267 ARM64_FTR_END, 268 }; 269 270 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 271 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 272 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 276 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 278 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 280 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 282 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 284 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 286 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 288 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 289 ARM64_FTR_END, 290 }; 291 292 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 293 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), 296 /* 297 * Page size not being supported at Stage-2 is not fatal. You 298 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 299 * your favourite nesting hypervisor. 300 * 301 * There is a small corner case where the hypervisor explicitly 302 * advertises a given granule size at Stage-2 (value 2) on some 303 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 304 * vCPUs. Although this is not forbidden by the architecture, it 305 * indicates that the hypervisor is being silly (or buggy). 306 * 307 * We make no effort to cope with this and pretend that if these 308 * fields are inconsistent across vCPUs, then it isn't worth 309 * trying to bring KVM up. 310 */ 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 314 /* 315 * We already refuse to boot CPUs that don't support our configured 316 * page size, so we can only detect mismatches for a page size other 317 * than the one we're currently using. Unfortunately, SoCs like this 318 * exist in the wild so, even though we don't like it, we'll have to go 319 * along with it and treat them as non-strict. 320 */ 321 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 322 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 324 325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 326 /* Linux shouldn't care about secure memory */ 327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 330 /* 331 * Differing PARange is fine as long as all peripherals and memory are mapped 332 * within the minimum PARange of all CPUs 333 */ 334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 335 ARM64_FTR_END, 336 }; 337 338 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 339 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0), 340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), 341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), 342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 345 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 350 ARM64_FTR_END, 351 }; 352 353 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0), 356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0), 357 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0), 358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 359 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0), 360 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 361 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0), 362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0), 363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0), 364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 369 ARM64_FTR_END, 370 }; 371 372 static const struct arm64_ftr_bits ftr_ctr[] = { 373 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 374 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 375 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 376 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 378 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 379 /* 380 * Linux can handle differing I-cache policies. Userspace JITs will 381 * make use of *minLine. 382 * If we have differing I-cache policies, report it as the weakest - VIPT. 383 */ 384 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 385 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 386 ARM64_FTR_END, 387 }; 388 389 static struct arm64_ftr_override __ro_after_init no_override = { }; 390 391 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 392 .name = "SYS_CTR_EL0", 393 .ftr_bits = ftr_ctr, 394 .override = &no_override, 395 }; 396 397 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 398 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 399 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 401 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 403 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 406 ARM64_FTR_END, 407 }; 408 409 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 410 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0), 411 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 415 /* 416 * We can instantiate multiple PMU instances with different levels 417 * of support. 418 */ 419 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 421 ARM64_FTR_END, 422 }; 423 424 static const struct arm64_ftr_bits ftr_mvfr2[] = { 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 427 ARM64_FTR_END, 428 }; 429 430 static const struct arm64_ftr_bits ftr_dczid[] = { 431 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), 432 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), 433 ARM64_FTR_END, 434 }; 435 436 static const struct arm64_ftr_bits ftr_gmid[] = { 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0), 438 ARM64_FTR_END, 439 }; 440 441 static const struct arm64_ftr_bits ftr_id_isar0[] = { 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 449 ARM64_FTR_END, 450 }; 451 452 static const struct arm64_ftr_bits ftr_id_isar5[] = { 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 459 ARM64_FTR_END, 460 }; 461 462 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 470 471 /* 472 * SpecSEI = 1 indicates that the PE might generate an SError on an 473 * external abort on speculative read. It is safe to assume that an 474 * SError might be generated than it will not be. Hence it has been 475 * classified as FTR_HIGHER_SAFE. 476 */ 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 478 ARM64_FTR_END, 479 }; 480 481 static const struct arm64_ftr_bits ftr_id_isar4[] = { 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 490 ARM64_FTR_END, 491 }; 492 493 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 495 ARM64_FTR_END, 496 }; 497 498 static const struct arm64_ftr_bits ftr_id_isar6[] = { 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 506 ARM64_FTR_END, 507 }; 508 509 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 516 ARM64_FTR_END, 517 }; 518 519 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 522 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 523 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 524 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 528 ARM64_FTR_END, 529 }; 530 531 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 534 ARM64_FTR_END, 535 }; 536 537 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 538 /* [31:28] TraceFilt */ 539 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf), 540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 546 ARM64_FTR_END, 547 }; 548 549 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 550 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 551 ARM64_FTR_END, 552 }; 553 554 static const struct arm64_ftr_bits ftr_zcr[] = { 555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 556 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 557 ARM64_FTR_END, 558 }; 559 560 /* 561 * Common ftr bits for a 32bit register with all hidden, strict 562 * attributes, with 4bit feature fields and a default safe value of 563 * 0. Covers the following 32bit registers: 564 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 565 */ 566 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 575 ARM64_FTR_END, 576 }; 577 578 /* Table for a single 32bit feature value */ 579 static const struct arm64_ftr_bits ftr_single32[] = { 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 581 ARM64_FTR_END, 582 }; 583 584 static const struct arm64_ftr_bits ftr_raz[] = { 585 ARM64_FTR_END, 586 }; 587 588 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 589 .sys_id = id, \ 590 .reg = &(struct arm64_ftr_reg){ \ 591 .name = id_str, \ 592 .override = (ovr), \ 593 .ftr_bits = &((table)[0]), \ 594 }} 595 596 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 597 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 598 599 #define ARM64_FTR_REG(id, table) \ 600 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 601 602 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 603 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 604 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 605 606 static const struct __ftr_reg_entry { 607 u32 sys_id; 608 struct arm64_ftr_reg *reg; 609 } arm64_ftr_regs[] = { 610 611 /* Op1 = 0, CRn = 0, CRm = 1 */ 612 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 613 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 614 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 615 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 616 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 617 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 618 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 619 620 /* Op1 = 0, CRn = 0, CRm = 2 */ 621 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 622 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 623 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 624 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 625 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 626 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 627 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 628 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 629 630 /* Op1 = 0, CRn = 0, CRm = 3 */ 631 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 632 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 633 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 634 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 635 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 636 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 637 638 /* Op1 = 0, CRn = 0, CRm = 4 */ 639 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 640 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 641 &id_aa64pfr1_override), 642 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 643 644 /* Op1 = 0, CRn = 0, CRm = 5 */ 645 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 646 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 647 648 /* Op1 = 0, CRn = 0, CRm = 6 */ 649 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 650 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 651 &id_aa64isar1_override), 652 ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2), 653 654 /* Op1 = 0, CRn = 0, CRm = 7 */ 655 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 656 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 657 &id_aa64mmfr1_override), 658 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 659 660 /* Op1 = 0, CRn = 1, CRm = 2 */ 661 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 662 663 /* Op1 = 1, CRn = 0, CRm = 0 */ 664 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 665 666 /* Op1 = 3, CRn = 0, CRm = 0 */ 667 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 668 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 669 670 /* Op1 = 3, CRn = 14, CRm = 0 */ 671 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 672 }; 673 674 static int search_cmp_ftr_reg(const void *id, const void *regp) 675 { 676 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 677 } 678 679 /* 680 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 681 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 682 * ascending order of sys_id, we use binary search to find a matching 683 * entry. 684 * 685 * returns - Upon success, matching ftr_reg entry for id. 686 * - NULL on failure. It is upto the caller to decide 687 * the impact of a failure. 688 */ 689 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 690 { 691 const struct __ftr_reg_entry *ret; 692 693 ret = bsearch((const void *)(unsigned long)sys_id, 694 arm64_ftr_regs, 695 ARRAY_SIZE(arm64_ftr_regs), 696 sizeof(arm64_ftr_regs[0]), 697 search_cmp_ftr_reg); 698 if (ret) 699 return ret->reg; 700 return NULL; 701 } 702 703 /* 704 * get_arm64_ftr_reg - Looks up a feature register entry using 705 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 706 * 707 * returns - Upon success, matching ftr_reg entry for id. 708 * - NULL on failure but with an WARN_ON(). 709 */ 710 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 711 { 712 struct arm64_ftr_reg *reg; 713 714 reg = get_arm64_ftr_reg_nowarn(sys_id); 715 716 /* 717 * Requesting a non-existent register search is an error. Warn 718 * and let the caller handle it. 719 */ 720 WARN_ON(!reg); 721 return reg; 722 } 723 724 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 725 s64 ftr_val) 726 { 727 u64 mask = arm64_ftr_mask(ftrp); 728 729 reg &= ~mask; 730 reg |= (ftr_val << ftrp->shift) & mask; 731 return reg; 732 } 733 734 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 735 s64 cur) 736 { 737 s64 ret = 0; 738 739 switch (ftrp->type) { 740 case FTR_EXACT: 741 ret = ftrp->safe_val; 742 break; 743 case FTR_LOWER_SAFE: 744 ret = min(new, cur); 745 break; 746 case FTR_HIGHER_OR_ZERO_SAFE: 747 if (!cur || !new) 748 break; 749 fallthrough; 750 case FTR_HIGHER_SAFE: 751 ret = max(new, cur); 752 break; 753 default: 754 BUG(); 755 } 756 757 return ret; 758 } 759 760 static void __init sort_ftr_regs(void) 761 { 762 unsigned int i; 763 764 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 765 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 766 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 767 unsigned int j = 0; 768 769 /* 770 * Features here must be sorted in descending order with respect 771 * to their shift values and should not overlap with each other. 772 */ 773 for (; ftr_bits->width != 0; ftr_bits++, j++) { 774 unsigned int width = ftr_reg->ftr_bits[j].width; 775 unsigned int shift = ftr_reg->ftr_bits[j].shift; 776 unsigned int prev_shift; 777 778 WARN((shift + width) > 64, 779 "%s has invalid feature at shift %d\n", 780 ftr_reg->name, shift); 781 782 /* 783 * Skip the first feature. There is nothing to 784 * compare against for now. 785 */ 786 if (j == 0) 787 continue; 788 789 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 790 WARN((shift + width) > prev_shift, 791 "%s has feature overlap at shift %d\n", 792 ftr_reg->name, shift); 793 } 794 795 /* 796 * Skip the first register. There is nothing to 797 * compare against for now. 798 */ 799 if (i == 0) 800 continue; 801 /* 802 * Registers here must be sorted in ascending order with respect 803 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 804 * to work correctly. 805 */ 806 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 807 } 808 } 809 810 /* 811 * Initialise the CPU feature register from Boot CPU values. 812 * Also initiliases the strict_mask for the register. 813 * Any bits that are not covered by an arm64_ftr_bits entry are considered 814 * RES0 for the system-wide value, and must strictly match. 815 */ 816 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 817 { 818 u64 val = 0; 819 u64 strict_mask = ~0x0ULL; 820 u64 user_mask = 0; 821 u64 valid_mask = 0; 822 823 const struct arm64_ftr_bits *ftrp; 824 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 825 826 if (!reg) 827 return; 828 829 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 830 u64 ftr_mask = arm64_ftr_mask(ftrp); 831 s64 ftr_new = arm64_ftr_value(ftrp, new); 832 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 833 834 if ((ftr_mask & reg->override->mask) == ftr_mask) { 835 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 836 char *str = NULL; 837 838 if (ftr_ovr != tmp) { 839 /* Unsafe, remove the override */ 840 reg->override->mask &= ~ftr_mask; 841 reg->override->val &= ~ftr_mask; 842 tmp = ftr_ovr; 843 str = "ignoring override"; 844 } else if (ftr_new != tmp) { 845 /* Override was valid */ 846 ftr_new = tmp; 847 str = "forced"; 848 } else if (ftr_ovr == tmp) { 849 /* Override was the safe value */ 850 str = "already set"; 851 } 852 853 if (str) 854 pr_warn("%s[%d:%d]: %s to %llx\n", 855 reg->name, 856 ftrp->shift + ftrp->width - 1, 857 ftrp->shift, str, tmp); 858 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 859 reg->override->val &= ~ftr_mask; 860 pr_warn("%s[%d:%d]: impossible override, ignored\n", 861 reg->name, 862 ftrp->shift + ftrp->width - 1, 863 ftrp->shift); 864 } 865 866 val = arm64_ftr_set_value(ftrp, val, ftr_new); 867 868 valid_mask |= ftr_mask; 869 if (!ftrp->strict) 870 strict_mask &= ~ftr_mask; 871 if (ftrp->visible) 872 user_mask |= ftr_mask; 873 else 874 reg->user_val = arm64_ftr_set_value(ftrp, 875 reg->user_val, 876 ftrp->safe_val); 877 } 878 879 val &= valid_mask; 880 881 reg->sys_val = val; 882 reg->strict_mask = strict_mask; 883 reg->user_mask = user_mask; 884 } 885 886 extern const struct arm64_cpu_capabilities arm64_errata[]; 887 static const struct arm64_cpu_capabilities arm64_features[]; 888 889 static void __init 890 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 891 { 892 for (; caps->matches; caps++) { 893 if (WARN(caps->capability >= ARM64_NCAPS, 894 "Invalid capability %d\n", caps->capability)) 895 continue; 896 if (WARN(cpu_hwcaps_ptrs[caps->capability], 897 "Duplicate entry for capability %d\n", 898 caps->capability)) 899 continue; 900 cpu_hwcaps_ptrs[caps->capability] = caps; 901 } 902 } 903 904 static void __init init_cpu_hwcaps_indirect_list(void) 905 { 906 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 907 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 908 } 909 910 static void __init setup_boot_cpu_capabilities(void); 911 912 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 913 { 914 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 915 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 916 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 917 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 918 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 919 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 920 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 921 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 922 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 923 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 924 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 925 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 926 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 927 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 928 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 929 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 930 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 931 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 932 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 933 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 934 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 935 } 936 937 void __init init_cpu_features(struct cpuinfo_arm64 *info) 938 { 939 /* Before we start using the tables, make sure it is sorted */ 940 sort_ftr_regs(); 941 942 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 943 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 944 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 945 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 946 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 947 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 948 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 949 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 950 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 951 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 952 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 953 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 954 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 955 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 956 957 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 958 init_32bit_cpu_features(&info->aarch32); 959 960 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 961 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 962 vec_init_vq_map(ARM64_VEC_SVE); 963 } 964 965 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 966 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 967 968 /* 969 * Initialize the indirect array of CPU hwcaps capabilities pointers 970 * before we handle the boot CPU below. 971 */ 972 init_cpu_hwcaps_indirect_list(); 973 974 /* 975 * Detect and enable early CPU capabilities based on the boot CPU, 976 * after we have initialised the CPU feature infrastructure. 977 */ 978 setup_boot_cpu_capabilities(); 979 } 980 981 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 982 { 983 const struct arm64_ftr_bits *ftrp; 984 985 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 986 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 987 s64 ftr_new = arm64_ftr_value(ftrp, new); 988 989 if (ftr_cur == ftr_new) 990 continue; 991 /* Find a safe value */ 992 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 993 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 994 } 995 996 } 997 998 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 999 { 1000 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1001 1002 if (!regp) 1003 return 0; 1004 1005 update_cpu_ftr_reg(regp, val); 1006 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1007 return 0; 1008 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1009 regp->name, boot, cpu, val); 1010 return 1; 1011 } 1012 1013 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1014 { 1015 const struct arm64_ftr_bits *ftrp; 1016 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1017 1018 if (!regp) 1019 return; 1020 1021 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1022 if (ftrp->shift == field) { 1023 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1024 break; 1025 } 1026 } 1027 1028 /* Bogus field? */ 1029 WARN_ON(!ftrp->width); 1030 } 1031 1032 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1033 struct cpuinfo_arm64 *boot) 1034 { 1035 static bool boot_cpu_32bit_regs_overridden = false; 1036 1037 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1038 return; 1039 1040 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1041 return; 1042 1043 boot->aarch32 = info->aarch32; 1044 init_32bit_cpu_features(&boot->aarch32); 1045 boot_cpu_32bit_regs_overridden = true; 1046 } 1047 1048 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1049 struct cpuinfo_32bit *boot) 1050 { 1051 int taint = 0; 1052 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1053 1054 /* 1055 * If we don't have AArch32 at EL1, then relax the strictness of 1056 * EL1-dependent register fields to avoid spurious sanity check fails. 1057 */ 1058 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1059 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 1060 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 1061 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 1062 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 1063 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 1064 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 1065 } 1066 1067 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1068 info->reg_id_dfr0, boot->reg_id_dfr0); 1069 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1070 info->reg_id_dfr1, boot->reg_id_dfr1); 1071 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1072 info->reg_id_isar0, boot->reg_id_isar0); 1073 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1074 info->reg_id_isar1, boot->reg_id_isar1); 1075 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1076 info->reg_id_isar2, boot->reg_id_isar2); 1077 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1078 info->reg_id_isar3, boot->reg_id_isar3); 1079 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1080 info->reg_id_isar4, boot->reg_id_isar4); 1081 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1082 info->reg_id_isar5, boot->reg_id_isar5); 1083 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1084 info->reg_id_isar6, boot->reg_id_isar6); 1085 1086 /* 1087 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1088 * ACTLR formats could differ across CPUs and therefore would have to 1089 * be trapped for virtualization anyway. 1090 */ 1091 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1092 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1093 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1094 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1095 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1096 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1097 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1098 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1099 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1100 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1101 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1102 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1103 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1104 info->reg_id_pfr0, boot->reg_id_pfr0); 1105 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1106 info->reg_id_pfr1, boot->reg_id_pfr1); 1107 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1108 info->reg_id_pfr2, boot->reg_id_pfr2); 1109 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1110 info->reg_mvfr0, boot->reg_mvfr0); 1111 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1112 info->reg_mvfr1, boot->reg_mvfr1); 1113 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1114 info->reg_mvfr2, boot->reg_mvfr2); 1115 1116 return taint; 1117 } 1118 1119 /* 1120 * Update system wide CPU feature registers with the values from a 1121 * non-boot CPU. Also performs SANITY checks to make sure that there 1122 * aren't any insane variations from that of the boot CPU. 1123 */ 1124 void update_cpu_features(int cpu, 1125 struct cpuinfo_arm64 *info, 1126 struct cpuinfo_arm64 *boot) 1127 { 1128 int taint = 0; 1129 1130 /* 1131 * The kernel can handle differing I-cache policies, but otherwise 1132 * caches should look identical. Userspace JITs will make use of 1133 * *minLine. 1134 */ 1135 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1136 info->reg_ctr, boot->reg_ctr); 1137 1138 /* 1139 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1140 * could result in too much or too little memory being zeroed if a 1141 * process is preempted and migrated between CPUs. 1142 */ 1143 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1144 info->reg_dczid, boot->reg_dczid); 1145 1146 /* If different, timekeeping will be broken (especially with KVM) */ 1147 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1148 info->reg_cntfrq, boot->reg_cntfrq); 1149 1150 /* 1151 * The kernel uses self-hosted debug features and expects CPUs to 1152 * support identical debug features. We presently need CTX_CMPs, WRPs, 1153 * and BRPs to be identical. 1154 * ID_AA64DFR1 is currently RES0. 1155 */ 1156 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1157 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1158 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1159 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1160 /* 1161 * Even in big.LITTLE, processors should be identical instruction-set 1162 * wise. 1163 */ 1164 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1165 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1166 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1167 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1168 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1169 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1170 1171 /* 1172 * Differing PARange support is fine as long as all peripherals and 1173 * memory are mapped within the minimum PARange of all CPUs. 1174 * Linux should not care about secure memory. 1175 */ 1176 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1177 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1178 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1179 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1180 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1181 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1182 1183 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1184 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1185 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1186 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1187 1188 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1189 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1190 1191 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 1192 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1193 info->reg_zcr, boot->reg_zcr); 1194 1195 /* Probe vector lengths, unless we already gave up on SVE */ 1196 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 1197 !system_capabilities_finalized()) 1198 vec_update_vq_map(ARM64_VEC_SVE); 1199 } 1200 1201 /* 1202 * The kernel uses the LDGM/STGM instructions and the number of tags 1203 * they read/write depends on the GMID_EL1.BS field. Check that the 1204 * value is the same on all CPUs. 1205 */ 1206 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1207 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1208 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1209 info->reg_gmid, boot->reg_gmid); 1210 } 1211 1212 /* 1213 * If we don't have AArch32 at all then skip the checks entirely 1214 * as the register values may be UNKNOWN and we're not going to be 1215 * using them for anything. 1216 * 1217 * This relies on a sanitised view of the AArch64 ID registers 1218 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1219 */ 1220 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1221 lazy_init_32bit_cpu_features(info, boot); 1222 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1223 &boot->aarch32); 1224 } 1225 1226 /* 1227 * Mismatched CPU features are a recipe for disaster. Don't even 1228 * pretend to support them. 1229 */ 1230 if (taint) { 1231 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1232 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1233 } 1234 } 1235 1236 u64 read_sanitised_ftr_reg(u32 id) 1237 { 1238 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1239 1240 if (!regp) 1241 return 0; 1242 return regp->sys_val; 1243 } 1244 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1245 1246 #define read_sysreg_case(r) \ 1247 case r: val = read_sysreg_s(r); break; 1248 1249 /* 1250 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1251 * Read the system register on the current CPU 1252 */ 1253 u64 __read_sysreg_by_encoding(u32 sys_id) 1254 { 1255 struct arm64_ftr_reg *regp; 1256 u64 val; 1257 1258 switch (sys_id) { 1259 read_sysreg_case(SYS_ID_PFR0_EL1); 1260 read_sysreg_case(SYS_ID_PFR1_EL1); 1261 read_sysreg_case(SYS_ID_PFR2_EL1); 1262 read_sysreg_case(SYS_ID_DFR0_EL1); 1263 read_sysreg_case(SYS_ID_DFR1_EL1); 1264 read_sysreg_case(SYS_ID_MMFR0_EL1); 1265 read_sysreg_case(SYS_ID_MMFR1_EL1); 1266 read_sysreg_case(SYS_ID_MMFR2_EL1); 1267 read_sysreg_case(SYS_ID_MMFR3_EL1); 1268 read_sysreg_case(SYS_ID_MMFR4_EL1); 1269 read_sysreg_case(SYS_ID_MMFR5_EL1); 1270 read_sysreg_case(SYS_ID_ISAR0_EL1); 1271 read_sysreg_case(SYS_ID_ISAR1_EL1); 1272 read_sysreg_case(SYS_ID_ISAR2_EL1); 1273 read_sysreg_case(SYS_ID_ISAR3_EL1); 1274 read_sysreg_case(SYS_ID_ISAR4_EL1); 1275 read_sysreg_case(SYS_ID_ISAR5_EL1); 1276 read_sysreg_case(SYS_ID_ISAR6_EL1); 1277 read_sysreg_case(SYS_MVFR0_EL1); 1278 read_sysreg_case(SYS_MVFR1_EL1); 1279 read_sysreg_case(SYS_MVFR2_EL1); 1280 1281 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1282 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1283 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1284 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1285 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1286 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1287 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1288 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1289 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1290 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1291 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1292 1293 read_sysreg_case(SYS_CNTFRQ_EL0); 1294 read_sysreg_case(SYS_CTR_EL0); 1295 read_sysreg_case(SYS_DCZID_EL0); 1296 1297 default: 1298 BUG(); 1299 return 0; 1300 } 1301 1302 regp = get_arm64_ftr_reg(sys_id); 1303 if (regp) { 1304 val &= ~regp->override->mask; 1305 val |= (regp->override->val & regp->override->mask); 1306 } 1307 1308 return val; 1309 } 1310 1311 #include <linux/irqchip/arm-gic-v3.h> 1312 1313 static bool 1314 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1315 { 1316 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 1317 1318 return val >= entry->min_field_value; 1319 } 1320 1321 static bool 1322 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1323 { 1324 u64 val; 1325 1326 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1327 if (scope == SCOPE_SYSTEM) 1328 val = read_sanitised_ftr_reg(entry->sys_reg); 1329 else 1330 val = __read_sysreg_by_encoding(entry->sys_reg); 1331 1332 return feature_matches(val, entry); 1333 } 1334 1335 const struct cpumask *system_32bit_el0_cpumask(void) 1336 { 1337 if (!system_supports_32bit_el0()) 1338 return cpu_none_mask; 1339 1340 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1341 return cpu_32bit_el0_mask; 1342 1343 return cpu_possible_mask; 1344 } 1345 1346 static int __init parse_32bit_el0_param(char *str) 1347 { 1348 allow_mismatched_32bit_el0 = true; 1349 return 0; 1350 } 1351 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1352 1353 static ssize_t aarch32_el0_show(struct device *dev, 1354 struct device_attribute *attr, char *buf) 1355 { 1356 const struct cpumask *mask = system_32bit_el0_cpumask(); 1357 1358 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1359 } 1360 static const DEVICE_ATTR_RO(aarch32_el0); 1361 1362 static int __init aarch32_el0_sysfs_init(void) 1363 { 1364 if (!allow_mismatched_32bit_el0) 1365 return 0; 1366 1367 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0); 1368 } 1369 device_initcall(aarch32_el0_sysfs_init); 1370 1371 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1372 { 1373 if (!has_cpuid_feature(entry, scope)) 1374 return allow_mismatched_32bit_el0; 1375 1376 if (scope == SCOPE_SYSTEM) 1377 pr_info("detected: 32-bit EL0 Support\n"); 1378 1379 return true; 1380 } 1381 1382 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1383 { 1384 bool has_sre; 1385 1386 if (!has_cpuid_feature(entry, scope)) 1387 return false; 1388 1389 has_sre = gic_enable_sre(); 1390 if (!has_sre) 1391 pr_warn_once("%s present but disabled by higher exception level\n", 1392 entry->desc); 1393 1394 return has_sre; 1395 } 1396 1397 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1398 { 1399 u32 midr = read_cpuid_id(); 1400 1401 /* Cavium ThunderX pass 1.x and 2.x */ 1402 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1403 MIDR_CPU_VAR_REV(0, 0), 1404 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1405 } 1406 1407 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1408 { 1409 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1410 1411 return cpuid_feature_extract_signed_field(pfr0, 1412 ID_AA64PFR0_FP_SHIFT) < 0; 1413 } 1414 1415 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1416 int scope) 1417 { 1418 u64 ctr; 1419 1420 if (scope == SCOPE_SYSTEM) 1421 ctr = arm64_ftr_reg_ctrel0.sys_val; 1422 else 1423 ctr = read_cpuid_effective_cachetype(); 1424 1425 return ctr & BIT(CTR_IDC_SHIFT); 1426 } 1427 1428 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1429 { 1430 /* 1431 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1432 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1433 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1434 * value. 1435 */ 1436 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 1437 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1438 } 1439 1440 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1441 int scope) 1442 { 1443 u64 ctr; 1444 1445 if (scope == SCOPE_SYSTEM) 1446 ctr = arm64_ftr_reg_ctrel0.sys_val; 1447 else 1448 ctr = read_cpuid_cachetype(); 1449 1450 return ctr & BIT(CTR_DIC_SHIFT); 1451 } 1452 1453 static bool __maybe_unused 1454 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1455 { 1456 /* 1457 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1458 * may share TLB entries with a CPU stuck in the crashed 1459 * kernel. 1460 */ 1461 if (is_kdump_kernel()) 1462 return false; 1463 1464 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1465 return false; 1466 1467 return has_cpuid_feature(entry, scope); 1468 } 1469 1470 /* 1471 * This check is triggered during the early boot before the cpufeature 1472 * is initialised. Checking the status on the local CPU allows the boot 1473 * CPU to detect the need for non-global mappings and thus avoiding a 1474 * pagetable re-write after all the CPUs are booted. This check will be 1475 * anyway run on individual CPUs, allowing us to get the consistent 1476 * state once the SMP CPUs are up and thus make the switch to non-global 1477 * mappings if required. 1478 */ 1479 bool kaslr_requires_kpti(void) 1480 { 1481 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1482 return false; 1483 1484 /* 1485 * E0PD does a similar job to KPTI so can be used instead 1486 * where available. 1487 */ 1488 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1489 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1490 if (cpuid_feature_extract_unsigned_field(mmfr2, 1491 ID_AA64MMFR2_E0PD_SHIFT)) 1492 return false; 1493 } 1494 1495 /* 1496 * Systems affected by Cavium erratum 24756 are incompatible 1497 * with KPTI. 1498 */ 1499 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1500 extern const struct midr_range cavium_erratum_27456_cpus[]; 1501 1502 if (is_midr_in_range_list(read_cpuid_id(), 1503 cavium_erratum_27456_cpus)) 1504 return false; 1505 } 1506 1507 return kaslr_offset() > 0; 1508 } 1509 1510 static bool __meltdown_safe = true; 1511 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1512 1513 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1514 int scope) 1515 { 1516 /* List of CPUs that are not vulnerable and don't need KPTI */ 1517 static const struct midr_range kpti_safe_list[] = { 1518 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1519 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1520 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1521 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1522 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1523 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1524 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1525 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1526 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1527 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1528 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1529 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1530 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1531 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1532 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1533 { /* sentinel */ } 1534 }; 1535 char const *str = "kpti command line option"; 1536 bool meltdown_safe; 1537 1538 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1539 1540 /* Defer to CPU feature registers */ 1541 if (has_cpuid_feature(entry, scope)) 1542 meltdown_safe = true; 1543 1544 if (!meltdown_safe) 1545 __meltdown_safe = false; 1546 1547 /* 1548 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1549 * ThunderX leads to apparent I-cache corruption of kernel text, which 1550 * ends as well as you might imagine. Don't even try. We cannot rely 1551 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1552 * because cpucap detection order may change. However, since we know 1553 * affected CPUs are always in a homogeneous configuration, it is 1554 * safe to rely on this_cpu_has_cap() here. 1555 */ 1556 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1557 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1558 __kpti_forced = -1; 1559 } 1560 1561 /* Useful for KASLR robustness */ 1562 if (kaslr_requires_kpti()) { 1563 if (!__kpti_forced) { 1564 str = "KASLR"; 1565 __kpti_forced = 1; 1566 } 1567 } 1568 1569 if (cpu_mitigations_off() && !__kpti_forced) { 1570 str = "mitigations=off"; 1571 __kpti_forced = -1; 1572 } 1573 1574 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1575 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1576 return false; 1577 } 1578 1579 /* Forced? */ 1580 if (__kpti_forced) { 1581 pr_info_once("kernel page table isolation forced %s by %s\n", 1582 __kpti_forced > 0 ? "ON" : "OFF", str); 1583 return __kpti_forced > 0; 1584 } 1585 1586 return !meltdown_safe; 1587 } 1588 1589 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1590 static void __nocfi 1591 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1592 { 1593 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1594 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1595 kpti_remap_fn *remap_fn; 1596 1597 int cpu = smp_processor_id(); 1598 1599 if (__this_cpu_read(this_cpu_vector) == vectors) { 1600 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1601 1602 __this_cpu_write(this_cpu_vector, v); 1603 } 1604 1605 /* 1606 * We don't need to rewrite the page-tables if either we've done 1607 * it already or we have KASLR enabled and therefore have not 1608 * created any global mappings at all. 1609 */ 1610 if (arm64_use_ng_mappings) 1611 return; 1612 1613 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings)); 1614 1615 cpu_install_idmap(); 1616 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1617 cpu_uninstall_idmap(); 1618 1619 if (!cpu) 1620 arm64_use_ng_mappings = true; 1621 } 1622 #else 1623 static void 1624 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1625 { 1626 } 1627 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1628 1629 static int __init parse_kpti(char *str) 1630 { 1631 bool enabled; 1632 int ret = strtobool(str, &enabled); 1633 1634 if (ret) 1635 return ret; 1636 1637 __kpti_forced = enabled ? 1 : -1; 1638 return 0; 1639 } 1640 early_param("kpti", parse_kpti); 1641 1642 #ifdef CONFIG_ARM64_HW_AFDBM 1643 static inline void __cpu_enable_hw_dbm(void) 1644 { 1645 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1646 1647 write_sysreg(tcr, tcr_el1); 1648 isb(); 1649 local_flush_tlb_all(); 1650 } 1651 1652 static bool cpu_has_broken_dbm(void) 1653 { 1654 /* List of CPUs which have broken DBM support. */ 1655 static const struct midr_range cpus[] = { 1656 #ifdef CONFIG_ARM64_ERRATUM_1024718 1657 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1658 /* Kryo4xx Silver (rdpe => r1p0) */ 1659 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1660 #endif 1661 #ifdef CONFIG_ARM64_ERRATUM_2051678 1662 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1663 #endif 1664 {}, 1665 }; 1666 1667 return is_midr_in_range_list(read_cpuid_id(), cpus); 1668 } 1669 1670 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1671 { 1672 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1673 !cpu_has_broken_dbm(); 1674 } 1675 1676 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1677 { 1678 if (cpu_can_use_dbm(cap)) 1679 __cpu_enable_hw_dbm(); 1680 } 1681 1682 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1683 int __unused) 1684 { 1685 static bool detected = false; 1686 /* 1687 * DBM is a non-conflicting feature. i.e, the kernel can safely 1688 * run a mix of CPUs with and without the feature. So, we 1689 * unconditionally enable the capability to allow any late CPU 1690 * to use the feature. We only enable the control bits on the 1691 * CPU, if it actually supports. 1692 * 1693 * We have to make sure we print the "feature" detection only 1694 * when at least one CPU actually uses it. So check if this CPU 1695 * can actually use it and print the message exactly once. 1696 * 1697 * This is safe as all CPUs (including secondary CPUs - due to the 1698 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1699 * goes through the "matches" check exactly once. Also if a CPU 1700 * matches the criteria, it is guaranteed that the CPU will turn 1701 * the DBM on, as the capability is unconditionally enabled. 1702 */ 1703 if (!detected && cpu_can_use_dbm(cap)) { 1704 detected = true; 1705 pr_info("detected: Hardware dirty bit management\n"); 1706 } 1707 1708 return true; 1709 } 1710 1711 #endif 1712 1713 #ifdef CONFIG_ARM64_AMU_EXTN 1714 1715 /* 1716 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1717 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1718 * information regarding all the events that it supports. When a CPU bit is 1719 * set in the cpumask, the user of this feature can only rely on the presence 1720 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1721 * counters are enabled or access to these counters is enabled by code 1722 * executed at higher exception levels (firmware). 1723 */ 1724 static struct cpumask amu_cpus __read_mostly; 1725 1726 bool cpu_has_amu_feat(int cpu) 1727 { 1728 return cpumask_test_cpu(cpu, &amu_cpus); 1729 } 1730 1731 int get_cpu_with_amu_feat(void) 1732 { 1733 return cpumask_any(&amu_cpus); 1734 } 1735 1736 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1737 { 1738 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1739 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1740 smp_processor_id()); 1741 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1742 update_freq_counters_refs(); 1743 } 1744 } 1745 1746 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1747 int __unused) 1748 { 1749 /* 1750 * The AMU extension is a non-conflicting feature: the kernel can 1751 * safely run a mix of CPUs with and without support for the 1752 * activity monitors extension. Therefore, unconditionally enable 1753 * the capability to allow any late CPU to use the feature. 1754 * 1755 * With this feature unconditionally enabled, the cpu_enable 1756 * function will be called for all CPUs that match the criteria, 1757 * including secondary and hotplugged, marking this feature as 1758 * present on that respective CPU. The enable function will also 1759 * print a detection message. 1760 */ 1761 1762 return true; 1763 } 1764 #else 1765 int get_cpu_with_amu_feat(void) 1766 { 1767 return nr_cpu_ids; 1768 } 1769 #endif 1770 1771 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1772 { 1773 return is_kernel_in_hyp_mode(); 1774 } 1775 1776 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1777 { 1778 /* 1779 * Copy register values that aren't redirected by hardware. 1780 * 1781 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1782 * this value to tpidr_el2 before we patch the code. Once we've done 1783 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1784 * do anything here. 1785 */ 1786 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1787 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1788 } 1789 1790 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1791 { 1792 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1793 1794 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1795 WARN_ON(CLIDR_LOUU(val) || CLIDR_LOUIS(val)); 1796 } 1797 1798 #ifdef CONFIG_ARM64_PAN 1799 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1800 { 1801 /* 1802 * We modify PSTATE. This won't work from irq context as the PSTATE 1803 * is discarded once we return from the exception. 1804 */ 1805 WARN_ON_ONCE(in_interrupt()); 1806 1807 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1808 set_pstate_pan(1); 1809 } 1810 #endif /* CONFIG_ARM64_PAN */ 1811 1812 #ifdef CONFIG_ARM64_RAS_EXTN 1813 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1814 { 1815 /* Firmware may have left a deferred SError in this register. */ 1816 write_sysreg_s(0, SYS_DISR_EL1); 1817 } 1818 #endif /* CONFIG_ARM64_RAS_EXTN */ 1819 1820 #ifdef CONFIG_ARM64_PTR_AUTH 1821 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1822 { 1823 int boot_val, sec_val; 1824 1825 /* We don't expect to be called with SCOPE_SYSTEM */ 1826 WARN_ON(scope == SCOPE_SYSTEM); 1827 /* 1828 * The ptr-auth feature levels are not intercompatible with lower 1829 * levels. Hence we must match ptr-auth feature level of the secondary 1830 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1831 * from the sanitised register whereas direct register read is done for 1832 * the secondary CPUs. 1833 * The sanitised feature state is guaranteed to match that of the 1834 * boot CPU as a mismatched secondary CPU is parked before it gets 1835 * a chance to update the state, with the capability. 1836 */ 1837 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1838 entry->field_pos, entry->sign); 1839 if (scope & SCOPE_BOOT_CPU) 1840 return boot_val >= entry->min_field_value; 1841 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 1842 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 1843 entry->field_pos, entry->sign); 1844 return sec_val == boot_val; 1845 } 1846 1847 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 1848 int scope) 1849 { 1850 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) || 1851 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 1852 } 1853 1854 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1855 int __unused) 1856 { 1857 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) || 1858 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1859 } 1860 #endif /* CONFIG_ARM64_PTR_AUTH */ 1861 1862 #ifdef CONFIG_ARM64_E0PD 1863 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1864 { 1865 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1866 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1867 } 1868 #endif /* CONFIG_ARM64_E0PD */ 1869 1870 #ifdef CONFIG_ARM64_PSEUDO_NMI 1871 static bool enable_pseudo_nmi; 1872 1873 static int __init early_enable_pseudo_nmi(char *p) 1874 { 1875 return strtobool(p, &enable_pseudo_nmi); 1876 } 1877 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1878 1879 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1880 int scope) 1881 { 1882 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1883 } 1884 #endif 1885 1886 #ifdef CONFIG_ARM64_BTI 1887 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 1888 { 1889 /* 1890 * Use of X16/X17 for tail-calls and trampolines that jump to 1891 * function entry points using BR is a requirement for 1892 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 1893 * So, be strict and forbid other BRs using other registers to 1894 * jump onto a PACIxSP instruction: 1895 */ 1896 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 1897 isb(); 1898 } 1899 #endif /* CONFIG_ARM64_BTI */ 1900 1901 #ifdef CONFIG_ARM64_MTE 1902 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 1903 { 1904 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 1905 isb(); 1906 1907 /* 1908 * Clear the tags in the zero page. This needs to be done via the 1909 * linear map which has the Tagged attribute. 1910 */ 1911 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) 1912 mte_clear_page_tags(lm_alias(empty_zero_page)); 1913 1914 kasan_init_hw_tags_cpu(); 1915 } 1916 #endif /* CONFIG_ARM64_MTE */ 1917 1918 #ifdef CONFIG_KVM 1919 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 1920 { 1921 if (kvm_get_mode() != KVM_MODE_PROTECTED) 1922 return false; 1923 1924 if (is_kernel_in_hyp_mode()) { 1925 pr_warn("Protected KVM not available with VHE\n"); 1926 return false; 1927 } 1928 1929 return true; 1930 } 1931 #endif /* CONFIG_KVM */ 1932 1933 /* Internal helper functions to match cpu capability type */ 1934 static bool 1935 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1936 { 1937 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1938 } 1939 1940 static bool 1941 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1942 { 1943 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1944 } 1945 1946 static bool 1947 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 1948 { 1949 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 1950 } 1951 1952 static const struct arm64_cpu_capabilities arm64_features[] = { 1953 { 1954 .desc = "GIC system register CPU interface", 1955 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1956 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1957 .matches = has_useable_gicv3_cpuif, 1958 .sys_reg = SYS_ID_AA64PFR0_EL1, 1959 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1960 .sign = FTR_UNSIGNED, 1961 .min_field_value = 1, 1962 }, 1963 { 1964 .desc = "Enhanced Counter Virtualization", 1965 .capability = ARM64_HAS_ECV, 1966 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1967 .matches = has_cpuid_feature, 1968 .sys_reg = SYS_ID_AA64MMFR0_EL1, 1969 .field_pos = ID_AA64MMFR0_ECV_SHIFT, 1970 .sign = FTR_UNSIGNED, 1971 .min_field_value = 1, 1972 }, 1973 #ifdef CONFIG_ARM64_PAN 1974 { 1975 .desc = "Privileged Access Never", 1976 .capability = ARM64_HAS_PAN, 1977 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1978 .matches = has_cpuid_feature, 1979 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1980 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1981 .sign = FTR_UNSIGNED, 1982 .min_field_value = 1, 1983 .cpu_enable = cpu_enable_pan, 1984 }, 1985 #endif /* CONFIG_ARM64_PAN */ 1986 #ifdef CONFIG_ARM64_EPAN 1987 { 1988 .desc = "Enhanced Privileged Access Never", 1989 .capability = ARM64_HAS_EPAN, 1990 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1991 .matches = has_cpuid_feature, 1992 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1993 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1994 .sign = FTR_UNSIGNED, 1995 .min_field_value = 3, 1996 }, 1997 #endif /* CONFIG_ARM64_EPAN */ 1998 #ifdef CONFIG_ARM64_LSE_ATOMICS 1999 { 2000 .desc = "LSE atomic instructions", 2001 .capability = ARM64_HAS_LSE_ATOMICS, 2002 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2003 .matches = has_cpuid_feature, 2004 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2005 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 2006 .sign = FTR_UNSIGNED, 2007 .min_field_value = 2, 2008 }, 2009 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2010 { 2011 .desc = "Software prefetching using PRFM", 2012 .capability = ARM64_HAS_NO_HW_PREFETCH, 2013 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2014 .matches = has_no_hw_prefetch, 2015 }, 2016 { 2017 .desc = "Virtualization Host Extensions", 2018 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2019 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2020 .matches = runs_at_el2, 2021 .cpu_enable = cpu_copy_el2regs, 2022 }, 2023 { 2024 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2025 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2026 .matches = has_32bit_el0, 2027 .sys_reg = SYS_ID_AA64PFR0_EL1, 2028 .sign = FTR_UNSIGNED, 2029 .field_pos = ID_AA64PFR0_EL0_SHIFT, 2030 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT, 2031 }, 2032 #ifdef CONFIG_KVM 2033 { 2034 .desc = "32-bit EL1 Support", 2035 .capability = ARM64_HAS_32BIT_EL1, 2036 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2037 .matches = has_cpuid_feature, 2038 .sys_reg = SYS_ID_AA64PFR0_EL1, 2039 .sign = FTR_UNSIGNED, 2040 .field_pos = ID_AA64PFR0_EL1_SHIFT, 2041 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT, 2042 }, 2043 { 2044 .desc = "Protected KVM", 2045 .capability = ARM64_KVM_PROTECTED_MODE, 2046 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2047 .matches = is_kvm_protected_mode, 2048 }, 2049 #endif 2050 { 2051 .desc = "Kernel page table isolation (KPTI)", 2052 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2053 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2054 /* 2055 * The ID feature fields below are used to indicate that 2056 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2057 * more details. 2058 */ 2059 .sys_reg = SYS_ID_AA64PFR0_EL1, 2060 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 2061 .min_field_value = 1, 2062 .matches = unmap_kernel_at_el0, 2063 .cpu_enable = kpti_install_ng_mappings, 2064 }, 2065 { 2066 /* FP/SIMD is not implemented */ 2067 .capability = ARM64_HAS_NO_FPSIMD, 2068 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2069 .min_field_value = 0, 2070 .matches = has_no_fpsimd, 2071 }, 2072 #ifdef CONFIG_ARM64_PMEM 2073 { 2074 .desc = "Data cache clean to Point of Persistence", 2075 .capability = ARM64_HAS_DCPOP, 2076 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2077 .matches = has_cpuid_feature, 2078 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2079 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 2080 .min_field_value = 1, 2081 }, 2082 { 2083 .desc = "Data cache clean to Point of Deep Persistence", 2084 .capability = ARM64_HAS_DCPODP, 2085 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2086 .matches = has_cpuid_feature, 2087 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2088 .sign = FTR_UNSIGNED, 2089 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 2090 .min_field_value = 2, 2091 }, 2092 #endif 2093 #ifdef CONFIG_ARM64_SVE 2094 { 2095 .desc = "Scalable Vector Extension", 2096 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2097 .capability = ARM64_SVE, 2098 .sys_reg = SYS_ID_AA64PFR0_EL1, 2099 .sign = FTR_UNSIGNED, 2100 .field_pos = ID_AA64PFR0_SVE_SHIFT, 2101 .min_field_value = ID_AA64PFR0_SVE, 2102 .matches = has_cpuid_feature, 2103 .cpu_enable = sve_kernel_enable, 2104 }, 2105 #endif /* CONFIG_ARM64_SVE */ 2106 #ifdef CONFIG_ARM64_RAS_EXTN 2107 { 2108 .desc = "RAS Extension Support", 2109 .capability = ARM64_HAS_RAS_EXTN, 2110 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2111 .matches = has_cpuid_feature, 2112 .sys_reg = SYS_ID_AA64PFR0_EL1, 2113 .sign = FTR_UNSIGNED, 2114 .field_pos = ID_AA64PFR0_RAS_SHIFT, 2115 .min_field_value = ID_AA64PFR0_RAS_V1, 2116 .cpu_enable = cpu_clear_disr, 2117 }, 2118 #endif /* CONFIG_ARM64_RAS_EXTN */ 2119 #ifdef CONFIG_ARM64_AMU_EXTN 2120 { 2121 /* 2122 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 2123 * Therefore, don't provide .desc as we don't want the detection 2124 * message to be shown until at least one CPU is detected to 2125 * support the feature. 2126 */ 2127 .capability = ARM64_HAS_AMU_EXTN, 2128 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2129 .matches = has_amu, 2130 .sys_reg = SYS_ID_AA64PFR0_EL1, 2131 .sign = FTR_UNSIGNED, 2132 .field_pos = ID_AA64PFR0_AMU_SHIFT, 2133 .min_field_value = ID_AA64PFR0_AMU, 2134 .cpu_enable = cpu_amu_enable, 2135 }, 2136 #endif /* CONFIG_ARM64_AMU_EXTN */ 2137 { 2138 .desc = "Data cache clean to the PoU not required for I/D coherence", 2139 .capability = ARM64_HAS_CACHE_IDC, 2140 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2141 .matches = has_cache_idc, 2142 .cpu_enable = cpu_emulate_effective_ctr, 2143 }, 2144 { 2145 .desc = "Instruction cache invalidation not required for I/D coherence", 2146 .capability = ARM64_HAS_CACHE_DIC, 2147 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2148 .matches = has_cache_dic, 2149 }, 2150 { 2151 .desc = "Stage-2 Force Write-Back", 2152 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2153 .capability = ARM64_HAS_STAGE2_FWB, 2154 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2155 .sign = FTR_UNSIGNED, 2156 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 2157 .min_field_value = 1, 2158 .matches = has_cpuid_feature, 2159 .cpu_enable = cpu_has_fwb, 2160 }, 2161 { 2162 .desc = "ARMv8.4 Translation Table Level", 2163 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2164 .capability = ARM64_HAS_ARMv8_4_TTL, 2165 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2166 .sign = FTR_UNSIGNED, 2167 .field_pos = ID_AA64MMFR2_TTL_SHIFT, 2168 .min_field_value = 1, 2169 .matches = has_cpuid_feature, 2170 }, 2171 { 2172 .desc = "TLB range maintenance instructions", 2173 .capability = ARM64_HAS_TLB_RANGE, 2174 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2175 .matches = has_cpuid_feature, 2176 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2177 .field_pos = ID_AA64ISAR0_TLB_SHIFT, 2178 .sign = FTR_UNSIGNED, 2179 .min_field_value = ID_AA64ISAR0_TLB_RANGE, 2180 }, 2181 #ifdef CONFIG_ARM64_HW_AFDBM 2182 { 2183 /* 2184 * Since we turn this on always, we don't want the user to 2185 * think that the feature is available when it may not be. 2186 * So hide the description. 2187 * 2188 * .desc = "Hardware pagetable Dirty Bit Management", 2189 * 2190 */ 2191 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2192 .capability = ARM64_HW_DBM, 2193 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2194 .sign = FTR_UNSIGNED, 2195 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 2196 .min_field_value = 2, 2197 .matches = has_hw_dbm, 2198 .cpu_enable = cpu_enable_hw_dbm, 2199 }, 2200 #endif 2201 { 2202 .desc = "CRC32 instructions", 2203 .capability = ARM64_HAS_CRC32, 2204 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2205 .matches = has_cpuid_feature, 2206 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2207 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 2208 .min_field_value = 1, 2209 }, 2210 { 2211 .desc = "Speculative Store Bypassing Safe (SSBS)", 2212 .capability = ARM64_SSBS, 2213 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2214 .matches = has_cpuid_feature, 2215 .sys_reg = SYS_ID_AA64PFR1_EL1, 2216 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 2217 .sign = FTR_UNSIGNED, 2218 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 2219 }, 2220 #ifdef CONFIG_ARM64_CNP 2221 { 2222 .desc = "Common not Private translations", 2223 .capability = ARM64_HAS_CNP, 2224 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2225 .matches = has_useable_cnp, 2226 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2227 .sign = FTR_UNSIGNED, 2228 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 2229 .min_field_value = 1, 2230 .cpu_enable = cpu_enable_cnp, 2231 }, 2232 #endif 2233 { 2234 .desc = "Speculation barrier (SB)", 2235 .capability = ARM64_HAS_SB, 2236 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2237 .matches = has_cpuid_feature, 2238 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2239 .field_pos = ID_AA64ISAR1_SB_SHIFT, 2240 .sign = FTR_UNSIGNED, 2241 .min_field_value = 1, 2242 }, 2243 #ifdef CONFIG_ARM64_PTR_AUTH 2244 { 2245 .desc = "Address authentication (architected algorithm)", 2246 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 2247 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2248 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2249 .sign = FTR_UNSIGNED, 2250 .field_pos = ID_AA64ISAR1_APA_SHIFT, 2251 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 2252 .matches = has_address_auth_cpucap, 2253 }, 2254 { 2255 .desc = "Address authentication (IMP DEF algorithm)", 2256 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2257 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2258 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2259 .sign = FTR_UNSIGNED, 2260 .field_pos = ID_AA64ISAR1_API_SHIFT, 2261 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 2262 .matches = has_address_auth_cpucap, 2263 }, 2264 { 2265 .capability = ARM64_HAS_ADDRESS_AUTH, 2266 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2267 .matches = has_address_auth_metacap, 2268 }, 2269 { 2270 .desc = "Generic authentication (architected algorithm)", 2271 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 2272 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2273 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2274 .sign = FTR_UNSIGNED, 2275 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 2276 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 2277 .matches = has_cpuid_feature, 2278 }, 2279 { 2280 .desc = "Generic authentication (IMP DEF algorithm)", 2281 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2282 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2283 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2284 .sign = FTR_UNSIGNED, 2285 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 2286 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 2287 .matches = has_cpuid_feature, 2288 }, 2289 { 2290 .capability = ARM64_HAS_GENERIC_AUTH, 2291 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2292 .matches = has_generic_auth, 2293 }, 2294 #endif /* CONFIG_ARM64_PTR_AUTH */ 2295 #ifdef CONFIG_ARM64_PSEUDO_NMI 2296 { 2297 /* 2298 * Depends on having GICv3 2299 */ 2300 .desc = "IRQ priority masking", 2301 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2302 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2303 .matches = can_use_gic_priorities, 2304 .sys_reg = SYS_ID_AA64PFR0_EL1, 2305 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2306 .sign = FTR_UNSIGNED, 2307 .min_field_value = 1, 2308 }, 2309 #endif 2310 #ifdef CONFIG_ARM64_E0PD 2311 { 2312 .desc = "E0PD", 2313 .capability = ARM64_HAS_E0PD, 2314 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2315 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2316 .sign = FTR_UNSIGNED, 2317 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2318 .matches = has_cpuid_feature, 2319 .min_field_value = 1, 2320 .cpu_enable = cpu_enable_e0pd, 2321 }, 2322 #endif 2323 #ifdef CONFIG_ARCH_RANDOM 2324 { 2325 .desc = "Random Number Generator", 2326 .capability = ARM64_HAS_RNG, 2327 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2328 .matches = has_cpuid_feature, 2329 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2330 .field_pos = ID_AA64ISAR0_RNDR_SHIFT, 2331 .sign = FTR_UNSIGNED, 2332 .min_field_value = 1, 2333 }, 2334 #endif 2335 #ifdef CONFIG_ARM64_BTI 2336 { 2337 .desc = "Branch Target Identification", 2338 .capability = ARM64_BTI, 2339 #ifdef CONFIG_ARM64_BTI_KERNEL 2340 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2341 #else 2342 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2343 #endif 2344 .matches = has_cpuid_feature, 2345 .cpu_enable = bti_enable, 2346 .sys_reg = SYS_ID_AA64PFR1_EL1, 2347 .field_pos = ID_AA64PFR1_BT_SHIFT, 2348 .min_field_value = ID_AA64PFR1_BT_BTI, 2349 .sign = FTR_UNSIGNED, 2350 }, 2351 #endif 2352 #ifdef CONFIG_ARM64_MTE 2353 { 2354 .desc = "Memory Tagging Extension", 2355 .capability = ARM64_MTE, 2356 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2357 .matches = has_cpuid_feature, 2358 .sys_reg = SYS_ID_AA64PFR1_EL1, 2359 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2360 .min_field_value = ID_AA64PFR1_MTE, 2361 .sign = FTR_UNSIGNED, 2362 .cpu_enable = cpu_enable_mte, 2363 }, 2364 { 2365 .desc = "Asymmetric MTE Tag Check Fault", 2366 .capability = ARM64_MTE_ASYMM, 2367 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2368 .matches = has_cpuid_feature, 2369 .sys_reg = SYS_ID_AA64PFR1_EL1, 2370 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2371 .min_field_value = ID_AA64PFR1_MTE_ASYMM, 2372 .sign = FTR_UNSIGNED, 2373 }, 2374 #endif /* CONFIG_ARM64_MTE */ 2375 { 2376 .desc = "RCpc load-acquire (LDAPR)", 2377 .capability = ARM64_HAS_LDAPR, 2378 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2379 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2380 .sign = FTR_UNSIGNED, 2381 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, 2382 .matches = has_cpuid_feature, 2383 .min_field_value = 1, 2384 }, 2385 {}, 2386 }; 2387 2388 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2389 .matches = has_cpuid_feature, \ 2390 .sys_reg = reg, \ 2391 .field_pos = field, \ 2392 .sign = s, \ 2393 .min_field_value = min_value, 2394 2395 #define __HWCAP_CAP(name, cap_type, cap) \ 2396 .desc = name, \ 2397 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2398 .hwcap_type = cap_type, \ 2399 .hwcap = cap, \ 2400 2401 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 2402 { \ 2403 __HWCAP_CAP(#cap, cap_type, cap) \ 2404 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2405 } 2406 2407 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2408 { \ 2409 __HWCAP_CAP(#cap, cap_type, cap) \ 2410 .matches = cpucap_multi_entry_cap_matches, \ 2411 .match_list = list, \ 2412 } 2413 2414 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2415 { \ 2416 __HWCAP_CAP(#cap, cap_type, cap) \ 2417 .matches = match, \ 2418 } 2419 2420 #ifdef CONFIG_ARM64_PTR_AUTH 2421 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2422 { 2423 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 2424 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 2425 }, 2426 { 2427 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 2428 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 2429 }, 2430 {}, 2431 }; 2432 2433 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2434 { 2435 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 2436 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 2437 }, 2438 { 2439 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 2440 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 2441 }, 2442 {}, 2443 }; 2444 #endif 2445 2446 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2447 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2448 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2449 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2450 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2451 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2452 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2453 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2454 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2455 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2456 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2457 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2458 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2459 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2460 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2461 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2462 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2463 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2464 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2465 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2466 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2467 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2468 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2469 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2470 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2471 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2472 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2473 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2474 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2475 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2476 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2477 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2478 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2479 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2480 #ifdef CONFIG_ARM64_SVE 2481 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2482 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2483 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2484 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2485 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2486 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2487 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2488 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2489 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2490 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2491 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2492 #endif 2493 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2494 #ifdef CONFIG_ARM64_BTI 2495 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2496 #endif 2497 #ifdef CONFIG_ARM64_PTR_AUTH 2498 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2499 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2500 #endif 2501 #ifdef CONFIG_ARM64_MTE 2502 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), 2503 #endif /* CONFIG_ARM64_MTE */ 2504 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), 2505 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), 2506 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2507 {}, 2508 }; 2509 2510 #ifdef CONFIG_COMPAT 2511 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2512 { 2513 /* 2514 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2515 * in line with that of arm32 as in vfp_init(). We make sure that the 2516 * check is future proof, by making sure value is non-zero. 2517 */ 2518 u32 mvfr1; 2519 2520 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2521 if (scope == SCOPE_SYSTEM) 2522 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2523 else 2524 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2525 2526 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2527 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2528 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2529 } 2530 #endif 2531 2532 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2533 #ifdef CONFIG_COMPAT 2534 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2535 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2536 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2537 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2538 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2539 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2540 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2541 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2542 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2543 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2544 #endif 2545 {}, 2546 }; 2547 2548 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2549 { 2550 switch (cap->hwcap_type) { 2551 case CAP_HWCAP: 2552 cpu_set_feature(cap->hwcap); 2553 break; 2554 #ifdef CONFIG_COMPAT 2555 case CAP_COMPAT_HWCAP: 2556 compat_elf_hwcap |= (u32)cap->hwcap; 2557 break; 2558 case CAP_COMPAT_HWCAP2: 2559 compat_elf_hwcap2 |= (u32)cap->hwcap; 2560 break; 2561 #endif 2562 default: 2563 WARN_ON(1); 2564 break; 2565 } 2566 } 2567 2568 /* Check if we have a particular HWCAP enabled */ 2569 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2570 { 2571 bool rc; 2572 2573 switch (cap->hwcap_type) { 2574 case CAP_HWCAP: 2575 rc = cpu_have_feature(cap->hwcap); 2576 break; 2577 #ifdef CONFIG_COMPAT 2578 case CAP_COMPAT_HWCAP: 2579 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2580 break; 2581 case CAP_COMPAT_HWCAP2: 2582 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2583 break; 2584 #endif 2585 default: 2586 WARN_ON(1); 2587 rc = false; 2588 } 2589 2590 return rc; 2591 } 2592 2593 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2594 { 2595 /* We support emulation of accesses to CPU ID feature registers */ 2596 cpu_set_named_feature(CPUID); 2597 for (; hwcaps->matches; hwcaps++) 2598 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2599 cap_set_elf_hwcap(hwcaps); 2600 } 2601 2602 static void update_cpu_capabilities(u16 scope_mask) 2603 { 2604 int i; 2605 const struct arm64_cpu_capabilities *caps; 2606 2607 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2608 for (i = 0; i < ARM64_NCAPS; i++) { 2609 caps = cpu_hwcaps_ptrs[i]; 2610 if (!caps || !(caps->type & scope_mask) || 2611 cpus_have_cap(caps->capability) || 2612 !caps->matches(caps, cpucap_default_scope(caps))) 2613 continue; 2614 2615 if (caps->desc) 2616 pr_info("detected: %s\n", caps->desc); 2617 cpus_set_cap(caps->capability); 2618 2619 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2620 set_bit(caps->capability, boot_capabilities); 2621 } 2622 } 2623 2624 /* 2625 * Enable all the available capabilities on this CPU. The capabilities 2626 * with BOOT_CPU scope are handled separately and hence skipped here. 2627 */ 2628 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2629 { 2630 int i; 2631 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2632 2633 for_each_available_cap(i) { 2634 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2635 2636 if (WARN_ON(!cap)) 2637 continue; 2638 2639 if (!(cap->type & non_boot_scope)) 2640 continue; 2641 2642 if (cap->cpu_enable) 2643 cap->cpu_enable(cap); 2644 } 2645 return 0; 2646 } 2647 2648 /* 2649 * Run through the enabled capabilities and enable() it on all active 2650 * CPUs 2651 */ 2652 static void __init enable_cpu_capabilities(u16 scope_mask) 2653 { 2654 int i; 2655 const struct arm64_cpu_capabilities *caps; 2656 bool boot_scope; 2657 2658 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2659 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2660 2661 for (i = 0; i < ARM64_NCAPS; i++) { 2662 unsigned int num; 2663 2664 caps = cpu_hwcaps_ptrs[i]; 2665 if (!caps || !(caps->type & scope_mask)) 2666 continue; 2667 num = caps->capability; 2668 if (!cpus_have_cap(num)) 2669 continue; 2670 2671 /* Ensure cpus_have_const_cap(num) works */ 2672 static_branch_enable(&cpu_hwcap_keys[num]); 2673 2674 if (boot_scope && caps->cpu_enable) 2675 /* 2676 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2677 * before any secondary CPU boots. Thus, each secondary 2678 * will enable the capability as appropriate via 2679 * check_local_cpu_capabilities(). The only exception is 2680 * the boot CPU, for which the capability must be 2681 * enabled here. This approach avoids costly 2682 * stop_machine() calls for this case. 2683 */ 2684 caps->cpu_enable(caps); 2685 } 2686 2687 /* 2688 * For all non-boot scope capabilities, use stop_machine() 2689 * as it schedules the work allowing us to modify PSTATE, 2690 * instead of on_each_cpu() which uses an IPI, giving us a 2691 * PSTATE that disappears when we return. 2692 */ 2693 if (!boot_scope) 2694 stop_machine(cpu_enable_non_boot_scope_capabilities, 2695 NULL, cpu_online_mask); 2696 } 2697 2698 /* 2699 * Run through the list of capabilities to check for conflicts. 2700 * If the system has already detected a capability, take necessary 2701 * action on this CPU. 2702 */ 2703 static void verify_local_cpu_caps(u16 scope_mask) 2704 { 2705 int i; 2706 bool cpu_has_cap, system_has_cap; 2707 const struct arm64_cpu_capabilities *caps; 2708 2709 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2710 2711 for (i = 0; i < ARM64_NCAPS; i++) { 2712 caps = cpu_hwcaps_ptrs[i]; 2713 if (!caps || !(caps->type & scope_mask)) 2714 continue; 2715 2716 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2717 system_has_cap = cpus_have_cap(caps->capability); 2718 2719 if (system_has_cap) { 2720 /* 2721 * Check if the new CPU misses an advertised feature, 2722 * which is not safe to miss. 2723 */ 2724 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2725 break; 2726 /* 2727 * We have to issue cpu_enable() irrespective of 2728 * whether the CPU has it or not, as it is enabeld 2729 * system wide. It is upto the call back to take 2730 * appropriate action on this CPU. 2731 */ 2732 if (caps->cpu_enable) 2733 caps->cpu_enable(caps); 2734 } else { 2735 /* 2736 * Check if the CPU has this capability if it isn't 2737 * safe to have when the system doesn't. 2738 */ 2739 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2740 break; 2741 } 2742 } 2743 2744 if (i < ARM64_NCAPS) { 2745 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2746 smp_processor_id(), caps->capability, 2747 caps->desc, system_has_cap, cpu_has_cap); 2748 2749 if (cpucap_panic_on_conflict(caps)) 2750 cpu_panic_kernel(); 2751 else 2752 cpu_die_early(); 2753 } 2754 } 2755 2756 /* 2757 * Check for CPU features that are used in early boot 2758 * based on the Boot CPU value. 2759 */ 2760 static void check_early_cpu_features(void) 2761 { 2762 verify_cpu_asid_bits(); 2763 2764 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2765 } 2766 2767 static void 2768 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2769 { 2770 2771 for (; caps->matches; caps++) 2772 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2773 pr_crit("CPU%d: missing HWCAP: %s\n", 2774 smp_processor_id(), caps->desc); 2775 cpu_die_early(); 2776 } 2777 } 2778 2779 static void verify_local_elf_hwcaps(void) 2780 { 2781 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 2782 2783 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 2784 __verify_local_elf_hwcaps(compat_elf_hwcaps); 2785 } 2786 2787 static void verify_sve_features(void) 2788 { 2789 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2790 u64 zcr = read_zcr_features(); 2791 2792 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2793 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2794 2795 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) { 2796 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2797 smp_processor_id()); 2798 cpu_die_early(); 2799 } 2800 2801 /* Add checks on other ZCR bits here if necessary */ 2802 } 2803 2804 static void verify_hyp_capabilities(void) 2805 { 2806 u64 safe_mmfr1, mmfr0, mmfr1; 2807 int parange, ipa_max; 2808 unsigned int safe_vmid_bits, vmid_bits; 2809 2810 if (!IS_ENABLED(CONFIG_KVM)) 2811 return; 2812 2813 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 2814 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 2815 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 2816 2817 /* Verify VMID bits */ 2818 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 2819 vmid_bits = get_vmid_bits(mmfr1); 2820 if (vmid_bits < safe_vmid_bits) { 2821 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 2822 cpu_die_early(); 2823 } 2824 2825 /* Verify IPA range */ 2826 parange = cpuid_feature_extract_unsigned_field(mmfr0, 2827 ID_AA64MMFR0_PARANGE_SHIFT); 2828 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 2829 if (ipa_max < get_kvm_ipa_limit()) { 2830 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 2831 cpu_die_early(); 2832 } 2833 } 2834 2835 /* 2836 * Run through the enabled system capabilities and enable() it on this CPU. 2837 * The capabilities were decided based on the available CPUs at the boot time. 2838 * Any new CPU should match the system wide status of the capability. If the 2839 * new CPU doesn't have a capability which the system now has enabled, we 2840 * cannot do anything to fix it up and could cause unexpected failures. So 2841 * we park the CPU. 2842 */ 2843 static void verify_local_cpu_capabilities(void) 2844 { 2845 /* 2846 * The capabilities with SCOPE_BOOT_CPU are checked from 2847 * check_early_cpu_features(), as they need to be verified 2848 * on all secondary CPUs. 2849 */ 2850 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2851 verify_local_elf_hwcaps(); 2852 2853 if (system_supports_sve()) 2854 verify_sve_features(); 2855 2856 if (is_hyp_mode_available()) 2857 verify_hyp_capabilities(); 2858 } 2859 2860 void check_local_cpu_capabilities(void) 2861 { 2862 /* 2863 * All secondary CPUs should conform to the early CPU features 2864 * in use by the kernel based on boot CPU. 2865 */ 2866 check_early_cpu_features(); 2867 2868 /* 2869 * If we haven't finalised the system capabilities, this CPU gets 2870 * a chance to update the errata work arounds and local features. 2871 * Otherwise, this CPU should verify that it has all the system 2872 * advertised capabilities. 2873 */ 2874 if (!system_capabilities_finalized()) 2875 update_cpu_capabilities(SCOPE_LOCAL_CPU); 2876 else 2877 verify_local_cpu_capabilities(); 2878 } 2879 2880 static void __init setup_boot_cpu_capabilities(void) 2881 { 2882 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 2883 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 2884 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 2885 enable_cpu_capabilities(SCOPE_BOOT_CPU); 2886 } 2887 2888 bool this_cpu_has_cap(unsigned int n) 2889 { 2890 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 2891 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2892 2893 if (cap) 2894 return cap->matches(cap, SCOPE_LOCAL_CPU); 2895 } 2896 2897 return false; 2898 } 2899 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 2900 2901 /* 2902 * This helper function is used in a narrow window when, 2903 * - The system wide safe registers are set with all the SMP CPUs and, 2904 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 2905 * In all other cases cpus_have_{const_}cap() should be used. 2906 */ 2907 static bool __maybe_unused __system_matches_cap(unsigned int n) 2908 { 2909 if (n < ARM64_NCAPS) { 2910 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2911 2912 if (cap) 2913 return cap->matches(cap, SCOPE_SYSTEM); 2914 } 2915 return false; 2916 } 2917 2918 void cpu_set_feature(unsigned int num) 2919 { 2920 WARN_ON(num >= MAX_CPU_FEATURES); 2921 elf_hwcap |= BIT(num); 2922 } 2923 EXPORT_SYMBOL_GPL(cpu_set_feature); 2924 2925 bool cpu_have_feature(unsigned int num) 2926 { 2927 WARN_ON(num >= MAX_CPU_FEATURES); 2928 return elf_hwcap & BIT(num); 2929 } 2930 EXPORT_SYMBOL_GPL(cpu_have_feature); 2931 2932 unsigned long cpu_get_elf_hwcap(void) 2933 { 2934 /* 2935 * We currently only populate the first 32 bits of AT_HWCAP. Please 2936 * note that for userspace compatibility we guarantee that bits 62 2937 * and 63 will always be returned as 0. 2938 */ 2939 return lower_32_bits(elf_hwcap); 2940 } 2941 2942 unsigned long cpu_get_elf_hwcap2(void) 2943 { 2944 return upper_32_bits(elf_hwcap); 2945 } 2946 2947 static void __init setup_system_capabilities(void) 2948 { 2949 /* 2950 * We have finalised the system-wide safe feature 2951 * registers, finalise the capabilities that depend 2952 * on it. Also enable all the available capabilities, 2953 * that are not enabled already. 2954 */ 2955 update_cpu_capabilities(SCOPE_SYSTEM); 2956 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2957 } 2958 2959 void __init setup_cpu_features(void) 2960 { 2961 u32 cwg; 2962 2963 setup_system_capabilities(); 2964 setup_elf_hwcaps(arm64_elf_hwcaps); 2965 2966 if (system_supports_32bit_el0()) 2967 setup_elf_hwcaps(compat_elf_hwcaps); 2968 2969 if (system_uses_ttbr0_pan()) 2970 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2971 2972 sve_setup(); 2973 minsigstksz_setup(); 2974 2975 /* Advertise that we have computed the system capabilities */ 2976 finalize_system_capabilities(); 2977 2978 /* 2979 * Check for sane CTR_EL0.CWG value. 2980 */ 2981 cwg = cache_type_cwg(); 2982 if (!cwg) 2983 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2984 ARCH_DMA_MINALIGN); 2985 } 2986 2987 static int enable_mismatched_32bit_el0(unsigned int cpu) 2988 { 2989 /* 2990 * The first 32-bit-capable CPU we detected and so can no longer 2991 * be offlined by userspace. -1 indicates we haven't yet onlined 2992 * a 32-bit-capable CPU. 2993 */ 2994 static int lucky_winner = -1; 2995 2996 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 2997 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 2998 2999 if (cpu_32bit) { 3000 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3001 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3002 } 3003 3004 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3005 return 0; 3006 3007 if (lucky_winner >= 0) 3008 return 0; 3009 3010 /* 3011 * We've detected a mismatch. We need to keep one of our CPUs with 3012 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3013 * every CPU in the system for a 32-bit task. 3014 */ 3015 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3016 cpu_active_mask); 3017 get_cpu_device(lucky_winner)->offline_disabled = true; 3018 setup_elf_hwcaps(compat_elf_hwcaps); 3019 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3020 cpu, lucky_winner); 3021 return 0; 3022 } 3023 3024 static int __init init_32bit_el0_mask(void) 3025 { 3026 if (!allow_mismatched_32bit_el0) 3027 return 0; 3028 3029 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3030 return -ENOMEM; 3031 3032 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3033 "arm64/mismatched_32bit_el0:online", 3034 enable_mismatched_32bit_el0, NULL); 3035 } 3036 subsys_initcall_sync(init_32bit_el0_mask); 3037 3038 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3039 { 3040 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 3041 } 3042 3043 /* 3044 * We emulate only the following system register space. 3045 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 3046 * See Table C5-6 System instruction encodings for System register accesses, 3047 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3048 */ 3049 static inline bool __attribute_const__ is_emulated(u32 id) 3050 { 3051 return (sys_reg_Op0(id) == 0x3 && 3052 sys_reg_CRn(id) == 0x0 && 3053 sys_reg_Op1(id) == 0x0 && 3054 (sys_reg_CRm(id) == 0 || 3055 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 3056 } 3057 3058 /* 3059 * With CRm == 0, reg should be one of : 3060 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3061 */ 3062 static inline int emulate_id_reg(u32 id, u64 *valp) 3063 { 3064 switch (id) { 3065 case SYS_MIDR_EL1: 3066 *valp = read_cpuid_id(); 3067 break; 3068 case SYS_MPIDR_EL1: 3069 *valp = SYS_MPIDR_SAFE_VAL; 3070 break; 3071 case SYS_REVIDR_EL1: 3072 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3073 *valp = 0; 3074 break; 3075 default: 3076 return -EINVAL; 3077 } 3078 3079 return 0; 3080 } 3081 3082 static int emulate_sys_reg(u32 id, u64 *valp) 3083 { 3084 struct arm64_ftr_reg *regp; 3085 3086 if (!is_emulated(id)) 3087 return -EINVAL; 3088 3089 if (sys_reg_CRm(id) == 0) 3090 return emulate_id_reg(id, valp); 3091 3092 regp = get_arm64_ftr_reg_nowarn(id); 3093 if (regp) 3094 *valp = arm64_ftr_reg_user_value(regp); 3095 else 3096 /* 3097 * The untracked registers are either IMPLEMENTATION DEFINED 3098 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3099 */ 3100 *valp = 0; 3101 return 0; 3102 } 3103 3104 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3105 { 3106 int rc; 3107 u64 val; 3108 3109 rc = emulate_sys_reg(sys_reg, &val); 3110 if (!rc) { 3111 pt_regs_write_reg(regs, rt, val); 3112 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3113 } 3114 return rc; 3115 } 3116 3117 static int emulate_mrs(struct pt_regs *regs, u32 insn) 3118 { 3119 u32 sys_reg, rt; 3120 3121 /* 3122 * sys_reg values are defined as used in mrs/msr instruction. 3123 * shift the imm value to get the encoding. 3124 */ 3125 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3126 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3127 return do_emulate_mrs(regs, sys_reg, rt); 3128 } 3129 3130 static struct undef_hook mrs_hook = { 3131 .instr_mask = 0xffff0000, 3132 .instr_val = 0xd5380000, 3133 .pstate_mask = PSR_AA32_MODE_MASK, 3134 .pstate_val = PSR_MODE_EL0t, 3135 .fn = emulate_mrs, 3136 }; 3137 3138 static int __init enable_mrs_emulation(void) 3139 { 3140 register_undef_hook(&mrs_hook); 3141 return 0; 3142 } 3143 3144 core_initcall(enable_mrs_emulation); 3145 3146 enum mitigation_state arm64_get_meltdown_state(void) 3147 { 3148 if (__meltdown_safe) 3149 return SPECTRE_UNAFFECTED; 3150 3151 if (arm64_kernel_unmapped_at_el0()) 3152 return SPECTRE_MITIGATED; 3153 3154 return SPECTRE_VULNERABLE; 3155 } 3156 3157 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3158 char *buf) 3159 { 3160 switch (arm64_get_meltdown_state()) { 3161 case SPECTRE_UNAFFECTED: 3162 return sprintf(buf, "Not affected\n"); 3163 3164 case SPECTRE_MITIGATED: 3165 return sprintf(buf, "Mitigation: PTI\n"); 3166 3167 default: 3168 return sprintf(buf, "Vulnerable\n"); 3169 } 3170 } 3171