1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 79 #include <asm/cpu.h> 80 #include <asm/cpufeature.h> 81 #include <asm/cpu_ops.h> 82 #include <asm/fpsimd.h> 83 #include <asm/hwcap.h> 84 #include <asm/insn.h> 85 #include <asm/kvm_host.h> 86 #include <asm/mmu_context.h> 87 #include <asm/mte.h> 88 #include <asm/processor.h> 89 #include <asm/smp.h> 90 #include <asm/sysreg.h> 91 #include <asm/traps.h> 92 #include <asm/vectors.h> 93 #include <asm/virt.h> 94 95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 97 98 #ifdef CONFIG_COMPAT 99 #define COMPAT_ELF_HWCAP_DEFAULT \ 100 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 101 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 102 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 103 COMPAT_HWCAP_LPAE) 104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 105 unsigned int compat_elf_hwcap2 __read_mostly; 106 #endif 107 108 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 109 EXPORT_SYMBOL(system_cpucaps); 110 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 111 112 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 113 114 bool arm64_use_ng_mappings = false; 115 EXPORT_SYMBOL(arm64_use_ng_mappings); 116 117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 118 119 /* 120 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 121 * support it? 122 */ 123 static bool __read_mostly allow_mismatched_32bit_el0; 124 125 /* 126 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 127 * seen at least one CPU capable of 32-bit EL0. 128 */ 129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 130 131 /* 132 * Mask of CPUs supporting 32-bit EL0. 133 * Only valid if arm64_mismatched_32bit_el0 is enabled. 134 */ 135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 136 137 void dump_cpu_features(void) 138 { 139 /* file-wide pr_fmt adds "CPU features: " prefix */ 140 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 141 } 142 143 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 144 .sys_reg = SYS_##reg, \ 145 .field_pos = reg##_##field##_SHIFT, \ 146 .field_width = reg##_##field##_WIDTH, \ 147 .sign = reg##_##field##_SIGNED, \ 148 .min_field_value = reg##_##field##_##min_value, 149 150 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 151 { \ 152 .sign = SIGNED, \ 153 .visible = VISIBLE, \ 154 .strict = STRICT, \ 155 .type = TYPE, \ 156 .shift = SHIFT, \ 157 .width = WIDTH, \ 158 .safe_val = SAFE_VAL, \ 159 } 160 161 /* Define a feature with unsigned values */ 162 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 163 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 164 165 /* Define a feature with a signed value */ 166 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 167 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 168 169 #define ARM64_FTR_END \ 170 { \ 171 .width = 0, \ 172 } 173 174 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 175 176 static bool __system_matches_cap(unsigned int n); 177 178 /* 179 * NOTE: Any changes to the visibility of features should be kept in 180 * sync with the documentation of the CPU feature register ABI. 181 */ 182 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 184 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 197 ARM64_FTR_END, 198 }; 199 200 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 208 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 210 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 215 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 217 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 219 ARM64_FTR_END, 220 }; 221 222 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 228 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 230 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 233 ARM64_FTR_END, 234 }; 235 236 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 244 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 247 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 248 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 253 ARM64_FTR_END, 254 }; 255 256 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 257 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 258 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 262 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 263 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 266 ARM64_FTR_END, 267 }; 268 269 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 271 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 275 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 276 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 277 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 278 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 279 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 280 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 281 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 282 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 283 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 284 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 285 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 286 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 287 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 288 ARM64_FTR_END, 289 }; 290 291 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 292 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 293 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 294 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 295 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 297 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 299 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 300 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 301 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 303 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 304 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 305 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 306 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 307 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 308 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 309 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 310 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 311 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 312 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 313 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 314 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 315 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 316 ARM64_FTR_END, 317 }; 318 319 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 320 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 323 /* 324 * Page size not being supported at Stage-2 is not fatal. You 325 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 326 * your favourite nesting hypervisor. 327 * 328 * There is a small corner case where the hypervisor explicitly 329 * advertises a given granule size at Stage-2 (value 2) on some 330 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 331 * vCPUs. Although this is not forbidden by the architecture, it 332 * indicates that the hypervisor is being silly (or buggy). 333 * 334 * We make no effort to cope with this and pretend that if these 335 * fields are inconsistent across vCPUs, then it isn't worth 336 * trying to bring KVM up. 337 */ 338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 339 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 341 /* 342 * We already refuse to boot CPUs that don't support our configured 343 * page size, so we can only detect mismatches for a page size other 344 * than the one we're currently using. Unfortunately, SoCs like this 345 * exist in the wild so, even though we don't like it, we'll have to go 346 * along with it and treat them as non-strict. 347 */ 348 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 349 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 351 352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 353 /* Linux shouldn't care about secure memory */ 354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 357 /* 358 * Differing PARange is fine as long as all peripherals and memory are mapped 359 * within the minimum PARange of all CPUs 360 */ 361 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 362 ARM64_FTR_END, 363 }; 364 365 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 379 ARM64_FTR_END, 380 }; 381 382 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 383 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 384 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 385 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 389 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 394 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 395 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 396 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 397 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 398 ARM64_FTR_END, 399 }; 400 401 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 403 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 404 ARM64_FTR_END, 405 }; 406 407 static const struct arm64_ftr_bits ftr_ctr[] = { 408 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 409 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 410 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 413 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 414 /* 415 * Linux can handle differing I-cache policies. Userspace JITs will 416 * make use of *minLine. 417 * If we have differing I-cache policies, report it as the weakest - VIPT. 418 */ 419 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 420 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 421 ARM64_FTR_END, 422 }; 423 424 static struct arm64_ftr_override __ro_after_init no_override = { }; 425 426 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 427 .name = "SYS_CTR_EL0", 428 .ftr_bits = ftr_ctr, 429 .override = &no_override, 430 }; 431 432 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 433 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 438 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 441 ARM64_FTR_END, 442 }; 443 444 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 445 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 450 /* 451 * We can instantiate multiple PMU instances with different levels 452 * of support. 453 */ 454 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 456 ARM64_FTR_END, 457 }; 458 459 static const struct arm64_ftr_bits ftr_mvfr0[] = { 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 468 ARM64_FTR_END, 469 }; 470 471 static const struct arm64_ftr_bits ftr_mvfr1[] = { 472 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 480 ARM64_FTR_END, 481 }; 482 483 static const struct arm64_ftr_bits ftr_mvfr2[] = { 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 486 ARM64_FTR_END, 487 }; 488 489 static const struct arm64_ftr_bits ftr_dczid[] = { 490 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 491 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 492 ARM64_FTR_END, 493 }; 494 495 static const struct arm64_ftr_bits ftr_gmid[] = { 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 497 ARM64_FTR_END, 498 }; 499 500 static const struct arm64_ftr_bits ftr_id_isar0[] = { 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 508 ARM64_FTR_END, 509 }; 510 511 static const struct arm64_ftr_bits ftr_id_isar5[] = { 512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 513 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 514 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 516 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 518 ARM64_FTR_END, 519 }; 520 521 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 522 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 523 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 524 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 529 530 /* 531 * SpecSEI = 1 indicates that the PE might generate an SError on an 532 * external abort on speculative read. It is safe to assume that an 533 * SError might be generated than it will not be. Hence it has been 534 * classified as FTR_HIGHER_SAFE. 535 */ 536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 537 ARM64_FTR_END, 538 }; 539 540 static const struct arm64_ftr_bits ftr_id_isar4[] = { 541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 549 ARM64_FTR_END, 550 }; 551 552 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 554 ARM64_FTR_END, 555 }; 556 557 static const struct arm64_ftr_bits ftr_id_isar6[] = { 558 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 561 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 563 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 564 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 565 ARM64_FTR_END, 566 }; 567 568 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 575 ARM64_FTR_END, 576 }; 577 578 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 581 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 587 ARM64_FTR_END, 588 }; 589 590 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 591 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 592 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 593 ARM64_FTR_END, 594 }; 595 596 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 597 /* [31:28] TraceFilt */ 598 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 599 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 605 ARM64_FTR_END, 606 }; 607 608 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 609 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 610 ARM64_FTR_END, 611 }; 612 613 static const struct arm64_ftr_bits ftr_zcr[] = { 614 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 615 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0), /* LEN */ 616 ARM64_FTR_END, 617 }; 618 619 static const struct arm64_ftr_bits ftr_smcr[] = { 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 621 SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0), /* LEN */ 622 ARM64_FTR_END, 623 }; 624 625 /* 626 * Common ftr bits for a 32bit register with all hidden, strict 627 * attributes, with 4bit feature fields and a default safe value of 628 * 0. Covers the following 32bit registers: 629 * id_isar[1-3], id_mmfr[1-3] 630 */ 631 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 632 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 633 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 634 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 635 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 637 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 639 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 640 ARM64_FTR_END, 641 }; 642 643 /* Table for a single 32bit feature value */ 644 static const struct arm64_ftr_bits ftr_single32[] = { 645 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 646 ARM64_FTR_END, 647 }; 648 649 static const struct arm64_ftr_bits ftr_raz[] = { 650 ARM64_FTR_END, 651 }; 652 653 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 654 .sys_id = id, \ 655 .reg = &(struct arm64_ftr_reg){ \ 656 .name = id_str, \ 657 .override = (ovr), \ 658 .ftr_bits = &((table)[0]), \ 659 }} 660 661 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 662 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 663 664 #define ARM64_FTR_REG(id, table) \ 665 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 666 667 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 668 struct arm64_ftr_override __ro_after_init id_aa64pfr0_override; 669 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 670 struct arm64_ftr_override __ro_after_init id_aa64zfr0_override; 671 struct arm64_ftr_override __ro_after_init id_aa64smfr0_override; 672 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 673 struct arm64_ftr_override __ro_after_init id_aa64isar2_override; 674 675 static const struct __ftr_reg_entry { 676 u32 sys_id; 677 struct arm64_ftr_reg *reg; 678 } arm64_ftr_regs[] = { 679 680 /* Op1 = 0, CRn = 0, CRm = 1 */ 681 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 682 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 683 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 684 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 685 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 686 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 687 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 688 689 /* Op1 = 0, CRn = 0, CRm = 2 */ 690 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 691 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 692 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 693 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 694 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 695 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 696 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 697 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 698 699 /* Op1 = 0, CRn = 0, CRm = 3 */ 700 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 701 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 702 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 703 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 704 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 705 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 706 707 /* Op1 = 0, CRn = 0, CRm = 4 */ 708 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 709 &id_aa64pfr0_override), 710 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 711 &id_aa64pfr1_override), 712 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 713 &id_aa64zfr0_override), 714 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 715 &id_aa64smfr0_override), 716 717 /* Op1 = 0, CRn = 0, CRm = 5 */ 718 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 719 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 720 721 /* Op1 = 0, CRn = 0, CRm = 6 */ 722 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 723 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 724 &id_aa64isar1_override), 725 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 726 &id_aa64isar2_override), 727 728 /* Op1 = 0, CRn = 0, CRm = 7 */ 729 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 730 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 731 &id_aa64mmfr1_override), 732 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 733 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 734 735 /* Op1 = 0, CRn = 1, CRm = 2 */ 736 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 737 ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr), 738 739 /* Op1 = 1, CRn = 0, CRm = 0 */ 740 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 741 742 /* Op1 = 3, CRn = 0, CRm = 0 */ 743 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 744 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 745 746 /* Op1 = 3, CRn = 14, CRm = 0 */ 747 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 748 }; 749 750 static int search_cmp_ftr_reg(const void *id, const void *regp) 751 { 752 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 753 } 754 755 /* 756 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 757 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 758 * ascending order of sys_id, we use binary search to find a matching 759 * entry. 760 * 761 * returns - Upon success, matching ftr_reg entry for id. 762 * - NULL on failure. It is upto the caller to decide 763 * the impact of a failure. 764 */ 765 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 766 { 767 const struct __ftr_reg_entry *ret; 768 769 ret = bsearch((const void *)(unsigned long)sys_id, 770 arm64_ftr_regs, 771 ARRAY_SIZE(arm64_ftr_regs), 772 sizeof(arm64_ftr_regs[0]), 773 search_cmp_ftr_reg); 774 if (ret) 775 return ret->reg; 776 return NULL; 777 } 778 779 /* 780 * get_arm64_ftr_reg - Looks up a feature register entry using 781 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 782 * 783 * returns - Upon success, matching ftr_reg entry for id. 784 * - NULL on failure but with an WARN_ON(). 785 */ 786 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 787 { 788 struct arm64_ftr_reg *reg; 789 790 reg = get_arm64_ftr_reg_nowarn(sys_id); 791 792 /* 793 * Requesting a non-existent register search is an error. Warn 794 * and let the caller handle it. 795 */ 796 WARN_ON(!reg); 797 return reg; 798 } 799 800 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 801 s64 ftr_val) 802 { 803 u64 mask = arm64_ftr_mask(ftrp); 804 805 reg &= ~mask; 806 reg |= (ftr_val << ftrp->shift) & mask; 807 return reg; 808 } 809 810 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 811 s64 cur) 812 { 813 s64 ret = 0; 814 815 switch (ftrp->type) { 816 case FTR_EXACT: 817 ret = ftrp->safe_val; 818 break; 819 case FTR_LOWER_SAFE: 820 ret = min(new, cur); 821 break; 822 case FTR_HIGHER_OR_ZERO_SAFE: 823 if (!cur || !new) 824 break; 825 fallthrough; 826 case FTR_HIGHER_SAFE: 827 ret = max(new, cur); 828 break; 829 default: 830 BUG(); 831 } 832 833 return ret; 834 } 835 836 static void __init sort_ftr_regs(void) 837 { 838 unsigned int i; 839 840 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 841 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 842 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 843 unsigned int j = 0; 844 845 /* 846 * Features here must be sorted in descending order with respect 847 * to their shift values and should not overlap with each other. 848 */ 849 for (; ftr_bits->width != 0; ftr_bits++, j++) { 850 unsigned int width = ftr_reg->ftr_bits[j].width; 851 unsigned int shift = ftr_reg->ftr_bits[j].shift; 852 unsigned int prev_shift; 853 854 WARN((shift + width) > 64, 855 "%s has invalid feature at shift %d\n", 856 ftr_reg->name, shift); 857 858 /* 859 * Skip the first feature. There is nothing to 860 * compare against for now. 861 */ 862 if (j == 0) 863 continue; 864 865 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 866 WARN((shift + width) > prev_shift, 867 "%s has feature overlap at shift %d\n", 868 ftr_reg->name, shift); 869 } 870 871 /* 872 * Skip the first register. There is nothing to 873 * compare against for now. 874 */ 875 if (i == 0) 876 continue; 877 /* 878 * Registers here must be sorted in ascending order with respect 879 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 880 * to work correctly. 881 */ 882 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 883 } 884 } 885 886 /* 887 * Initialise the CPU feature register from Boot CPU values. 888 * Also initiliases the strict_mask for the register. 889 * Any bits that are not covered by an arm64_ftr_bits entry are considered 890 * RES0 for the system-wide value, and must strictly match. 891 */ 892 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 893 { 894 u64 val = 0; 895 u64 strict_mask = ~0x0ULL; 896 u64 user_mask = 0; 897 u64 valid_mask = 0; 898 899 const struct arm64_ftr_bits *ftrp; 900 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 901 902 if (!reg) 903 return; 904 905 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 906 u64 ftr_mask = arm64_ftr_mask(ftrp); 907 s64 ftr_new = arm64_ftr_value(ftrp, new); 908 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 909 910 if ((ftr_mask & reg->override->mask) == ftr_mask) { 911 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 912 char *str = NULL; 913 914 if (ftr_ovr != tmp) { 915 /* Unsafe, remove the override */ 916 reg->override->mask &= ~ftr_mask; 917 reg->override->val &= ~ftr_mask; 918 tmp = ftr_ovr; 919 str = "ignoring override"; 920 } else if (ftr_new != tmp) { 921 /* Override was valid */ 922 ftr_new = tmp; 923 str = "forced"; 924 } else if (ftr_ovr == tmp) { 925 /* Override was the safe value */ 926 str = "already set"; 927 } 928 929 if (str) 930 pr_warn("%s[%d:%d]: %s to %llx\n", 931 reg->name, 932 ftrp->shift + ftrp->width - 1, 933 ftrp->shift, str, tmp); 934 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 935 reg->override->val &= ~ftr_mask; 936 pr_warn("%s[%d:%d]: impossible override, ignored\n", 937 reg->name, 938 ftrp->shift + ftrp->width - 1, 939 ftrp->shift); 940 } 941 942 val = arm64_ftr_set_value(ftrp, val, ftr_new); 943 944 valid_mask |= ftr_mask; 945 if (!ftrp->strict) 946 strict_mask &= ~ftr_mask; 947 if (ftrp->visible) 948 user_mask |= ftr_mask; 949 else 950 reg->user_val = arm64_ftr_set_value(ftrp, 951 reg->user_val, 952 ftrp->safe_val); 953 } 954 955 val &= valid_mask; 956 957 reg->sys_val = val; 958 reg->strict_mask = strict_mask; 959 reg->user_mask = user_mask; 960 } 961 962 extern const struct arm64_cpu_capabilities arm64_errata[]; 963 static const struct arm64_cpu_capabilities arm64_features[]; 964 965 static void __init 966 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 967 { 968 for (; caps->matches; caps++) { 969 if (WARN(caps->capability >= ARM64_NCAPS, 970 "Invalid capability %d\n", caps->capability)) 971 continue; 972 if (WARN(cpucap_ptrs[caps->capability], 973 "Duplicate entry for capability %d\n", 974 caps->capability)) 975 continue; 976 cpucap_ptrs[caps->capability] = caps; 977 } 978 } 979 980 static void __init init_cpucap_indirect_list(void) 981 { 982 init_cpucap_indirect_list_from_array(arm64_features); 983 init_cpucap_indirect_list_from_array(arm64_errata); 984 } 985 986 static void __init setup_boot_cpu_capabilities(void); 987 988 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 989 { 990 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 991 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 992 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 993 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 994 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 995 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 996 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 997 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 998 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 999 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1000 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1001 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1002 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1003 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1004 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1005 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1006 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1007 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1008 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1009 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1010 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1011 } 1012 1013 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1014 { 1015 /* Before we start using the tables, make sure it is sorted */ 1016 sort_ftr_regs(); 1017 1018 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1019 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1020 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1021 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1022 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1023 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1024 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1025 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1026 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1027 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1028 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1029 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1030 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1031 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1032 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1033 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1034 1035 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1036 init_32bit_cpu_features(&info->aarch32); 1037 1038 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1039 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1040 info->reg_zcr = read_zcr_features(); 1041 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 1042 vec_init_vq_map(ARM64_VEC_SVE); 1043 } 1044 1045 if (IS_ENABLED(CONFIG_ARM64_SME) && 1046 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1047 info->reg_smcr = read_smcr_features(); 1048 /* 1049 * We mask out SMPS since even if the hardware 1050 * supports priorities the kernel does not at present 1051 * and we block access to them. 1052 */ 1053 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1054 init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr); 1055 vec_init_vq_map(ARM64_VEC_SME); 1056 } 1057 1058 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1059 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1060 1061 /* 1062 * Initialize the indirect array of CPU capabilities pointers before we 1063 * handle the boot CPU below. 1064 */ 1065 init_cpucap_indirect_list(); 1066 1067 /* 1068 * Detect and enable early CPU capabilities based on the boot CPU, 1069 * after we have initialised the CPU feature infrastructure. 1070 */ 1071 setup_boot_cpu_capabilities(); 1072 } 1073 1074 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1075 { 1076 const struct arm64_ftr_bits *ftrp; 1077 1078 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1079 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1080 s64 ftr_new = arm64_ftr_value(ftrp, new); 1081 1082 if (ftr_cur == ftr_new) 1083 continue; 1084 /* Find a safe value */ 1085 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1086 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1087 } 1088 1089 } 1090 1091 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1092 { 1093 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1094 1095 if (!regp) 1096 return 0; 1097 1098 update_cpu_ftr_reg(regp, val); 1099 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1100 return 0; 1101 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1102 regp->name, boot, cpu, val); 1103 return 1; 1104 } 1105 1106 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1107 { 1108 const struct arm64_ftr_bits *ftrp; 1109 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1110 1111 if (!regp) 1112 return; 1113 1114 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1115 if (ftrp->shift == field) { 1116 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1117 break; 1118 } 1119 } 1120 1121 /* Bogus field? */ 1122 WARN_ON(!ftrp->width); 1123 } 1124 1125 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1126 struct cpuinfo_arm64 *boot) 1127 { 1128 static bool boot_cpu_32bit_regs_overridden = false; 1129 1130 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1131 return; 1132 1133 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1134 return; 1135 1136 boot->aarch32 = info->aarch32; 1137 init_32bit_cpu_features(&boot->aarch32); 1138 boot_cpu_32bit_regs_overridden = true; 1139 } 1140 1141 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1142 struct cpuinfo_32bit *boot) 1143 { 1144 int taint = 0; 1145 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1146 1147 /* 1148 * If we don't have AArch32 at EL1, then relax the strictness of 1149 * EL1-dependent register fields to avoid spurious sanity check fails. 1150 */ 1151 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1152 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1153 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1154 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1155 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1156 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1157 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1158 } 1159 1160 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1161 info->reg_id_dfr0, boot->reg_id_dfr0); 1162 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1163 info->reg_id_dfr1, boot->reg_id_dfr1); 1164 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1165 info->reg_id_isar0, boot->reg_id_isar0); 1166 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1167 info->reg_id_isar1, boot->reg_id_isar1); 1168 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1169 info->reg_id_isar2, boot->reg_id_isar2); 1170 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1171 info->reg_id_isar3, boot->reg_id_isar3); 1172 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1173 info->reg_id_isar4, boot->reg_id_isar4); 1174 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1175 info->reg_id_isar5, boot->reg_id_isar5); 1176 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1177 info->reg_id_isar6, boot->reg_id_isar6); 1178 1179 /* 1180 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1181 * ACTLR formats could differ across CPUs and therefore would have to 1182 * be trapped for virtualization anyway. 1183 */ 1184 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1185 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1186 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1187 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1188 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1189 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1190 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1191 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1192 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1193 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1194 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1195 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1196 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1197 info->reg_id_pfr0, boot->reg_id_pfr0); 1198 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1199 info->reg_id_pfr1, boot->reg_id_pfr1); 1200 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1201 info->reg_id_pfr2, boot->reg_id_pfr2); 1202 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1203 info->reg_mvfr0, boot->reg_mvfr0); 1204 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1205 info->reg_mvfr1, boot->reg_mvfr1); 1206 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1207 info->reg_mvfr2, boot->reg_mvfr2); 1208 1209 return taint; 1210 } 1211 1212 /* 1213 * Update system wide CPU feature registers with the values from a 1214 * non-boot CPU. Also performs SANITY checks to make sure that there 1215 * aren't any insane variations from that of the boot CPU. 1216 */ 1217 void update_cpu_features(int cpu, 1218 struct cpuinfo_arm64 *info, 1219 struct cpuinfo_arm64 *boot) 1220 { 1221 int taint = 0; 1222 1223 /* 1224 * The kernel can handle differing I-cache policies, but otherwise 1225 * caches should look identical. Userspace JITs will make use of 1226 * *minLine. 1227 */ 1228 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1229 info->reg_ctr, boot->reg_ctr); 1230 1231 /* 1232 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1233 * could result in too much or too little memory being zeroed if a 1234 * process is preempted and migrated between CPUs. 1235 */ 1236 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1237 info->reg_dczid, boot->reg_dczid); 1238 1239 /* If different, timekeeping will be broken (especially with KVM) */ 1240 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1241 info->reg_cntfrq, boot->reg_cntfrq); 1242 1243 /* 1244 * The kernel uses self-hosted debug features and expects CPUs to 1245 * support identical debug features. We presently need CTX_CMPs, WRPs, 1246 * and BRPs to be identical. 1247 * ID_AA64DFR1 is currently RES0. 1248 */ 1249 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1250 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1251 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1252 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1253 /* 1254 * Even in big.LITTLE, processors should be identical instruction-set 1255 * wise. 1256 */ 1257 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1258 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1259 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1260 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1261 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1262 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1263 1264 /* 1265 * Differing PARange support is fine as long as all peripherals and 1266 * memory are mapped within the minimum PARange of all CPUs. 1267 * Linux should not care about secure memory. 1268 */ 1269 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1270 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1271 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1272 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1273 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1274 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1275 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1276 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1277 1278 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1279 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1280 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1281 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1282 1283 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1284 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1285 1286 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1287 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1288 1289 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1290 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1291 info->reg_zcr = read_zcr_features(); 1292 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1293 info->reg_zcr, boot->reg_zcr); 1294 1295 /* Probe vector lengths */ 1296 if (!system_capabilities_finalized()) 1297 vec_update_vq_map(ARM64_VEC_SVE); 1298 } 1299 1300 if (IS_ENABLED(CONFIG_ARM64_SME) && 1301 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1302 info->reg_smcr = read_smcr_features(); 1303 /* 1304 * We mask out SMPS since even if the hardware 1305 * supports priorities the kernel does not at present 1306 * and we block access to them. 1307 */ 1308 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1309 taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu, 1310 info->reg_smcr, boot->reg_smcr); 1311 1312 /* Probe vector lengths */ 1313 if (!system_capabilities_finalized()) 1314 vec_update_vq_map(ARM64_VEC_SME); 1315 } 1316 1317 /* 1318 * The kernel uses the LDGM/STGM instructions and the number of tags 1319 * they read/write depends on the GMID_EL1.BS field. Check that the 1320 * value is the same on all CPUs. 1321 */ 1322 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1323 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1324 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1325 info->reg_gmid, boot->reg_gmid); 1326 } 1327 1328 /* 1329 * If we don't have AArch32 at all then skip the checks entirely 1330 * as the register values may be UNKNOWN and we're not going to be 1331 * using them for anything. 1332 * 1333 * This relies on a sanitised view of the AArch64 ID registers 1334 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1335 */ 1336 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1337 lazy_init_32bit_cpu_features(info, boot); 1338 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1339 &boot->aarch32); 1340 } 1341 1342 /* 1343 * Mismatched CPU features are a recipe for disaster. Don't even 1344 * pretend to support them. 1345 */ 1346 if (taint) { 1347 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1348 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1349 } 1350 } 1351 1352 u64 read_sanitised_ftr_reg(u32 id) 1353 { 1354 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1355 1356 if (!regp) 1357 return 0; 1358 return regp->sys_val; 1359 } 1360 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1361 1362 #define read_sysreg_case(r) \ 1363 case r: val = read_sysreg_s(r); break; 1364 1365 /* 1366 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1367 * Read the system register on the current CPU 1368 */ 1369 u64 __read_sysreg_by_encoding(u32 sys_id) 1370 { 1371 struct arm64_ftr_reg *regp; 1372 u64 val; 1373 1374 switch (sys_id) { 1375 read_sysreg_case(SYS_ID_PFR0_EL1); 1376 read_sysreg_case(SYS_ID_PFR1_EL1); 1377 read_sysreg_case(SYS_ID_PFR2_EL1); 1378 read_sysreg_case(SYS_ID_DFR0_EL1); 1379 read_sysreg_case(SYS_ID_DFR1_EL1); 1380 read_sysreg_case(SYS_ID_MMFR0_EL1); 1381 read_sysreg_case(SYS_ID_MMFR1_EL1); 1382 read_sysreg_case(SYS_ID_MMFR2_EL1); 1383 read_sysreg_case(SYS_ID_MMFR3_EL1); 1384 read_sysreg_case(SYS_ID_MMFR4_EL1); 1385 read_sysreg_case(SYS_ID_MMFR5_EL1); 1386 read_sysreg_case(SYS_ID_ISAR0_EL1); 1387 read_sysreg_case(SYS_ID_ISAR1_EL1); 1388 read_sysreg_case(SYS_ID_ISAR2_EL1); 1389 read_sysreg_case(SYS_ID_ISAR3_EL1); 1390 read_sysreg_case(SYS_ID_ISAR4_EL1); 1391 read_sysreg_case(SYS_ID_ISAR5_EL1); 1392 read_sysreg_case(SYS_ID_ISAR6_EL1); 1393 read_sysreg_case(SYS_MVFR0_EL1); 1394 read_sysreg_case(SYS_MVFR1_EL1); 1395 read_sysreg_case(SYS_MVFR2_EL1); 1396 1397 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1398 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1399 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1400 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1401 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1402 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1403 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1404 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1405 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1406 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1407 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1408 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1409 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1410 1411 read_sysreg_case(SYS_CNTFRQ_EL0); 1412 read_sysreg_case(SYS_CTR_EL0); 1413 read_sysreg_case(SYS_DCZID_EL0); 1414 1415 default: 1416 BUG(); 1417 return 0; 1418 } 1419 1420 regp = get_arm64_ftr_reg(sys_id); 1421 if (regp) { 1422 val &= ~regp->override->mask; 1423 val |= (regp->override->val & regp->override->mask); 1424 } 1425 1426 return val; 1427 } 1428 1429 #include <linux/irqchip/arm-gic-v3.h> 1430 1431 static bool 1432 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1433 { 1434 return true; 1435 } 1436 1437 static bool 1438 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1439 { 1440 int val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1441 entry->field_width, 1442 entry->sign); 1443 1444 return val >= entry->min_field_value; 1445 } 1446 1447 static u64 1448 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1449 { 1450 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1451 if (scope == SCOPE_SYSTEM) 1452 return read_sanitised_ftr_reg(entry->sys_reg); 1453 else 1454 return __read_sysreg_by_encoding(entry->sys_reg); 1455 } 1456 1457 static bool 1458 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1459 { 1460 int mask; 1461 struct arm64_ftr_reg *regp; 1462 u64 val = read_scoped_sysreg(entry, scope); 1463 1464 regp = get_arm64_ftr_reg(entry->sys_reg); 1465 if (!regp) 1466 return false; 1467 1468 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1469 entry->field_pos, 1470 entry->field_width); 1471 if (!mask) 1472 return false; 1473 1474 return feature_matches(val, entry); 1475 } 1476 1477 static bool 1478 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1479 { 1480 u64 val = read_scoped_sysreg(entry, scope); 1481 return feature_matches(val, entry); 1482 } 1483 1484 const struct cpumask *system_32bit_el0_cpumask(void) 1485 { 1486 if (!system_supports_32bit_el0()) 1487 return cpu_none_mask; 1488 1489 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1490 return cpu_32bit_el0_mask; 1491 1492 return cpu_possible_mask; 1493 } 1494 1495 static int __init parse_32bit_el0_param(char *str) 1496 { 1497 allow_mismatched_32bit_el0 = true; 1498 return 0; 1499 } 1500 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1501 1502 static ssize_t aarch32_el0_show(struct device *dev, 1503 struct device_attribute *attr, char *buf) 1504 { 1505 const struct cpumask *mask = system_32bit_el0_cpumask(); 1506 1507 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1508 } 1509 static const DEVICE_ATTR_RO(aarch32_el0); 1510 1511 static int __init aarch32_el0_sysfs_init(void) 1512 { 1513 struct device *dev_root; 1514 int ret = 0; 1515 1516 if (!allow_mismatched_32bit_el0) 1517 return 0; 1518 1519 dev_root = bus_get_dev_root(&cpu_subsys); 1520 if (dev_root) { 1521 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1522 put_device(dev_root); 1523 } 1524 return ret; 1525 } 1526 device_initcall(aarch32_el0_sysfs_init); 1527 1528 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1529 { 1530 if (!has_cpuid_feature(entry, scope)) 1531 return allow_mismatched_32bit_el0; 1532 1533 if (scope == SCOPE_SYSTEM) 1534 pr_info("detected: 32-bit EL0 Support\n"); 1535 1536 return true; 1537 } 1538 1539 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1540 { 1541 bool has_sre; 1542 1543 if (!has_cpuid_feature(entry, scope)) 1544 return false; 1545 1546 has_sre = gic_enable_sre(); 1547 if (!has_sre) 1548 pr_warn_once("%s present but disabled by higher exception level\n", 1549 entry->desc); 1550 1551 return has_sre; 1552 } 1553 1554 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1555 { 1556 u32 midr = read_cpuid_id(); 1557 1558 /* Cavium ThunderX pass 1.x and 2.x */ 1559 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1560 MIDR_CPU_VAR_REV(0, 0), 1561 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1562 } 1563 1564 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1565 { 1566 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1567 1568 return cpuid_feature_extract_signed_field(pfr0, 1569 ID_AA64PFR0_EL1_FP_SHIFT) < 0; 1570 } 1571 1572 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1573 int scope) 1574 { 1575 u64 ctr; 1576 1577 if (scope == SCOPE_SYSTEM) 1578 ctr = arm64_ftr_reg_ctrel0.sys_val; 1579 else 1580 ctr = read_cpuid_effective_cachetype(); 1581 1582 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1583 } 1584 1585 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1586 { 1587 /* 1588 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1589 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1590 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1591 * value. 1592 */ 1593 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1594 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1595 } 1596 1597 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1598 int scope) 1599 { 1600 u64 ctr; 1601 1602 if (scope == SCOPE_SYSTEM) 1603 ctr = arm64_ftr_reg_ctrel0.sys_val; 1604 else 1605 ctr = read_cpuid_cachetype(); 1606 1607 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1608 } 1609 1610 static bool __maybe_unused 1611 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1612 { 1613 /* 1614 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1615 * may share TLB entries with a CPU stuck in the crashed 1616 * kernel. 1617 */ 1618 if (is_kdump_kernel()) 1619 return false; 1620 1621 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1622 return false; 1623 1624 return has_cpuid_feature(entry, scope); 1625 } 1626 1627 /* 1628 * This check is triggered during the early boot before the cpufeature 1629 * is initialised. Checking the status on the local CPU allows the boot 1630 * CPU to detect the need for non-global mappings and thus avoiding a 1631 * pagetable re-write after all the CPUs are booted. This check will be 1632 * anyway run on individual CPUs, allowing us to get the consistent 1633 * state once the SMP CPUs are up and thus make the switch to non-global 1634 * mappings if required. 1635 */ 1636 bool kaslr_requires_kpti(void) 1637 { 1638 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1639 return false; 1640 1641 /* 1642 * E0PD does a similar job to KPTI so can be used instead 1643 * where available. 1644 */ 1645 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1646 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1647 if (cpuid_feature_extract_unsigned_field(mmfr2, 1648 ID_AA64MMFR2_EL1_E0PD_SHIFT)) 1649 return false; 1650 } 1651 1652 /* 1653 * Systems affected by Cavium erratum 24756 are incompatible 1654 * with KPTI. 1655 */ 1656 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1657 extern const struct midr_range cavium_erratum_27456_cpus[]; 1658 1659 if (is_midr_in_range_list(read_cpuid_id(), 1660 cavium_erratum_27456_cpus)) 1661 return false; 1662 } 1663 1664 return kaslr_enabled(); 1665 } 1666 1667 static bool __meltdown_safe = true; 1668 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1669 1670 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1671 int scope) 1672 { 1673 /* List of CPUs that are not vulnerable and don't need KPTI */ 1674 static const struct midr_range kpti_safe_list[] = { 1675 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1676 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1677 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1678 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1679 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1680 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1681 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1682 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1683 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1684 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1685 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1686 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1687 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1688 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1689 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1690 { /* sentinel */ } 1691 }; 1692 char const *str = "kpti command line option"; 1693 bool meltdown_safe; 1694 1695 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1696 1697 /* Defer to CPU feature registers */ 1698 if (has_cpuid_feature(entry, scope)) 1699 meltdown_safe = true; 1700 1701 if (!meltdown_safe) 1702 __meltdown_safe = false; 1703 1704 /* 1705 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1706 * ThunderX leads to apparent I-cache corruption of kernel text, which 1707 * ends as well as you might imagine. Don't even try. We cannot rely 1708 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1709 * because cpucap detection order may change. However, since we know 1710 * affected CPUs are always in a homogeneous configuration, it is 1711 * safe to rely on this_cpu_has_cap() here. 1712 */ 1713 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1714 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1715 __kpti_forced = -1; 1716 } 1717 1718 /* Useful for KASLR robustness */ 1719 if (kaslr_requires_kpti()) { 1720 if (!__kpti_forced) { 1721 str = "KASLR"; 1722 __kpti_forced = 1; 1723 } 1724 } 1725 1726 if (cpu_mitigations_off() && !__kpti_forced) { 1727 str = "mitigations=off"; 1728 __kpti_forced = -1; 1729 } 1730 1731 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1732 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1733 return false; 1734 } 1735 1736 /* Forced? */ 1737 if (__kpti_forced) { 1738 pr_info_once("kernel page table isolation forced %s by %s\n", 1739 __kpti_forced > 0 ? "ON" : "OFF", str); 1740 return __kpti_forced > 0; 1741 } 1742 1743 return !meltdown_safe; 1744 } 1745 1746 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1747 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1748 1749 extern 1750 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1751 phys_addr_t size, pgprot_t prot, 1752 phys_addr_t (*pgtable_alloc)(int), int flags); 1753 1754 static phys_addr_t kpti_ng_temp_alloc; 1755 1756 static phys_addr_t kpti_ng_pgd_alloc(int shift) 1757 { 1758 kpti_ng_temp_alloc -= PAGE_SIZE; 1759 return kpti_ng_temp_alloc; 1760 } 1761 1762 static void 1763 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1764 { 1765 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1766 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1767 kpti_remap_fn *remap_fn; 1768 1769 int cpu = smp_processor_id(); 1770 int levels = CONFIG_PGTABLE_LEVELS; 1771 int order = order_base_2(levels); 1772 u64 kpti_ng_temp_pgd_pa = 0; 1773 pgd_t *kpti_ng_temp_pgd; 1774 u64 alloc = 0; 1775 1776 if (__this_cpu_read(this_cpu_vector) == vectors) { 1777 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1778 1779 __this_cpu_write(this_cpu_vector, v); 1780 } 1781 1782 /* 1783 * We don't need to rewrite the page-tables if either we've done 1784 * it already or we have KASLR enabled and therefore have not 1785 * created any global mappings at all. 1786 */ 1787 if (arm64_use_ng_mappings) 1788 return; 1789 1790 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1791 1792 if (!cpu) { 1793 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1794 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1795 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1796 1797 // 1798 // Create a minimal page table hierarchy that permits us to map 1799 // the swapper page tables temporarily as we traverse them. 1800 // 1801 // The physical pages are laid out as follows: 1802 // 1803 // +--------+-/-------+-/------ +-\\--------+ 1804 // : PTE[] : | PMD[] : | PUD[] : || PGD[] : 1805 // +--------+-\-------+-\------ +-//--------+ 1806 // ^ 1807 // The first page is mapped into this hierarchy at a PMD_SHIFT 1808 // aligned virtual address, so that we can manipulate the PTE 1809 // level entries while the mapping is active. The first entry 1810 // covers the PTE[] page itself, the remaining entries are free 1811 // to be used as a ad-hoc fixmap. 1812 // 1813 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1814 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1815 kpti_ng_pgd_alloc, 0); 1816 } 1817 1818 cpu_install_idmap(); 1819 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1820 cpu_uninstall_idmap(); 1821 1822 if (!cpu) { 1823 free_pages(alloc, order); 1824 arm64_use_ng_mappings = true; 1825 } 1826 } 1827 #else 1828 static void 1829 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1830 { 1831 } 1832 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1833 1834 static int __init parse_kpti(char *str) 1835 { 1836 bool enabled; 1837 int ret = kstrtobool(str, &enabled); 1838 1839 if (ret) 1840 return ret; 1841 1842 __kpti_forced = enabled ? 1 : -1; 1843 return 0; 1844 } 1845 early_param("kpti", parse_kpti); 1846 1847 #ifdef CONFIG_ARM64_HW_AFDBM 1848 static inline void __cpu_enable_hw_dbm(void) 1849 { 1850 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1851 1852 write_sysreg(tcr, tcr_el1); 1853 isb(); 1854 local_flush_tlb_all(); 1855 } 1856 1857 static bool cpu_has_broken_dbm(void) 1858 { 1859 /* List of CPUs which have broken DBM support. */ 1860 static const struct midr_range cpus[] = { 1861 #ifdef CONFIG_ARM64_ERRATUM_1024718 1862 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1863 /* Kryo4xx Silver (rdpe => r1p0) */ 1864 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1865 #endif 1866 #ifdef CONFIG_ARM64_ERRATUM_2051678 1867 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1868 #endif 1869 {}, 1870 }; 1871 1872 return is_midr_in_range_list(read_cpuid_id(), cpus); 1873 } 1874 1875 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1876 { 1877 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1878 !cpu_has_broken_dbm(); 1879 } 1880 1881 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1882 { 1883 if (cpu_can_use_dbm(cap)) 1884 __cpu_enable_hw_dbm(); 1885 } 1886 1887 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1888 int __unused) 1889 { 1890 static bool detected = false; 1891 /* 1892 * DBM is a non-conflicting feature. i.e, the kernel can safely 1893 * run a mix of CPUs with and without the feature. So, we 1894 * unconditionally enable the capability to allow any late CPU 1895 * to use the feature. We only enable the control bits on the 1896 * CPU, if it actually supports. 1897 * 1898 * We have to make sure we print the "feature" detection only 1899 * when at least one CPU actually uses it. So check if this CPU 1900 * can actually use it and print the message exactly once. 1901 * 1902 * This is safe as all CPUs (including secondary CPUs - due to the 1903 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1904 * goes through the "matches" check exactly once. Also if a CPU 1905 * matches the criteria, it is guaranteed that the CPU will turn 1906 * the DBM on, as the capability is unconditionally enabled. 1907 */ 1908 if (!detected && cpu_can_use_dbm(cap)) { 1909 detected = true; 1910 pr_info("detected: Hardware dirty bit management\n"); 1911 } 1912 1913 return true; 1914 } 1915 1916 #endif 1917 1918 #ifdef CONFIG_ARM64_AMU_EXTN 1919 1920 /* 1921 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1922 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1923 * information regarding all the events that it supports. When a CPU bit is 1924 * set in the cpumask, the user of this feature can only rely on the presence 1925 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1926 * counters are enabled or access to these counters is enabled by code 1927 * executed at higher exception levels (firmware). 1928 */ 1929 static struct cpumask amu_cpus __read_mostly; 1930 1931 bool cpu_has_amu_feat(int cpu) 1932 { 1933 return cpumask_test_cpu(cpu, &amu_cpus); 1934 } 1935 1936 int get_cpu_with_amu_feat(void) 1937 { 1938 return cpumask_any(&amu_cpus); 1939 } 1940 1941 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1942 { 1943 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1944 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1945 smp_processor_id()); 1946 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1947 1948 /* 0 reference values signal broken/disabled counters */ 1949 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 1950 update_freq_counters_refs(); 1951 } 1952 } 1953 1954 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1955 int __unused) 1956 { 1957 /* 1958 * The AMU extension is a non-conflicting feature: the kernel can 1959 * safely run a mix of CPUs with and without support for the 1960 * activity monitors extension. Therefore, unconditionally enable 1961 * the capability to allow any late CPU to use the feature. 1962 * 1963 * With this feature unconditionally enabled, the cpu_enable 1964 * function will be called for all CPUs that match the criteria, 1965 * including secondary and hotplugged, marking this feature as 1966 * present on that respective CPU. The enable function will also 1967 * print a detection message. 1968 */ 1969 1970 return true; 1971 } 1972 #else 1973 int get_cpu_with_amu_feat(void) 1974 { 1975 return nr_cpu_ids; 1976 } 1977 #endif 1978 1979 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1980 { 1981 return is_kernel_in_hyp_mode(); 1982 } 1983 1984 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1985 { 1986 /* 1987 * Copy register values that aren't redirected by hardware. 1988 * 1989 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1990 * this value to tpidr_el2 before we patch the code. Once we've done 1991 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1992 * do anything here. 1993 */ 1994 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1995 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1996 } 1997 1998 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 1999 int scope) 2000 { 2001 if (kvm_get_mode() != KVM_MODE_NV) 2002 return false; 2003 2004 if (!has_cpuid_feature(cap, scope)) { 2005 pr_warn("unavailable: %s\n", cap->desc); 2006 return false; 2007 } 2008 2009 return true; 2010 } 2011 2012 #ifdef CONFIG_ARM64_PAN 2013 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2014 { 2015 /* 2016 * We modify PSTATE. This won't work from irq context as the PSTATE 2017 * is discarded once we return from the exception. 2018 */ 2019 WARN_ON_ONCE(in_interrupt()); 2020 2021 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2022 set_pstate_pan(1); 2023 } 2024 #endif /* CONFIG_ARM64_PAN */ 2025 2026 #ifdef CONFIG_ARM64_RAS_EXTN 2027 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2028 { 2029 /* Firmware may have left a deferred SError in this register. */ 2030 write_sysreg_s(0, SYS_DISR_EL1); 2031 } 2032 #endif /* CONFIG_ARM64_RAS_EXTN */ 2033 2034 #ifdef CONFIG_ARM64_PTR_AUTH 2035 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2036 { 2037 int boot_val, sec_val; 2038 2039 /* We don't expect to be called with SCOPE_SYSTEM */ 2040 WARN_ON(scope == SCOPE_SYSTEM); 2041 /* 2042 * The ptr-auth feature levels are not intercompatible with lower 2043 * levels. Hence we must match ptr-auth feature level of the secondary 2044 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2045 * from the sanitised register whereas direct register read is done for 2046 * the secondary CPUs. 2047 * The sanitised feature state is guaranteed to match that of the 2048 * boot CPU as a mismatched secondary CPU is parked before it gets 2049 * a chance to update the state, with the capability. 2050 */ 2051 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2052 entry->field_pos, entry->sign); 2053 if (scope & SCOPE_BOOT_CPU) 2054 return boot_val >= entry->min_field_value; 2055 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2056 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2057 entry->field_pos, entry->sign); 2058 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2059 } 2060 2061 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2062 int scope) 2063 { 2064 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2065 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2066 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2067 2068 return apa || apa3 || api; 2069 } 2070 2071 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2072 int __unused) 2073 { 2074 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2075 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2076 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2077 2078 return gpa || gpa3 || gpi; 2079 } 2080 #endif /* CONFIG_ARM64_PTR_AUTH */ 2081 2082 #ifdef CONFIG_ARM64_E0PD 2083 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2084 { 2085 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2086 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2087 } 2088 #endif /* CONFIG_ARM64_E0PD */ 2089 2090 #ifdef CONFIG_ARM64_PSEUDO_NMI 2091 static bool enable_pseudo_nmi; 2092 2093 static int __init early_enable_pseudo_nmi(char *p) 2094 { 2095 return kstrtobool(p, &enable_pseudo_nmi); 2096 } 2097 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 2098 2099 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2100 int scope) 2101 { 2102 /* 2103 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2104 * feature, so will be detected earlier. 2105 */ 2106 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2107 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2108 return false; 2109 2110 return enable_pseudo_nmi; 2111 } 2112 2113 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2114 int scope) 2115 { 2116 /* 2117 * If we're not using priority masking then we won't be poking PMR_EL1, 2118 * and there's no need to relax synchronization of writes to it, and 2119 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2120 * that. 2121 * 2122 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2123 * feature, so will be detected earlier. 2124 */ 2125 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2126 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2127 return false; 2128 2129 /* 2130 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2131 * hint for interrupt distribution, a DSB is not necessary when 2132 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2133 * 2134 * Linux itself doesn't use 1:N distribution, so has no need to 2135 * set PMHE. The only reason to have it set is if EL3 requires it 2136 * (and we can't change it). 2137 */ 2138 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2139 } 2140 #endif 2141 2142 #ifdef CONFIG_ARM64_BTI 2143 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2144 { 2145 /* 2146 * Use of X16/X17 for tail-calls and trampolines that jump to 2147 * function entry points using BR is a requirement for 2148 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2149 * So, be strict and forbid other BRs using other registers to 2150 * jump onto a PACIxSP instruction: 2151 */ 2152 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2153 isb(); 2154 } 2155 #endif /* CONFIG_ARM64_BTI */ 2156 2157 #ifdef CONFIG_ARM64_MTE 2158 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2159 { 2160 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2161 2162 mte_cpu_setup(); 2163 2164 /* 2165 * Clear the tags in the zero page. This needs to be done via the 2166 * linear map which has the Tagged attribute. 2167 */ 2168 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2169 mte_clear_page_tags(lm_alias(empty_zero_page)); 2170 set_page_mte_tagged(ZERO_PAGE(0)); 2171 } 2172 2173 kasan_init_hw_tags_cpu(); 2174 } 2175 #endif /* CONFIG_ARM64_MTE */ 2176 2177 static void elf_hwcap_fixup(void) 2178 { 2179 #ifdef CONFIG_ARM64_ERRATUM_1742098 2180 if (cpus_have_const_cap(ARM64_WORKAROUND_1742098)) 2181 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2182 #endif /* ARM64_ERRATUM_1742098 */ 2183 } 2184 2185 #ifdef CONFIG_KVM 2186 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2187 { 2188 return kvm_get_mode() == KVM_MODE_PROTECTED; 2189 } 2190 #endif /* CONFIG_KVM */ 2191 2192 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2193 { 2194 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2195 } 2196 2197 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2198 { 2199 set_pstate_dit(1); 2200 } 2201 2202 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2203 { 2204 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2205 } 2206 2207 /* Internal helper functions to match cpu capability type */ 2208 static bool 2209 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2210 { 2211 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2212 } 2213 2214 static bool 2215 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2216 { 2217 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2218 } 2219 2220 static bool 2221 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2222 { 2223 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2224 } 2225 2226 static const struct arm64_cpu_capabilities arm64_features[] = { 2227 { 2228 .capability = ARM64_ALWAYS_BOOT, 2229 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2230 .matches = has_always, 2231 }, 2232 { 2233 .capability = ARM64_ALWAYS_SYSTEM, 2234 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2235 .matches = has_always, 2236 }, 2237 { 2238 .desc = "GIC system register CPU interface", 2239 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2240 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2241 .matches = has_useable_gicv3_cpuif, 2242 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2243 }, 2244 { 2245 .desc = "Enhanced Counter Virtualization", 2246 .capability = ARM64_HAS_ECV, 2247 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2248 .matches = has_cpuid_feature, 2249 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2250 }, 2251 { 2252 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2253 .capability = ARM64_HAS_ECV_CNTPOFF, 2254 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2255 .matches = has_cpuid_feature, 2256 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2257 }, 2258 #ifdef CONFIG_ARM64_PAN 2259 { 2260 .desc = "Privileged Access Never", 2261 .capability = ARM64_HAS_PAN, 2262 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2263 .matches = has_cpuid_feature, 2264 .cpu_enable = cpu_enable_pan, 2265 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2266 }, 2267 #endif /* CONFIG_ARM64_PAN */ 2268 #ifdef CONFIG_ARM64_EPAN 2269 { 2270 .desc = "Enhanced Privileged Access Never", 2271 .capability = ARM64_HAS_EPAN, 2272 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2273 .matches = has_cpuid_feature, 2274 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2275 }, 2276 #endif /* CONFIG_ARM64_EPAN */ 2277 #ifdef CONFIG_ARM64_LSE_ATOMICS 2278 { 2279 .desc = "LSE atomic instructions", 2280 .capability = ARM64_HAS_LSE_ATOMICS, 2281 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2282 .matches = has_cpuid_feature, 2283 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2284 }, 2285 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2286 { 2287 .desc = "Software prefetching using PRFM", 2288 .capability = ARM64_HAS_NO_HW_PREFETCH, 2289 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2290 .matches = has_no_hw_prefetch, 2291 }, 2292 { 2293 .desc = "Virtualization Host Extensions", 2294 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2295 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2296 .matches = runs_at_el2, 2297 .cpu_enable = cpu_copy_el2regs, 2298 }, 2299 { 2300 .desc = "Nested Virtualization Support", 2301 .capability = ARM64_HAS_NESTED_VIRT, 2302 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2303 .matches = has_nested_virt_support, 2304 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, IMP) 2305 }, 2306 { 2307 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2308 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2309 .matches = has_32bit_el0, 2310 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2311 }, 2312 #ifdef CONFIG_KVM 2313 { 2314 .desc = "32-bit EL1 Support", 2315 .capability = ARM64_HAS_32BIT_EL1, 2316 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2317 .matches = has_cpuid_feature, 2318 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2319 }, 2320 { 2321 .desc = "Protected KVM", 2322 .capability = ARM64_KVM_PROTECTED_MODE, 2323 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2324 .matches = is_kvm_protected_mode, 2325 }, 2326 { 2327 .desc = "HCRX_EL2 register", 2328 .capability = ARM64_HAS_HCX, 2329 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2330 .matches = has_cpuid_feature, 2331 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2332 }, 2333 #endif 2334 { 2335 .desc = "Kernel page table isolation (KPTI)", 2336 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2337 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2338 .cpu_enable = kpti_install_ng_mappings, 2339 .matches = unmap_kernel_at_el0, 2340 /* 2341 * The ID feature fields below are used to indicate that 2342 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2343 * more details. 2344 */ 2345 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2346 }, 2347 { 2348 /* FP/SIMD is not implemented */ 2349 .capability = ARM64_HAS_NO_FPSIMD, 2350 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2351 .min_field_value = 0, 2352 .matches = has_no_fpsimd, 2353 }, 2354 #ifdef CONFIG_ARM64_PMEM 2355 { 2356 .desc = "Data cache clean to Point of Persistence", 2357 .capability = ARM64_HAS_DCPOP, 2358 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2359 .matches = has_cpuid_feature, 2360 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2361 }, 2362 { 2363 .desc = "Data cache clean to Point of Deep Persistence", 2364 .capability = ARM64_HAS_DCPODP, 2365 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2366 .matches = has_cpuid_feature, 2367 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2368 }, 2369 #endif 2370 #ifdef CONFIG_ARM64_SVE 2371 { 2372 .desc = "Scalable Vector Extension", 2373 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2374 .capability = ARM64_SVE, 2375 .cpu_enable = sve_kernel_enable, 2376 .matches = has_cpuid_feature, 2377 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2378 }, 2379 #endif /* CONFIG_ARM64_SVE */ 2380 #ifdef CONFIG_ARM64_RAS_EXTN 2381 { 2382 .desc = "RAS Extension Support", 2383 .capability = ARM64_HAS_RAS_EXTN, 2384 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2385 .matches = has_cpuid_feature, 2386 .cpu_enable = cpu_clear_disr, 2387 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2388 }, 2389 #endif /* CONFIG_ARM64_RAS_EXTN */ 2390 #ifdef CONFIG_ARM64_AMU_EXTN 2391 { 2392 /* 2393 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 2394 * Therefore, don't provide .desc as we don't want the detection 2395 * message to be shown until at least one CPU is detected to 2396 * support the feature. 2397 */ 2398 .capability = ARM64_HAS_AMU_EXTN, 2399 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2400 .matches = has_amu, 2401 .cpu_enable = cpu_amu_enable, 2402 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2403 }, 2404 #endif /* CONFIG_ARM64_AMU_EXTN */ 2405 { 2406 .desc = "Data cache clean to the PoU not required for I/D coherence", 2407 .capability = ARM64_HAS_CACHE_IDC, 2408 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2409 .matches = has_cache_idc, 2410 .cpu_enable = cpu_emulate_effective_ctr, 2411 }, 2412 { 2413 .desc = "Instruction cache invalidation not required for I/D coherence", 2414 .capability = ARM64_HAS_CACHE_DIC, 2415 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2416 .matches = has_cache_dic, 2417 }, 2418 { 2419 .desc = "Stage-2 Force Write-Back", 2420 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2421 .capability = ARM64_HAS_STAGE2_FWB, 2422 .matches = has_cpuid_feature, 2423 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2424 }, 2425 { 2426 .desc = "ARMv8.4 Translation Table Level", 2427 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2428 .capability = ARM64_HAS_ARMv8_4_TTL, 2429 .matches = has_cpuid_feature, 2430 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2431 }, 2432 { 2433 .desc = "TLB range maintenance instructions", 2434 .capability = ARM64_HAS_TLB_RANGE, 2435 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2436 .matches = has_cpuid_feature, 2437 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2438 }, 2439 #ifdef CONFIG_ARM64_HW_AFDBM 2440 { 2441 /* 2442 * Since we turn this on always, we don't want the user to 2443 * think that the feature is available when it may not be. 2444 * So hide the description. 2445 * 2446 * .desc = "Hardware pagetable Dirty Bit Management", 2447 * 2448 */ 2449 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2450 .capability = ARM64_HW_DBM, 2451 .matches = has_hw_dbm, 2452 .cpu_enable = cpu_enable_hw_dbm, 2453 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2454 }, 2455 #endif 2456 { 2457 .desc = "CRC32 instructions", 2458 .capability = ARM64_HAS_CRC32, 2459 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2460 .matches = has_cpuid_feature, 2461 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2462 }, 2463 { 2464 .desc = "Speculative Store Bypassing Safe (SSBS)", 2465 .capability = ARM64_SSBS, 2466 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2467 .matches = has_cpuid_feature, 2468 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2469 }, 2470 #ifdef CONFIG_ARM64_CNP 2471 { 2472 .desc = "Common not Private translations", 2473 .capability = ARM64_HAS_CNP, 2474 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2475 .matches = has_useable_cnp, 2476 .cpu_enable = cpu_enable_cnp, 2477 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2478 }, 2479 #endif 2480 { 2481 .desc = "Speculation barrier (SB)", 2482 .capability = ARM64_HAS_SB, 2483 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2484 .matches = has_cpuid_feature, 2485 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2486 }, 2487 #ifdef CONFIG_ARM64_PTR_AUTH 2488 { 2489 .desc = "Address authentication (architected QARMA5 algorithm)", 2490 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2491 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2492 .matches = has_address_auth_cpucap, 2493 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2494 }, 2495 { 2496 .desc = "Address authentication (architected QARMA3 algorithm)", 2497 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2498 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2499 .matches = has_address_auth_cpucap, 2500 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2501 }, 2502 { 2503 .desc = "Address authentication (IMP DEF algorithm)", 2504 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2505 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2506 .matches = has_address_auth_cpucap, 2507 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2508 }, 2509 { 2510 .capability = ARM64_HAS_ADDRESS_AUTH, 2511 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2512 .matches = has_address_auth_metacap, 2513 }, 2514 { 2515 .desc = "Generic authentication (architected QARMA5 algorithm)", 2516 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2517 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2518 .matches = has_cpuid_feature, 2519 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2520 }, 2521 { 2522 .desc = "Generic authentication (architected QARMA3 algorithm)", 2523 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2524 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2525 .matches = has_cpuid_feature, 2526 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2527 }, 2528 { 2529 .desc = "Generic authentication (IMP DEF algorithm)", 2530 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2531 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2532 .matches = has_cpuid_feature, 2533 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2534 }, 2535 { 2536 .capability = ARM64_HAS_GENERIC_AUTH, 2537 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2538 .matches = has_generic_auth, 2539 }, 2540 #endif /* CONFIG_ARM64_PTR_AUTH */ 2541 #ifdef CONFIG_ARM64_PSEUDO_NMI 2542 { 2543 /* 2544 * Depends on having GICv3 2545 */ 2546 .desc = "IRQ priority masking", 2547 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2548 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2549 .matches = can_use_gic_priorities, 2550 }, 2551 { 2552 /* 2553 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2554 */ 2555 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2556 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2557 .matches = has_gic_prio_relaxed_sync, 2558 }, 2559 #endif 2560 #ifdef CONFIG_ARM64_E0PD 2561 { 2562 .desc = "E0PD", 2563 .capability = ARM64_HAS_E0PD, 2564 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2565 .cpu_enable = cpu_enable_e0pd, 2566 .matches = has_cpuid_feature, 2567 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2568 }, 2569 #endif 2570 { 2571 .desc = "Random Number Generator", 2572 .capability = ARM64_HAS_RNG, 2573 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2574 .matches = has_cpuid_feature, 2575 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2576 }, 2577 #ifdef CONFIG_ARM64_BTI 2578 { 2579 .desc = "Branch Target Identification", 2580 .capability = ARM64_BTI, 2581 #ifdef CONFIG_ARM64_BTI_KERNEL 2582 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2583 #else 2584 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2585 #endif 2586 .matches = has_cpuid_feature, 2587 .cpu_enable = bti_enable, 2588 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2589 }, 2590 #endif 2591 #ifdef CONFIG_ARM64_MTE 2592 { 2593 .desc = "Memory Tagging Extension", 2594 .capability = ARM64_MTE, 2595 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2596 .matches = has_cpuid_feature, 2597 .cpu_enable = cpu_enable_mte, 2598 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2599 }, 2600 { 2601 .desc = "Asymmetric MTE Tag Check Fault", 2602 .capability = ARM64_MTE_ASYMM, 2603 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2604 .matches = has_cpuid_feature, 2605 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2606 }, 2607 #endif /* CONFIG_ARM64_MTE */ 2608 { 2609 .desc = "RCpc load-acquire (LDAPR)", 2610 .capability = ARM64_HAS_LDAPR, 2611 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2612 .matches = has_cpuid_feature, 2613 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2614 }, 2615 #ifdef CONFIG_ARM64_SME 2616 { 2617 .desc = "Scalable Matrix Extension", 2618 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2619 .capability = ARM64_SME, 2620 .matches = has_cpuid_feature, 2621 .cpu_enable = sme_kernel_enable, 2622 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2623 }, 2624 /* FA64 should be sorted after the base SME capability */ 2625 { 2626 .desc = "FA64", 2627 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2628 .capability = ARM64_SME_FA64, 2629 .matches = has_cpuid_feature, 2630 .cpu_enable = fa64_kernel_enable, 2631 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2632 }, 2633 { 2634 .desc = "SME2", 2635 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2636 .capability = ARM64_SME2, 2637 .matches = has_cpuid_feature, 2638 .cpu_enable = sme2_kernel_enable, 2639 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2640 }, 2641 #endif /* CONFIG_ARM64_SME */ 2642 { 2643 .desc = "WFx with timeout", 2644 .capability = ARM64_HAS_WFXT, 2645 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2646 .matches = has_cpuid_feature, 2647 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2648 }, 2649 { 2650 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2651 .capability = ARM64_HAS_TIDCP1, 2652 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2653 .matches = has_cpuid_feature, 2654 .cpu_enable = cpu_trap_el0_impdef, 2655 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2656 }, 2657 { 2658 .desc = "Data independent timing control (DIT)", 2659 .capability = ARM64_HAS_DIT, 2660 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2661 .matches = has_cpuid_feature, 2662 .cpu_enable = cpu_enable_dit, 2663 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2664 }, 2665 { 2666 .desc = "Memory Copy and Memory Set instructions", 2667 .capability = ARM64_HAS_MOPS, 2668 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2669 .matches = has_cpuid_feature, 2670 .cpu_enable = cpu_enable_mops, 2671 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2672 }, 2673 { 2674 .capability = ARM64_HAS_TCR2, 2675 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2676 .matches = has_cpuid_feature, 2677 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2678 }, 2679 { 2680 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2681 .capability = ARM64_HAS_S1PIE, 2682 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2683 .matches = has_cpuid_feature, 2684 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2685 }, 2686 {}, 2687 }; 2688 2689 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 2690 .matches = has_user_cpuid_feature, \ 2691 ARM64_CPUID_FIELDS(reg, field, min_value) 2692 2693 #define __HWCAP_CAP(name, cap_type, cap) \ 2694 .desc = name, \ 2695 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2696 .hwcap_type = cap_type, \ 2697 .hwcap = cap, \ 2698 2699 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 2700 { \ 2701 __HWCAP_CAP(#cap, cap_type, cap) \ 2702 HWCAP_CPUID_MATCH(reg, field, min_value) \ 2703 } 2704 2705 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2706 { \ 2707 __HWCAP_CAP(#cap, cap_type, cap) \ 2708 .matches = cpucap_multi_entry_cap_matches, \ 2709 .match_list = list, \ 2710 } 2711 2712 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2713 { \ 2714 __HWCAP_CAP(#cap, cap_type, cap) \ 2715 .matches = match, \ 2716 } 2717 2718 #ifdef CONFIG_ARM64_PTR_AUTH 2719 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2720 { 2721 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 2722 }, 2723 { 2724 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 2725 }, 2726 { 2727 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 2728 }, 2729 {}, 2730 }; 2731 2732 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2733 { 2734 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 2735 }, 2736 { 2737 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 2738 }, 2739 { 2740 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 2741 }, 2742 {}, 2743 }; 2744 #endif 2745 2746 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2747 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2748 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 2749 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2750 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2751 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2752 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2753 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2754 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2755 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2756 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 2757 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 2758 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2759 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2760 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2761 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2762 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 2763 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 2764 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2765 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2766 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2767 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 2768 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2769 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2770 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2771 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2772 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2773 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2774 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2775 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 2776 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 2777 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 2778 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 2779 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2780 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2781 #ifdef CONFIG_ARM64_SVE 2782 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 2783 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 2784 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2785 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2786 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2787 HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2788 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2789 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 2790 HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2791 HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2792 HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2793 HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2794 HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2795 #endif 2796 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2797 #ifdef CONFIG_ARM64_BTI 2798 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 2799 #endif 2800 #ifdef CONFIG_ARM64_PTR_AUTH 2801 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2802 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2803 #endif 2804 #ifdef CONFIG_ARM64_MTE 2805 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 2806 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 2807 #endif /* CONFIG_ARM64_MTE */ 2808 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 2809 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 2810 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 2811 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 2812 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2813 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 2814 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 2815 #ifdef CONFIG_ARM64_SME 2816 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 2817 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 2818 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 2819 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 2820 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 2821 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 2822 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 2823 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 2824 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 2825 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 2826 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 2827 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 2828 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 2829 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 2830 #endif /* CONFIG_ARM64_SME */ 2831 {}, 2832 }; 2833 2834 #ifdef CONFIG_COMPAT 2835 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2836 { 2837 /* 2838 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2839 * in line with that of arm32 as in vfp_init(). We make sure that the 2840 * check is future proof, by making sure value is non-zero. 2841 */ 2842 u32 mvfr1; 2843 2844 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2845 if (scope == SCOPE_SYSTEM) 2846 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2847 else 2848 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2849 2850 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 2851 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 2852 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 2853 } 2854 #endif 2855 2856 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2857 #ifdef CONFIG_COMPAT 2858 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2859 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2860 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2861 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2862 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2863 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 2864 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 2865 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2866 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2867 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2868 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2869 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2870 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 2871 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 2872 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 2873 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 2874 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 2875 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 2876 #endif 2877 {}, 2878 }; 2879 2880 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2881 { 2882 switch (cap->hwcap_type) { 2883 case CAP_HWCAP: 2884 cpu_set_feature(cap->hwcap); 2885 break; 2886 #ifdef CONFIG_COMPAT 2887 case CAP_COMPAT_HWCAP: 2888 compat_elf_hwcap |= (u32)cap->hwcap; 2889 break; 2890 case CAP_COMPAT_HWCAP2: 2891 compat_elf_hwcap2 |= (u32)cap->hwcap; 2892 break; 2893 #endif 2894 default: 2895 WARN_ON(1); 2896 break; 2897 } 2898 } 2899 2900 /* Check if we have a particular HWCAP enabled */ 2901 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2902 { 2903 bool rc; 2904 2905 switch (cap->hwcap_type) { 2906 case CAP_HWCAP: 2907 rc = cpu_have_feature(cap->hwcap); 2908 break; 2909 #ifdef CONFIG_COMPAT 2910 case CAP_COMPAT_HWCAP: 2911 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2912 break; 2913 case CAP_COMPAT_HWCAP2: 2914 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2915 break; 2916 #endif 2917 default: 2918 WARN_ON(1); 2919 rc = false; 2920 } 2921 2922 return rc; 2923 } 2924 2925 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2926 { 2927 /* We support emulation of accesses to CPU ID feature registers */ 2928 cpu_set_named_feature(CPUID); 2929 for (; hwcaps->matches; hwcaps++) 2930 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2931 cap_set_elf_hwcap(hwcaps); 2932 } 2933 2934 static void update_cpu_capabilities(u16 scope_mask) 2935 { 2936 int i; 2937 const struct arm64_cpu_capabilities *caps; 2938 2939 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2940 for (i = 0; i < ARM64_NCAPS; i++) { 2941 caps = cpucap_ptrs[i]; 2942 if (!caps || !(caps->type & scope_mask) || 2943 cpus_have_cap(caps->capability) || 2944 !caps->matches(caps, cpucap_default_scope(caps))) 2945 continue; 2946 2947 if (caps->desc) 2948 pr_info("detected: %s\n", caps->desc); 2949 2950 __set_bit(caps->capability, system_cpucaps); 2951 2952 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2953 set_bit(caps->capability, boot_cpucaps); 2954 } 2955 } 2956 2957 /* 2958 * Enable all the available capabilities on this CPU. The capabilities 2959 * with BOOT_CPU scope are handled separately and hence skipped here. 2960 */ 2961 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2962 { 2963 int i; 2964 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2965 2966 for_each_available_cap(i) { 2967 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 2968 2969 if (WARN_ON(!cap)) 2970 continue; 2971 2972 if (!(cap->type & non_boot_scope)) 2973 continue; 2974 2975 if (cap->cpu_enable) 2976 cap->cpu_enable(cap); 2977 } 2978 return 0; 2979 } 2980 2981 /* 2982 * Run through the enabled capabilities and enable() it on all active 2983 * CPUs 2984 */ 2985 static void __init enable_cpu_capabilities(u16 scope_mask) 2986 { 2987 int i; 2988 const struct arm64_cpu_capabilities *caps; 2989 bool boot_scope; 2990 2991 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2992 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2993 2994 for (i = 0; i < ARM64_NCAPS; i++) { 2995 unsigned int num; 2996 2997 caps = cpucap_ptrs[i]; 2998 if (!caps || !(caps->type & scope_mask)) 2999 continue; 3000 num = caps->capability; 3001 if (!cpus_have_cap(num)) 3002 continue; 3003 3004 if (boot_scope && caps->cpu_enable) 3005 /* 3006 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3007 * before any secondary CPU boots. Thus, each secondary 3008 * will enable the capability as appropriate via 3009 * check_local_cpu_capabilities(). The only exception is 3010 * the boot CPU, for which the capability must be 3011 * enabled here. This approach avoids costly 3012 * stop_machine() calls for this case. 3013 */ 3014 caps->cpu_enable(caps); 3015 } 3016 3017 /* 3018 * For all non-boot scope capabilities, use stop_machine() 3019 * as it schedules the work allowing us to modify PSTATE, 3020 * instead of on_each_cpu() which uses an IPI, giving us a 3021 * PSTATE that disappears when we return. 3022 */ 3023 if (!boot_scope) 3024 stop_machine(cpu_enable_non_boot_scope_capabilities, 3025 NULL, cpu_online_mask); 3026 } 3027 3028 /* 3029 * Run through the list of capabilities to check for conflicts. 3030 * If the system has already detected a capability, take necessary 3031 * action on this CPU. 3032 */ 3033 static void verify_local_cpu_caps(u16 scope_mask) 3034 { 3035 int i; 3036 bool cpu_has_cap, system_has_cap; 3037 const struct arm64_cpu_capabilities *caps; 3038 3039 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3040 3041 for (i = 0; i < ARM64_NCAPS; i++) { 3042 caps = cpucap_ptrs[i]; 3043 if (!caps || !(caps->type & scope_mask)) 3044 continue; 3045 3046 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3047 system_has_cap = cpus_have_cap(caps->capability); 3048 3049 if (system_has_cap) { 3050 /* 3051 * Check if the new CPU misses an advertised feature, 3052 * which is not safe to miss. 3053 */ 3054 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3055 break; 3056 /* 3057 * We have to issue cpu_enable() irrespective of 3058 * whether the CPU has it or not, as it is enabeld 3059 * system wide. It is upto the call back to take 3060 * appropriate action on this CPU. 3061 */ 3062 if (caps->cpu_enable) 3063 caps->cpu_enable(caps); 3064 } else { 3065 /* 3066 * Check if the CPU has this capability if it isn't 3067 * safe to have when the system doesn't. 3068 */ 3069 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3070 break; 3071 } 3072 } 3073 3074 if (i < ARM64_NCAPS) { 3075 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3076 smp_processor_id(), caps->capability, 3077 caps->desc, system_has_cap, cpu_has_cap); 3078 3079 if (cpucap_panic_on_conflict(caps)) 3080 cpu_panic_kernel(); 3081 else 3082 cpu_die_early(); 3083 } 3084 } 3085 3086 /* 3087 * Check for CPU features that are used in early boot 3088 * based on the Boot CPU value. 3089 */ 3090 static void check_early_cpu_features(void) 3091 { 3092 verify_cpu_asid_bits(); 3093 3094 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3095 } 3096 3097 static void 3098 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3099 { 3100 3101 for (; caps->matches; caps++) 3102 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3103 pr_crit("CPU%d: missing HWCAP: %s\n", 3104 smp_processor_id(), caps->desc); 3105 cpu_die_early(); 3106 } 3107 } 3108 3109 static void verify_local_elf_hwcaps(void) 3110 { 3111 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3112 3113 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3114 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3115 } 3116 3117 static void verify_sve_features(void) 3118 { 3119 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 3120 u64 zcr = read_zcr_features(); 3121 3122 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 3123 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 3124 3125 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) { 3126 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3127 smp_processor_id()); 3128 cpu_die_early(); 3129 } 3130 3131 /* Add checks on other ZCR bits here if necessary */ 3132 } 3133 3134 static void verify_sme_features(void) 3135 { 3136 u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1); 3137 u64 smcr = read_smcr_features(); 3138 3139 unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK; 3140 unsigned int len = smcr & SMCR_ELx_LEN_MASK; 3141 3142 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) { 3143 pr_crit("CPU%d: SME: vector length support mismatch\n", 3144 smp_processor_id()); 3145 cpu_die_early(); 3146 } 3147 3148 /* Add checks on other SMCR bits here if necessary */ 3149 } 3150 3151 static void verify_hyp_capabilities(void) 3152 { 3153 u64 safe_mmfr1, mmfr0, mmfr1; 3154 int parange, ipa_max; 3155 unsigned int safe_vmid_bits, vmid_bits; 3156 3157 if (!IS_ENABLED(CONFIG_KVM)) 3158 return; 3159 3160 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3161 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3162 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3163 3164 /* Verify VMID bits */ 3165 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3166 vmid_bits = get_vmid_bits(mmfr1); 3167 if (vmid_bits < safe_vmid_bits) { 3168 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3169 cpu_die_early(); 3170 } 3171 3172 /* Verify IPA range */ 3173 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3174 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3175 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3176 if (ipa_max < get_kvm_ipa_limit()) { 3177 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3178 cpu_die_early(); 3179 } 3180 } 3181 3182 /* 3183 * Run through the enabled system capabilities and enable() it on this CPU. 3184 * The capabilities were decided based on the available CPUs at the boot time. 3185 * Any new CPU should match the system wide status of the capability. If the 3186 * new CPU doesn't have a capability which the system now has enabled, we 3187 * cannot do anything to fix it up and could cause unexpected failures. So 3188 * we park the CPU. 3189 */ 3190 static void verify_local_cpu_capabilities(void) 3191 { 3192 /* 3193 * The capabilities with SCOPE_BOOT_CPU are checked from 3194 * check_early_cpu_features(), as they need to be verified 3195 * on all secondary CPUs. 3196 */ 3197 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3198 verify_local_elf_hwcaps(); 3199 3200 if (system_supports_sve()) 3201 verify_sve_features(); 3202 3203 if (system_supports_sme()) 3204 verify_sme_features(); 3205 3206 if (is_hyp_mode_available()) 3207 verify_hyp_capabilities(); 3208 } 3209 3210 void check_local_cpu_capabilities(void) 3211 { 3212 /* 3213 * All secondary CPUs should conform to the early CPU features 3214 * in use by the kernel based on boot CPU. 3215 */ 3216 check_early_cpu_features(); 3217 3218 /* 3219 * If we haven't finalised the system capabilities, this CPU gets 3220 * a chance to update the errata work arounds and local features. 3221 * Otherwise, this CPU should verify that it has all the system 3222 * advertised capabilities. 3223 */ 3224 if (!system_capabilities_finalized()) 3225 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3226 else 3227 verify_local_cpu_capabilities(); 3228 } 3229 3230 static void __init setup_boot_cpu_capabilities(void) 3231 { 3232 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 3233 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3234 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 3235 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3236 } 3237 3238 bool this_cpu_has_cap(unsigned int n) 3239 { 3240 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3241 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3242 3243 if (cap) 3244 return cap->matches(cap, SCOPE_LOCAL_CPU); 3245 } 3246 3247 return false; 3248 } 3249 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3250 3251 /* 3252 * This helper function is used in a narrow window when, 3253 * - The system wide safe registers are set with all the SMP CPUs and, 3254 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3255 * In all other cases cpus_have_{const_}cap() should be used. 3256 */ 3257 static bool __maybe_unused __system_matches_cap(unsigned int n) 3258 { 3259 if (n < ARM64_NCAPS) { 3260 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3261 3262 if (cap) 3263 return cap->matches(cap, SCOPE_SYSTEM); 3264 } 3265 return false; 3266 } 3267 3268 void cpu_set_feature(unsigned int num) 3269 { 3270 set_bit(num, elf_hwcap); 3271 } 3272 3273 bool cpu_have_feature(unsigned int num) 3274 { 3275 return test_bit(num, elf_hwcap); 3276 } 3277 EXPORT_SYMBOL_GPL(cpu_have_feature); 3278 3279 unsigned long cpu_get_elf_hwcap(void) 3280 { 3281 /* 3282 * We currently only populate the first 32 bits of AT_HWCAP. Please 3283 * note that for userspace compatibility we guarantee that bits 62 3284 * and 63 will always be returned as 0. 3285 */ 3286 return elf_hwcap[0]; 3287 } 3288 3289 unsigned long cpu_get_elf_hwcap2(void) 3290 { 3291 return elf_hwcap[1]; 3292 } 3293 3294 static void __init setup_system_capabilities(void) 3295 { 3296 /* 3297 * We have finalised the system-wide safe feature 3298 * registers, finalise the capabilities that depend 3299 * on it. Also enable all the available capabilities, 3300 * that are not enabled already. 3301 */ 3302 update_cpu_capabilities(SCOPE_SYSTEM); 3303 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3304 } 3305 3306 void __init setup_cpu_features(void) 3307 { 3308 u32 cwg; 3309 3310 setup_system_capabilities(); 3311 setup_elf_hwcaps(arm64_elf_hwcaps); 3312 3313 if (system_supports_32bit_el0()) { 3314 setup_elf_hwcaps(compat_elf_hwcaps); 3315 elf_hwcap_fixup(); 3316 } 3317 3318 if (system_uses_ttbr0_pan()) 3319 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3320 3321 sve_setup(); 3322 sme_setup(); 3323 minsigstksz_setup(); 3324 3325 /* 3326 * Check for sane CTR_EL0.CWG value. 3327 */ 3328 cwg = cache_type_cwg(); 3329 if (!cwg) 3330 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3331 ARCH_DMA_MINALIGN); 3332 } 3333 3334 static int enable_mismatched_32bit_el0(unsigned int cpu) 3335 { 3336 /* 3337 * The first 32-bit-capable CPU we detected and so can no longer 3338 * be offlined by userspace. -1 indicates we haven't yet onlined 3339 * a 32-bit-capable CPU. 3340 */ 3341 static int lucky_winner = -1; 3342 3343 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3344 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3345 3346 if (cpu_32bit) { 3347 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3348 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3349 } 3350 3351 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3352 return 0; 3353 3354 if (lucky_winner >= 0) 3355 return 0; 3356 3357 /* 3358 * We've detected a mismatch. We need to keep one of our CPUs with 3359 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3360 * every CPU in the system for a 32-bit task. 3361 */ 3362 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3363 cpu_active_mask); 3364 get_cpu_device(lucky_winner)->offline_disabled = true; 3365 setup_elf_hwcaps(compat_elf_hwcaps); 3366 elf_hwcap_fixup(); 3367 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3368 cpu, lucky_winner); 3369 return 0; 3370 } 3371 3372 static int __init init_32bit_el0_mask(void) 3373 { 3374 if (!allow_mismatched_32bit_el0) 3375 return 0; 3376 3377 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3378 return -ENOMEM; 3379 3380 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3381 "arm64/mismatched_32bit_el0:online", 3382 enable_mismatched_32bit_el0, NULL); 3383 } 3384 subsys_initcall_sync(init_32bit_el0_mask); 3385 3386 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3387 { 3388 cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir); 3389 } 3390 3391 /* 3392 * We emulate only the following system register space. 3393 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3394 * See Table C5-6 System instruction encodings for System register accesses, 3395 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3396 */ 3397 static inline bool __attribute_const__ is_emulated(u32 id) 3398 { 3399 return (sys_reg_Op0(id) == 0x3 && 3400 sys_reg_CRn(id) == 0x0 && 3401 sys_reg_Op1(id) == 0x0 && 3402 (sys_reg_CRm(id) == 0 || 3403 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3404 } 3405 3406 /* 3407 * With CRm == 0, reg should be one of : 3408 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3409 */ 3410 static inline int emulate_id_reg(u32 id, u64 *valp) 3411 { 3412 switch (id) { 3413 case SYS_MIDR_EL1: 3414 *valp = read_cpuid_id(); 3415 break; 3416 case SYS_MPIDR_EL1: 3417 *valp = SYS_MPIDR_SAFE_VAL; 3418 break; 3419 case SYS_REVIDR_EL1: 3420 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3421 *valp = 0; 3422 break; 3423 default: 3424 return -EINVAL; 3425 } 3426 3427 return 0; 3428 } 3429 3430 static int emulate_sys_reg(u32 id, u64 *valp) 3431 { 3432 struct arm64_ftr_reg *regp; 3433 3434 if (!is_emulated(id)) 3435 return -EINVAL; 3436 3437 if (sys_reg_CRm(id) == 0) 3438 return emulate_id_reg(id, valp); 3439 3440 regp = get_arm64_ftr_reg_nowarn(id); 3441 if (regp) 3442 *valp = arm64_ftr_reg_user_value(regp); 3443 else 3444 /* 3445 * The untracked registers are either IMPLEMENTATION DEFINED 3446 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3447 */ 3448 *valp = 0; 3449 return 0; 3450 } 3451 3452 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3453 { 3454 int rc; 3455 u64 val; 3456 3457 rc = emulate_sys_reg(sys_reg, &val); 3458 if (!rc) { 3459 pt_regs_write_reg(regs, rt, val); 3460 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3461 } 3462 return rc; 3463 } 3464 3465 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3466 { 3467 u32 sys_reg, rt; 3468 3469 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3470 return false; 3471 3472 /* 3473 * sys_reg values are defined as used in mrs/msr instruction. 3474 * shift the imm value to get the encoding. 3475 */ 3476 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3477 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3478 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3479 } 3480 3481 enum mitigation_state arm64_get_meltdown_state(void) 3482 { 3483 if (__meltdown_safe) 3484 return SPECTRE_UNAFFECTED; 3485 3486 if (arm64_kernel_unmapped_at_el0()) 3487 return SPECTRE_MITIGATED; 3488 3489 return SPECTRE_VULNERABLE; 3490 } 3491 3492 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3493 char *buf) 3494 { 3495 switch (arm64_get_meltdown_state()) { 3496 case SPECTRE_UNAFFECTED: 3497 return sprintf(buf, "Not affected\n"); 3498 3499 case SPECTRE_MITIGATED: 3500 return sprintf(buf, "Mitigation: PTI\n"); 3501 3502 default: 3503 return sprintf(buf, "Vulnerable\n"); 3504 } 3505 } 3506