1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/sysfs.h> 71 #include <linux/types.h> 72 #include <linux/minmax.h> 73 #include <linux/mm.h> 74 #include <linux/cpu.h> 75 #include <linux/kasan.h> 76 #include <linux/percpu.h> 77 78 #include <asm/cpu.h> 79 #include <asm/cpufeature.h> 80 #include <asm/cpu_ops.h> 81 #include <asm/fpsimd.h> 82 #include <asm/insn.h> 83 #include <asm/kvm_host.h> 84 #include <asm/mmu_context.h> 85 #include <asm/mte.h> 86 #include <asm/processor.h> 87 #include <asm/smp.h> 88 #include <asm/sysreg.h> 89 #include <asm/traps.h> 90 #include <asm/vectors.h> 91 #include <asm/virt.h> 92 93 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 94 static unsigned long elf_hwcap __read_mostly; 95 96 #ifdef CONFIG_COMPAT 97 #define COMPAT_ELF_HWCAP_DEFAULT \ 98 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 99 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 100 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 101 COMPAT_HWCAP_LPAE) 102 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 103 unsigned int compat_elf_hwcap2 __read_mostly; 104 #endif 105 106 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 107 EXPORT_SYMBOL(cpu_hwcaps); 108 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 109 110 /* Need also bit for ARM64_CB_PATCH */ 111 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 112 113 bool arm64_use_ng_mappings = false; 114 EXPORT_SYMBOL(arm64_use_ng_mappings); 115 116 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 117 118 /* 119 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 120 * support it? 121 */ 122 static bool __read_mostly allow_mismatched_32bit_el0; 123 124 /* 125 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 126 * seen at least one CPU capable of 32-bit EL0. 127 */ 128 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 129 130 /* 131 * Mask of CPUs supporting 32-bit EL0. 132 * Only valid if arm64_mismatched_32bit_el0 is enabled. 133 */ 134 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 135 136 /* 137 * Flag to indicate if we have computed the system wide 138 * capabilities based on the boot time active CPUs. This 139 * will be used to determine if a new booting CPU should 140 * go through the verification process to make sure that it 141 * supports the system capabilities, without using a hotplug 142 * notifier. This is also used to decide if we could use 143 * the fast path for checking constant CPU caps. 144 */ 145 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 146 EXPORT_SYMBOL(arm64_const_caps_ready); 147 static inline void finalize_system_capabilities(void) 148 { 149 static_branch_enable(&arm64_const_caps_ready); 150 } 151 152 void dump_cpu_features(void) 153 { 154 /* file-wide pr_fmt adds "CPU features: " prefix */ 155 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 156 } 157 158 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 159 EXPORT_SYMBOL(cpu_hwcap_keys); 160 161 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 162 { \ 163 .sign = SIGNED, \ 164 .visible = VISIBLE, \ 165 .strict = STRICT, \ 166 .type = TYPE, \ 167 .shift = SHIFT, \ 168 .width = WIDTH, \ 169 .safe_val = SAFE_VAL, \ 170 } 171 172 /* Define a feature with unsigned values */ 173 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 174 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 175 176 /* Define a feature with a signed value */ 177 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 178 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 179 180 #define ARM64_FTR_END \ 181 { \ 182 .width = 0, \ 183 } 184 185 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 186 187 static bool __system_matches_cap(unsigned int n); 188 189 /* 190 * NOTE: Any changes to the visibility of features should be kept in 191 * sync with the documentation of the CPU feature register ABI. 192 */ 193 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 208 ARM64_FTR_END, 209 }; 210 211 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 219 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 221 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 226 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 228 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 230 ARM64_FTR_END, 231 }; 232 233 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 236 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 238 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0), 240 ARM64_FTR_END, 241 }; 242 243 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 254 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 255 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), 259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY), 260 ARM64_FTR_END, 261 }; 262 263 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 264 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI), 268 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 269 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 270 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 271 ARM64_FTR_END, 272 }; 273 274 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 276 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 278 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 280 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 282 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 284 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 286 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 288 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 290 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 292 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 293 ARM64_FTR_END, 294 }; 295 296 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 297 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), 300 /* 301 * Page size not being supported at Stage-2 is not fatal. You 302 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 303 * your favourite nesting hypervisor. 304 * 305 * There is a small corner case where the hypervisor explicitly 306 * advertises a given granule size at Stage-2 (value 2) on some 307 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 308 * vCPUs. Although this is not forbidden by the architecture, it 309 * indicates that the hypervisor is being silly (or buggy). 310 * 311 * We make no effort to cope with this and pretend that if these 312 * fields are inconsistent across vCPUs, then it isn't worth 313 * trying to bring KVM up. 314 */ 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 318 /* 319 * We already refuse to boot CPUs that don't support our configured 320 * page size, so we can only detect mismatches for a page size other 321 * than the one we're currently using. Unfortunately, SoCs like this 322 * exist in the wild so, even though we don't like it, we'll have to go 323 * along with it and treat them as non-strict. 324 */ 325 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 326 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 328 329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 330 /* Linux shouldn't care about secure memory */ 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 334 /* 335 * Differing PARange is fine as long as all peripherals and memory are mapped 336 * within the minimum PARange of all CPUs 337 */ 338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 339 ARM64_FTR_END, 340 }; 341 342 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 343 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), 345 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), 346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), 347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 354 ARM64_FTR_END, 355 }; 356 357 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 359 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0), 360 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0), 361 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0), 362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0), 364 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 373 ARM64_FTR_END, 374 }; 375 376 static const struct arm64_ftr_bits ftr_ctr[] = { 377 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 378 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 379 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 380 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 382 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 383 /* 384 * Linux can handle differing I-cache policies. Userspace JITs will 385 * make use of *minLine. 386 * If we have differing I-cache policies, report it as the weakest - VIPT. 387 */ 388 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 389 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 390 ARM64_FTR_END, 391 }; 392 393 static struct arm64_ftr_override __ro_after_init no_override = { }; 394 395 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 396 .name = "SYS_CTR_EL0", 397 .ftr_bits = ftr_ctr, 398 .override = &no_override, 399 }; 400 401 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 402 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 403 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 407 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 410 ARM64_FTR_END, 411 }; 412 413 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 414 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0), 415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 417 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 419 /* 420 * We can instantiate multiple PMU instances with different levels 421 * of support. 422 */ 423 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 425 ARM64_FTR_END, 426 }; 427 428 static const struct arm64_ftr_bits ftr_mvfr2[] = { 429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 431 ARM64_FTR_END, 432 }; 433 434 static const struct arm64_ftr_bits ftr_dczid[] = { 435 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), 436 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), 437 ARM64_FTR_END, 438 }; 439 440 static const struct arm64_ftr_bits ftr_gmid[] = { 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0), 442 ARM64_FTR_END, 443 }; 444 445 static const struct arm64_ftr_bits ftr_id_isar0[] = { 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 453 ARM64_FTR_END, 454 }; 455 456 static const struct arm64_ftr_bits ftr_id_isar5[] = { 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 463 ARM64_FTR_END, 464 }; 465 466 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 474 475 /* 476 * SpecSEI = 1 indicates that the PE might generate an SError on an 477 * external abort on speculative read. It is safe to assume that an 478 * SError might be generated than it will not be. Hence it has been 479 * classified as FTR_HIGHER_SAFE. 480 */ 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 482 ARM64_FTR_END, 483 }; 484 485 static const struct arm64_ftr_bits ftr_id_isar4[] = { 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 494 ARM64_FTR_END, 495 }; 496 497 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 499 ARM64_FTR_END, 500 }; 501 502 static const struct arm64_ftr_bits ftr_id_isar6[] = { 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 510 ARM64_FTR_END, 511 }; 512 513 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 520 ARM64_FTR_END, 521 }; 522 523 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 524 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 532 ARM64_FTR_END, 533 }; 534 535 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 538 ARM64_FTR_END, 539 }; 540 541 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 542 /* [31:28] TraceFilt */ 543 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 550 ARM64_FTR_END, 551 }; 552 553 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 554 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 555 ARM64_FTR_END, 556 }; 557 558 static const struct arm64_ftr_bits ftr_zcr[] = { 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 560 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 561 ARM64_FTR_END, 562 }; 563 564 /* 565 * Common ftr bits for a 32bit register with all hidden, strict 566 * attributes, with 4bit feature fields and a default safe value of 567 * 0. Covers the following 32bit registers: 568 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 569 */ 570 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 578 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 579 ARM64_FTR_END, 580 }; 581 582 /* Table for a single 32bit feature value */ 583 static const struct arm64_ftr_bits ftr_single32[] = { 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 585 ARM64_FTR_END, 586 }; 587 588 static const struct arm64_ftr_bits ftr_raz[] = { 589 ARM64_FTR_END, 590 }; 591 592 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 593 .sys_id = id, \ 594 .reg = &(struct arm64_ftr_reg){ \ 595 .name = id_str, \ 596 .override = (ovr), \ 597 .ftr_bits = &((table)[0]), \ 598 }} 599 600 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 601 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 602 603 #define ARM64_FTR_REG(id, table) \ 604 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 605 606 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 607 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 608 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 609 struct arm64_ftr_override __ro_after_init id_aa64isar2_override; 610 611 static const struct __ftr_reg_entry { 612 u32 sys_id; 613 struct arm64_ftr_reg *reg; 614 } arm64_ftr_regs[] = { 615 616 /* Op1 = 0, CRn = 0, CRm = 1 */ 617 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 618 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 619 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 620 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 621 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 622 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 623 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 624 625 /* Op1 = 0, CRn = 0, CRm = 2 */ 626 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 627 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 628 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 629 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 630 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 631 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 632 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 633 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 634 635 /* Op1 = 0, CRn = 0, CRm = 3 */ 636 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 637 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 638 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 639 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 640 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 641 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 642 643 /* Op1 = 0, CRn = 0, CRm = 4 */ 644 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 645 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 646 &id_aa64pfr1_override), 647 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 648 649 /* Op1 = 0, CRn = 0, CRm = 5 */ 650 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 651 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 652 653 /* Op1 = 0, CRn = 0, CRm = 6 */ 654 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 655 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 656 &id_aa64isar1_override), 657 ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2), 658 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 659 &id_aa64isar2_override), 660 661 /* Op1 = 0, CRn = 0, CRm = 7 */ 662 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 663 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 664 &id_aa64mmfr1_override), 665 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 666 667 /* Op1 = 0, CRn = 1, CRm = 2 */ 668 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 669 670 /* Op1 = 1, CRn = 0, CRm = 0 */ 671 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 672 673 /* Op1 = 3, CRn = 0, CRm = 0 */ 674 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 675 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 676 677 /* Op1 = 3, CRn = 14, CRm = 0 */ 678 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 679 }; 680 681 static int search_cmp_ftr_reg(const void *id, const void *regp) 682 { 683 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 684 } 685 686 /* 687 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 688 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 689 * ascending order of sys_id, we use binary search to find a matching 690 * entry. 691 * 692 * returns - Upon success, matching ftr_reg entry for id. 693 * - NULL on failure. It is upto the caller to decide 694 * the impact of a failure. 695 */ 696 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 697 { 698 const struct __ftr_reg_entry *ret; 699 700 ret = bsearch((const void *)(unsigned long)sys_id, 701 arm64_ftr_regs, 702 ARRAY_SIZE(arm64_ftr_regs), 703 sizeof(arm64_ftr_regs[0]), 704 search_cmp_ftr_reg); 705 if (ret) 706 return ret->reg; 707 return NULL; 708 } 709 710 /* 711 * get_arm64_ftr_reg - Looks up a feature register entry using 712 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 713 * 714 * returns - Upon success, matching ftr_reg entry for id. 715 * - NULL on failure but with an WARN_ON(). 716 */ 717 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 718 { 719 struct arm64_ftr_reg *reg; 720 721 reg = get_arm64_ftr_reg_nowarn(sys_id); 722 723 /* 724 * Requesting a non-existent register search is an error. Warn 725 * and let the caller handle it. 726 */ 727 WARN_ON(!reg); 728 return reg; 729 } 730 731 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 732 s64 ftr_val) 733 { 734 u64 mask = arm64_ftr_mask(ftrp); 735 736 reg &= ~mask; 737 reg |= (ftr_val << ftrp->shift) & mask; 738 return reg; 739 } 740 741 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 742 s64 cur) 743 { 744 s64 ret = 0; 745 746 switch (ftrp->type) { 747 case FTR_EXACT: 748 ret = ftrp->safe_val; 749 break; 750 case FTR_LOWER_SAFE: 751 ret = min(new, cur); 752 break; 753 case FTR_HIGHER_OR_ZERO_SAFE: 754 if (!cur || !new) 755 break; 756 fallthrough; 757 case FTR_HIGHER_SAFE: 758 ret = max(new, cur); 759 break; 760 default: 761 BUG(); 762 } 763 764 return ret; 765 } 766 767 static void __init sort_ftr_regs(void) 768 { 769 unsigned int i; 770 771 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 772 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 773 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 774 unsigned int j = 0; 775 776 /* 777 * Features here must be sorted in descending order with respect 778 * to their shift values and should not overlap with each other. 779 */ 780 for (; ftr_bits->width != 0; ftr_bits++, j++) { 781 unsigned int width = ftr_reg->ftr_bits[j].width; 782 unsigned int shift = ftr_reg->ftr_bits[j].shift; 783 unsigned int prev_shift; 784 785 WARN((shift + width) > 64, 786 "%s has invalid feature at shift %d\n", 787 ftr_reg->name, shift); 788 789 /* 790 * Skip the first feature. There is nothing to 791 * compare against for now. 792 */ 793 if (j == 0) 794 continue; 795 796 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 797 WARN((shift + width) > prev_shift, 798 "%s has feature overlap at shift %d\n", 799 ftr_reg->name, shift); 800 } 801 802 /* 803 * Skip the first register. There is nothing to 804 * compare against for now. 805 */ 806 if (i == 0) 807 continue; 808 /* 809 * Registers here must be sorted in ascending order with respect 810 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 811 * to work correctly. 812 */ 813 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 814 } 815 } 816 817 /* 818 * Initialise the CPU feature register from Boot CPU values. 819 * Also initiliases the strict_mask for the register. 820 * Any bits that are not covered by an arm64_ftr_bits entry are considered 821 * RES0 for the system-wide value, and must strictly match. 822 */ 823 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 824 { 825 u64 val = 0; 826 u64 strict_mask = ~0x0ULL; 827 u64 user_mask = 0; 828 u64 valid_mask = 0; 829 830 const struct arm64_ftr_bits *ftrp; 831 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 832 833 if (!reg) 834 return; 835 836 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 837 u64 ftr_mask = arm64_ftr_mask(ftrp); 838 s64 ftr_new = arm64_ftr_value(ftrp, new); 839 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 840 841 if ((ftr_mask & reg->override->mask) == ftr_mask) { 842 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 843 char *str = NULL; 844 845 if (ftr_ovr != tmp) { 846 /* Unsafe, remove the override */ 847 reg->override->mask &= ~ftr_mask; 848 reg->override->val &= ~ftr_mask; 849 tmp = ftr_ovr; 850 str = "ignoring override"; 851 } else if (ftr_new != tmp) { 852 /* Override was valid */ 853 ftr_new = tmp; 854 str = "forced"; 855 } else if (ftr_ovr == tmp) { 856 /* Override was the safe value */ 857 str = "already set"; 858 } 859 860 if (str) 861 pr_warn("%s[%d:%d]: %s to %llx\n", 862 reg->name, 863 ftrp->shift + ftrp->width - 1, 864 ftrp->shift, str, tmp); 865 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 866 reg->override->val &= ~ftr_mask; 867 pr_warn("%s[%d:%d]: impossible override, ignored\n", 868 reg->name, 869 ftrp->shift + ftrp->width - 1, 870 ftrp->shift); 871 } 872 873 val = arm64_ftr_set_value(ftrp, val, ftr_new); 874 875 valid_mask |= ftr_mask; 876 if (!ftrp->strict) 877 strict_mask &= ~ftr_mask; 878 if (ftrp->visible) 879 user_mask |= ftr_mask; 880 else 881 reg->user_val = arm64_ftr_set_value(ftrp, 882 reg->user_val, 883 ftrp->safe_val); 884 } 885 886 val &= valid_mask; 887 888 reg->sys_val = val; 889 reg->strict_mask = strict_mask; 890 reg->user_mask = user_mask; 891 } 892 893 extern const struct arm64_cpu_capabilities arm64_errata[]; 894 static const struct arm64_cpu_capabilities arm64_features[]; 895 896 static void __init 897 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 898 { 899 for (; caps->matches; caps++) { 900 if (WARN(caps->capability >= ARM64_NCAPS, 901 "Invalid capability %d\n", caps->capability)) 902 continue; 903 if (WARN(cpu_hwcaps_ptrs[caps->capability], 904 "Duplicate entry for capability %d\n", 905 caps->capability)) 906 continue; 907 cpu_hwcaps_ptrs[caps->capability] = caps; 908 } 909 } 910 911 static void __init init_cpu_hwcaps_indirect_list(void) 912 { 913 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 914 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 915 } 916 917 static void __init setup_boot_cpu_capabilities(void); 918 919 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 920 { 921 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 922 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 923 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 924 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 925 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 926 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 927 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 928 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 929 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 930 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 931 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 932 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 933 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 934 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 935 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 936 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 937 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 938 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 939 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 940 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 941 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 942 } 943 944 void __init init_cpu_features(struct cpuinfo_arm64 *info) 945 { 946 /* Before we start using the tables, make sure it is sorted */ 947 sort_ftr_regs(); 948 949 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 950 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 951 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 952 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 953 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 954 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 955 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 956 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 957 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 958 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 959 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 960 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 961 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 962 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 963 964 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 965 init_32bit_cpu_features(&info->aarch32); 966 967 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 968 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 969 vec_init_vq_map(ARM64_VEC_SVE); 970 } 971 972 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 973 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 974 975 /* 976 * Initialize the indirect array of CPU hwcaps capabilities pointers 977 * before we handle the boot CPU below. 978 */ 979 init_cpu_hwcaps_indirect_list(); 980 981 /* 982 * Detect and enable early CPU capabilities based on the boot CPU, 983 * after we have initialised the CPU feature infrastructure. 984 */ 985 setup_boot_cpu_capabilities(); 986 } 987 988 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 989 { 990 const struct arm64_ftr_bits *ftrp; 991 992 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 993 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 994 s64 ftr_new = arm64_ftr_value(ftrp, new); 995 996 if (ftr_cur == ftr_new) 997 continue; 998 /* Find a safe value */ 999 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1000 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1001 } 1002 1003 } 1004 1005 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1006 { 1007 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1008 1009 if (!regp) 1010 return 0; 1011 1012 update_cpu_ftr_reg(regp, val); 1013 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1014 return 0; 1015 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1016 regp->name, boot, cpu, val); 1017 return 1; 1018 } 1019 1020 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1021 { 1022 const struct arm64_ftr_bits *ftrp; 1023 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1024 1025 if (!regp) 1026 return; 1027 1028 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1029 if (ftrp->shift == field) { 1030 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1031 break; 1032 } 1033 } 1034 1035 /* Bogus field? */ 1036 WARN_ON(!ftrp->width); 1037 } 1038 1039 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1040 struct cpuinfo_arm64 *boot) 1041 { 1042 static bool boot_cpu_32bit_regs_overridden = false; 1043 1044 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1045 return; 1046 1047 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1048 return; 1049 1050 boot->aarch32 = info->aarch32; 1051 init_32bit_cpu_features(&boot->aarch32); 1052 boot_cpu_32bit_regs_overridden = true; 1053 } 1054 1055 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1056 struct cpuinfo_32bit *boot) 1057 { 1058 int taint = 0; 1059 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1060 1061 /* 1062 * If we don't have AArch32 at EL1, then relax the strictness of 1063 * EL1-dependent register fields to avoid spurious sanity check fails. 1064 */ 1065 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1066 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 1067 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 1068 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 1069 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 1070 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 1071 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 1072 } 1073 1074 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1075 info->reg_id_dfr0, boot->reg_id_dfr0); 1076 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1077 info->reg_id_dfr1, boot->reg_id_dfr1); 1078 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1079 info->reg_id_isar0, boot->reg_id_isar0); 1080 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1081 info->reg_id_isar1, boot->reg_id_isar1); 1082 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1083 info->reg_id_isar2, boot->reg_id_isar2); 1084 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1085 info->reg_id_isar3, boot->reg_id_isar3); 1086 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1087 info->reg_id_isar4, boot->reg_id_isar4); 1088 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1089 info->reg_id_isar5, boot->reg_id_isar5); 1090 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1091 info->reg_id_isar6, boot->reg_id_isar6); 1092 1093 /* 1094 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1095 * ACTLR formats could differ across CPUs and therefore would have to 1096 * be trapped for virtualization anyway. 1097 */ 1098 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1099 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1100 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1101 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1102 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1103 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1104 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1105 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1106 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1107 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1108 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1109 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1110 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1111 info->reg_id_pfr0, boot->reg_id_pfr0); 1112 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1113 info->reg_id_pfr1, boot->reg_id_pfr1); 1114 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1115 info->reg_id_pfr2, boot->reg_id_pfr2); 1116 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1117 info->reg_mvfr0, boot->reg_mvfr0); 1118 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1119 info->reg_mvfr1, boot->reg_mvfr1); 1120 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1121 info->reg_mvfr2, boot->reg_mvfr2); 1122 1123 return taint; 1124 } 1125 1126 /* 1127 * Update system wide CPU feature registers with the values from a 1128 * non-boot CPU. Also performs SANITY checks to make sure that there 1129 * aren't any insane variations from that of the boot CPU. 1130 */ 1131 void update_cpu_features(int cpu, 1132 struct cpuinfo_arm64 *info, 1133 struct cpuinfo_arm64 *boot) 1134 { 1135 int taint = 0; 1136 1137 /* 1138 * The kernel can handle differing I-cache policies, but otherwise 1139 * caches should look identical. Userspace JITs will make use of 1140 * *minLine. 1141 */ 1142 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1143 info->reg_ctr, boot->reg_ctr); 1144 1145 /* 1146 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1147 * could result in too much or too little memory being zeroed if a 1148 * process is preempted and migrated between CPUs. 1149 */ 1150 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1151 info->reg_dczid, boot->reg_dczid); 1152 1153 /* If different, timekeeping will be broken (especially with KVM) */ 1154 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1155 info->reg_cntfrq, boot->reg_cntfrq); 1156 1157 /* 1158 * The kernel uses self-hosted debug features and expects CPUs to 1159 * support identical debug features. We presently need CTX_CMPs, WRPs, 1160 * and BRPs to be identical. 1161 * ID_AA64DFR1 is currently RES0. 1162 */ 1163 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1164 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1165 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1166 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1167 /* 1168 * Even in big.LITTLE, processors should be identical instruction-set 1169 * wise. 1170 */ 1171 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1172 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1173 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1174 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1175 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1176 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1177 1178 /* 1179 * Differing PARange support is fine as long as all peripherals and 1180 * memory are mapped within the minimum PARange of all CPUs. 1181 * Linux should not care about secure memory. 1182 */ 1183 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1184 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1185 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1186 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1187 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1188 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1189 1190 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1191 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1192 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1193 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1194 1195 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1196 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1197 1198 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 1199 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1200 info->reg_zcr, boot->reg_zcr); 1201 1202 /* Probe vector lengths, unless we already gave up on SVE */ 1203 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 1204 !system_capabilities_finalized()) 1205 vec_update_vq_map(ARM64_VEC_SVE); 1206 } 1207 1208 /* 1209 * The kernel uses the LDGM/STGM instructions and the number of tags 1210 * they read/write depends on the GMID_EL1.BS field. Check that the 1211 * value is the same on all CPUs. 1212 */ 1213 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1214 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1215 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1216 info->reg_gmid, boot->reg_gmid); 1217 } 1218 1219 /* 1220 * If we don't have AArch32 at all then skip the checks entirely 1221 * as the register values may be UNKNOWN and we're not going to be 1222 * using them for anything. 1223 * 1224 * This relies on a sanitised view of the AArch64 ID registers 1225 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1226 */ 1227 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1228 lazy_init_32bit_cpu_features(info, boot); 1229 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1230 &boot->aarch32); 1231 } 1232 1233 /* 1234 * Mismatched CPU features are a recipe for disaster. Don't even 1235 * pretend to support them. 1236 */ 1237 if (taint) { 1238 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1239 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1240 } 1241 } 1242 1243 u64 read_sanitised_ftr_reg(u32 id) 1244 { 1245 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1246 1247 if (!regp) 1248 return 0; 1249 return regp->sys_val; 1250 } 1251 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1252 1253 #define read_sysreg_case(r) \ 1254 case r: val = read_sysreg_s(r); break; 1255 1256 /* 1257 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1258 * Read the system register on the current CPU 1259 */ 1260 u64 __read_sysreg_by_encoding(u32 sys_id) 1261 { 1262 struct arm64_ftr_reg *regp; 1263 u64 val; 1264 1265 switch (sys_id) { 1266 read_sysreg_case(SYS_ID_PFR0_EL1); 1267 read_sysreg_case(SYS_ID_PFR1_EL1); 1268 read_sysreg_case(SYS_ID_PFR2_EL1); 1269 read_sysreg_case(SYS_ID_DFR0_EL1); 1270 read_sysreg_case(SYS_ID_DFR1_EL1); 1271 read_sysreg_case(SYS_ID_MMFR0_EL1); 1272 read_sysreg_case(SYS_ID_MMFR1_EL1); 1273 read_sysreg_case(SYS_ID_MMFR2_EL1); 1274 read_sysreg_case(SYS_ID_MMFR3_EL1); 1275 read_sysreg_case(SYS_ID_MMFR4_EL1); 1276 read_sysreg_case(SYS_ID_MMFR5_EL1); 1277 read_sysreg_case(SYS_ID_ISAR0_EL1); 1278 read_sysreg_case(SYS_ID_ISAR1_EL1); 1279 read_sysreg_case(SYS_ID_ISAR2_EL1); 1280 read_sysreg_case(SYS_ID_ISAR3_EL1); 1281 read_sysreg_case(SYS_ID_ISAR4_EL1); 1282 read_sysreg_case(SYS_ID_ISAR5_EL1); 1283 read_sysreg_case(SYS_ID_ISAR6_EL1); 1284 read_sysreg_case(SYS_MVFR0_EL1); 1285 read_sysreg_case(SYS_MVFR1_EL1); 1286 read_sysreg_case(SYS_MVFR2_EL1); 1287 1288 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1289 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1290 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1291 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1292 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1293 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1294 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1295 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1296 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1297 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1298 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1299 1300 read_sysreg_case(SYS_CNTFRQ_EL0); 1301 read_sysreg_case(SYS_CTR_EL0); 1302 read_sysreg_case(SYS_DCZID_EL0); 1303 1304 default: 1305 BUG(); 1306 return 0; 1307 } 1308 1309 regp = get_arm64_ftr_reg(sys_id); 1310 if (regp) { 1311 val &= ~regp->override->mask; 1312 val |= (regp->override->val & regp->override->mask); 1313 } 1314 1315 return val; 1316 } 1317 1318 #include <linux/irqchip/arm-gic-v3.h> 1319 1320 static bool 1321 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1322 { 1323 int val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1324 entry->field_width, 1325 entry->sign); 1326 1327 return val >= entry->min_field_value; 1328 } 1329 1330 static bool 1331 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1332 { 1333 u64 val; 1334 1335 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1336 if (scope == SCOPE_SYSTEM) 1337 val = read_sanitised_ftr_reg(entry->sys_reg); 1338 else 1339 val = __read_sysreg_by_encoding(entry->sys_reg); 1340 1341 return feature_matches(val, entry); 1342 } 1343 1344 const struct cpumask *system_32bit_el0_cpumask(void) 1345 { 1346 if (!system_supports_32bit_el0()) 1347 return cpu_none_mask; 1348 1349 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1350 return cpu_32bit_el0_mask; 1351 1352 return cpu_possible_mask; 1353 } 1354 1355 static int __init parse_32bit_el0_param(char *str) 1356 { 1357 allow_mismatched_32bit_el0 = true; 1358 return 0; 1359 } 1360 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1361 1362 static ssize_t aarch32_el0_show(struct device *dev, 1363 struct device_attribute *attr, char *buf) 1364 { 1365 const struct cpumask *mask = system_32bit_el0_cpumask(); 1366 1367 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1368 } 1369 static const DEVICE_ATTR_RO(aarch32_el0); 1370 1371 static int __init aarch32_el0_sysfs_init(void) 1372 { 1373 if (!allow_mismatched_32bit_el0) 1374 return 0; 1375 1376 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0); 1377 } 1378 device_initcall(aarch32_el0_sysfs_init); 1379 1380 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1381 { 1382 if (!has_cpuid_feature(entry, scope)) 1383 return allow_mismatched_32bit_el0; 1384 1385 if (scope == SCOPE_SYSTEM) 1386 pr_info("detected: 32-bit EL0 Support\n"); 1387 1388 return true; 1389 } 1390 1391 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1392 { 1393 bool has_sre; 1394 1395 if (!has_cpuid_feature(entry, scope)) 1396 return false; 1397 1398 has_sre = gic_enable_sre(); 1399 if (!has_sre) 1400 pr_warn_once("%s present but disabled by higher exception level\n", 1401 entry->desc); 1402 1403 return has_sre; 1404 } 1405 1406 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1407 { 1408 u32 midr = read_cpuid_id(); 1409 1410 /* Cavium ThunderX pass 1.x and 2.x */ 1411 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1412 MIDR_CPU_VAR_REV(0, 0), 1413 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1414 } 1415 1416 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1417 { 1418 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1419 1420 return cpuid_feature_extract_signed_field(pfr0, 1421 ID_AA64PFR0_FP_SHIFT) < 0; 1422 } 1423 1424 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1425 int scope) 1426 { 1427 u64 ctr; 1428 1429 if (scope == SCOPE_SYSTEM) 1430 ctr = arm64_ftr_reg_ctrel0.sys_val; 1431 else 1432 ctr = read_cpuid_effective_cachetype(); 1433 1434 return ctr & BIT(CTR_IDC_SHIFT); 1435 } 1436 1437 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1438 { 1439 /* 1440 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1441 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1442 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1443 * value. 1444 */ 1445 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 1446 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1447 } 1448 1449 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1450 int scope) 1451 { 1452 u64 ctr; 1453 1454 if (scope == SCOPE_SYSTEM) 1455 ctr = arm64_ftr_reg_ctrel0.sys_val; 1456 else 1457 ctr = read_cpuid_cachetype(); 1458 1459 return ctr & BIT(CTR_DIC_SHIFT); 1460 } 1461 1462 static bool __maybe_unused 1463 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1464 { 1465 /* 1466 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1467 * may share TLB entries with a CPU stuck in the crashed 1468 * kernel. 1469 */ 1470 if (is_kdump_kernel()) 1471 return false; 1472 1473 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1474 return false; 1475 1476 return has_cpuid_feature(entry, scope); 1477 } 1478 1479 /* 1480 * This check is triggered during the early boot before the cpufeature 1481 * is initialised. Checking the status on the local CPU allows the boot 1482 * CPU to detect the need for non-global mappings and thus avoiding a 1483 * pagetable re-write after all the CPUs are booted. This check will be 1484 * anyway run on individual CPUs, allowing us to get the consistent 1485 * state once the SMP CPUs are up and thus make the switch to non-global 1486 * mappings if required. 1487 */ 1488 bool kaslr_requires_kpti(void) 1489 { 1490 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1491 return false; 1492 1493 /* 1494 * E0PD does a similar job to KPTI so can be used instead 1495 * where available. 1496 */ 1497 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1498 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1499 if (cpuid_feature_extract_unsigned_field(mmfr2, 1500 ID_AA64MMFR2_E0PD_SHIFT)) 1501 return false; 1502 } 1503 1504 /* 1505 * Systems affected by Cavium erratum 24756 are incompatible 1506 * with KPTI. 1507 */ 1508 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1509 extern const struct midr_range cavium_erratum_27456_cpus[]; 1510 1511 if (is_midr_in_range_list(read_cpuid_id(), 1512 cavium_erratum_27456_cpus)) 1513 return false; 1514 } 1515 1516 return kaslr_offset() > 0; 1517 } 1518 1519 static bool __meltdown_safe = true; 1520 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1521 1522 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1523 int scope) 1524 { 1525 /* List of CPUs that are not vulnerable and don't need KPTI */ 1526 static const struct midr_range kpti_safe_list[] = { 1527 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1528 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1529 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1530 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1531 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1532 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1533 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1534 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1535 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1536 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1537 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1538 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1539 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1540 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1541 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1542 { /* sentinel */ } 1543 }; 1544 char const *str = "kpti command line option"; 1545 bool meltdown_safe; 1546 1547 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1548 1549 /* Defer to CPU feature registers */ 1550 if (has_cpuid_feature(entry, scope)) 1551 meltdown_safe = true; 1552 1553 if (!meltdown_safe) 1554 __meltdown_safe = false; 1555 1556 /* 1557 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1558 * ThunderX leads to apparent I-cache corruption of kernel text, which 1559 * ends as well as you might imagine. Don't even try. We cannot rely 1560 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1561 * because cpucap detection order may change. However, since we know 1562 * affected CPUs are always in a homogeneous configuration, it is 1563 * safe to rely on this_cpu_has_cap() here. 1564 */ 1565 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1566 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1567 __kpti_forced = -1; 1568 } 1569 1570 /* Useful for KASLR robustness */ 1571 if (kaslr_requires_kpti()) { 1572 if (!__kpti_forced) { 1573 str = "KASLR"; 1574 __kpti_forced = 1; 1575 } 1576 } 1577 1578 if (cpu_mitigations_off() && !__kpti_forced) { 1579 str = "mitigations=off"; 1580 __kpti_forced = -1; 1581 } 1582 1583 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1584 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1585 return false; 1586 } 1587 1588 /* Forced? */ 1589 if (__kpti_forced) { 1590 pr_info_once("kernel page table isolation forced %s by %s\n", 1591 __kpti_forced > 0 ? "ON" : "OFF", str); 1592 return __kpti_forced > 0; 1593 } 1594 1595 return !meltdown_safe; 1596 } 1597 1598 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1599 static void __nocfi 1600 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1601 { 1602 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1603 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1604 kpti_remap_fn *remap_fn; 1605 1606 int cpu = smp_processor_id(); 1607 1608 if (__this_cpu_read(this_cpu_vector) == vectors) { 1609 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1610 1611 __this_cpu_write(this_cpu_vector, v); 1612 } 1613 1614 /* 1615 * We don't need to rewrite the page-tables if either we've done 1616 * it already or we have KASLR enabled and therefore have not 1617 * created any global mappings at all. 1618 */ 1619 if (arm64_use_ng_mappings) 1620 return; 1621 1622 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings)); 1623 1624 cpu_install_idmap(); 1625 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1626 cpu_uninstall_idmap(); 1627 1628 if (!cpu) 1629 arm64_use_ng_mappings = true; 1630 } 1631 #else 1632 static void 1633 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1634 { 1635 } 1636 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1637 1638 static int __init parse_kpti(char *str) 1639 { 1640 bool enabled; 1641 int ret = strtobool(str, &enabled); 1642 1643 if (ret) 1644 return ret; 1645 1646 __kpti_forced = enabled ? 1 : -1; 1647 return 0; 1648 } 1649 early_param("kpti", parse_kpti); 1650 1651 #ifdef CONFIG_ARM64_HW_AFDBM 1652 static inline void __cpu_enable_hw_dbm(void) 1653 { 1654 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1655 1656 write_sysreg(tcr, tcr_el1); 1657 isb(); 1658 local_flush_tlb_all(); 1659 } 1660 1661 static bool cpu_has_broken_dbm(void) 1662 { 1663 /* List of CPUs which have broken DBM support. */ 1664 static const struct midr_range cpus[] = { 1665 #ifdef CONFIG_ARM64_ERRATUM_1024718 1666 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1667 /* Kryo4xx Silver (rdpe => r1p0) */ 1668 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1669 #endif 1670 #ifdef CONFIG_ARM64_ERRATUM_2051678 1671 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1672 #endif 1673 {}, 1674 }; 1675 1676 return is_midr_in_range_list(read_cpuid_id(), cpus); 1677 } 1678 1679 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1680 { 1681 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1682 !cpu_has_broken_dbm(); 1683 } 1684 1685 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1686 { 1687 if (cpu_can_use_dbm(cap)) 1688 __cpu_enable_hw_dbm(); 1689 } 1690 1691 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1692 int __unused) 1693 { 1694 static bool detected = false; 1695 /* 1696 * DBM is a non-conflicting feature. i.e, the kernel can safely 1697 * run a mix of CPUs with and without the feature. So, we 1698 * unconditionally enable the capability to allow any late CPU 1699 * to use the feature. We only enable the control bits on the 1700 * CPU, if it actually supports. 1701 * 1702 * We have to make sure we print the "feature" detection only 1703 * when at least one CPU actually uses it. So check if this CPU 1704 * can actually use it and print the message exactly once. 1705 * 1706 * This is safe as all CPUs (including secondary CPUs - due to the 1707 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1708 * goes through the "matches" check exactly once. Also if a CPU 1709 * matches the criteria, it is guaranteed that the CPU will turn 1710 * the DBM on, as the capability is unconditionally enabled. 1711 */ 1712 if (!detected && cpu_can_use_dbm(cap)) { 1713 detected = true; 1714 pr_info("detected: Hardware dirty bit management\n"); 1715 } 1716 1717 return true; 1718 } 1719 1720 #endif 1721 1722 #ifdef CONFIG_ARM64_AMU_EXTN 1723 1724 /* 1725 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1726 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1727 * information regarding all the events that it supports. When a CPU bit is 1728 * set in the cpumask, the user of this feature can only rely on the presence 1729 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1730 * counters are enabled or access to these counters is enabled by code 1731 * executed at higher exception levels (firmware). 1732 */ 1733 static struct cpumask amu_cpus __read_mostly; 1734 1735 bool cpu_has_amu_feat(int cpu) 1736 { 1737 return cpumask_test_cpu(cpu, &amu_cpus); 1738 } 1739 1740 int get_cpu_with_amu_feat(void) 1741 { 1742 return cpumask_any(&amu_cpus); 1743 } 1744 1745 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1746 { 1747 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1748 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1749 smp_processor_id()); 1750 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1751 update_freq_counters_refs(); 1752 } 1753 } 1754 1755 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1756 int __unused) 1757 { 1758 /* 1759 * The AMU extension is a non-conflicting feature: the kernel can 1760 * safely run a mix of CPUs with and without support for the 1761 * activity monitors extension. Therefore, unconditionally enable 1762 * the capability to allow any late CPU to use the feature. 1763 * 1764 * With this feature unconditionally enabled, the cpu_enable 1765 * function will be called for all CPUs that match the criteria, 1766 * including secondary and hotplugged, marking this feature as 1767 * present on that respective CPU. The enable function will also 1768 * print a detection message. 1769 */ 1770 1771 return true; 1772 } 1773 #else 1774 int get_cpu_with_amu_feat(void) 1775 { 1776 return nr_cpu_ids; 1777 } 1778 #endif 1779 1780 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1781 { 1782 return is_kernel_in_hyp_mode(); 1783 } 1784 1785 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1786 { 1787 /* 1788 * Copy register values that aren't redirected by hardware. 1789 * 1790 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1791 * this value to tpidr_el2 before we patch the code. Once we've done 1792 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1793 * do anything here. 1794 */ 1795 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1796 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1797 } 1798 1799 #ifdef CONFIG_ARM64_PAN 1800 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1801 { 1802 /* 1803 * We modify PSTATE. This won't work from irq context as the PSTATE 1804 * is discarded once we return from the exception. 1805 */ 1806 WARN_ON_ONCE(in_interrupt()); 1807 1808 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1809 set_pstate_pan(1); 1810 } 1811 #endif /* CONFIG_ARM64_PAN */ 1812 1813 #ifdef CONFIG_ARM64_RAS_EXTN 1814 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1815 { 1816 /* Firmware may have left a deferred SError in this register. */ 1817 write_sysreg_s(0, SYS_DISR_EL1); 1818 } 1819 #endif /* CONFIG_ARM64_RAS_EXTN */ 1820 1821 #ifdef CONFIG_ARM64_PTR_AUTH 1822 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1823 { 1824 int boot_val, sec_val; 1825 1826 /* We don't expect to be called with SCOPE_SYSTEM */ 1827 WARN_ON(scope == SCOPE_SYSTEM); 1828 /* 1829 * The ptr-auth feature levels are not intercompatible with lower 1830 * levels. Hence we must match ptr-auth feature level of the secondary 1831 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1832 * from the sanitised register whereas direct register read is done for 1833 * the secondary CPUs. 1834 * The sanitised feature state is guaranteed to match that of the 1835 * boot CPU as a mismatched secondary CPU is parked before it gets 1836 * a chance to update the state, with the capability. 1837 */ 1838 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1839 entry->field_pos, entry->sign); 1840 if (scope & SCOPE_BOOT_CPU) 1841 return boot_val >= entry->min_field_value; 1842 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 1843 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 1844 entry->field_pos, entry->sign); 1845 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 1846 } 1847 1848 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 1849 int scope) 1850 { 1851 bool api = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 1852 bool apa = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 1853 bool apa3 = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 1854 1855 return apa || apa3 || api; 1856 } 1857 1858 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1859 int __unused) 1860 { 1861 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1862 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 1863 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 1864 1865 return gpa || gpa3 || gpi; 1866 } 1867 #endif /* CONFIG_ARM64_PTR_AUTH */ 1868 1869 #ifdef CONFIG_ARM64_E0PD 1870 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1871 { 1872 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1873 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1874 } 1875 #endif /* CONFIG_ARM64_E0PD */ 1876 1877 #ifdef CONFIG_ARM64_PSEUDO_NMI 1878 static bool enable_pseudo_nmi; 1879 1880 static int __init early_enable_pseudo_nmi(char *p) 1881 { 1882 return strtobool(p, &enable_pseudo_nmi); 1883 } 1884 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1885 1886 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1887 int scope) 1888 { 1889 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1890 } 1891 #endif 1892 1893 #ifdef CONFIG_ARM64_BTI 1894 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 1895 { 1896 /* 1897 * Use of X16/X17 for tail-calls and trampolines that jump to 1898 * function entry points using BR is a requirement for 1899 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 1900 * So, be strict and forbid other BRs using other registers to 1901 * jump onto a PACIxSP instruction: 1902 */ 1903 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 1904 isb(); 1905 } 1906 #endif /* CONFIG_ARM64_BTI */ 1907 1908 #ifdef CONFIG_ARM64_MTE 1909 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 1910 { 1911 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 1912 isb(); 1913 1914 /* 1915 * Clear the tags in the zero page. This needs to be done via the 1916 * linear map which has the Tagged attribute. 1917 */ 1918 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) 1919 mte_clear_page_tags(lm_alias(empty_zero_page)); 1920 1921 kasan_init_hw_tags_cpu(); 1922 } 1923 #endif /* CONFIG_ARM64_MTE */ 1924 1925 #ifdef CONFIG_KVM 1926 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 1927 { 1928 if (kvm_get_mode() != KVM_MODE_PROTECTED) 1929 return false; 1930 1931 if (is_kernel_in_hyp_mode()) { 1932 pr_warn("Protected KVM not available with VHE\n"); 1933 return false; 1934 } 1935 1936 return true; 1937 } 1938 #endif /* CONFIG_KVM */ 1939 1940 /* Internal helper functions to match cpu capability type */ 1941 static bool 1942 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1943 { 1944 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1945 } 1946 1947 static bool 1948 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1949 { 1950 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1951 } 1952 1953 static bool 1954 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 1955 { 1956 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 1957 } 1958 1959 static const struct arm64_cpu_capabilities arm64_features[] = { 1960 { 1961 .desc = "GIC system register CPU interface", 1962 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1963 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1964 .matches = has_useable_gicv3_cpuif, 1965 .sys_reg = SYS_ID_AA64PFR0_EL1, 1966 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1967 .field_width = 4, 1968 .sign = FTR_UNSIGNED, 1969 .min_field_value = 1, 1970 }, 1971 { 1972 .desc = "Enhanced Counter Virtualization", 1973 .capability = ARM64_HAS_ECV, 1974 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1975 .matches = has_cpuid_feature, 1976 .sys_reg = SYS_ID_AA64MMFR0_EL1, 1977 .field_pos = ID_AA64MMFR0_ECV_SHIFT, 1978 .field_width = 4, 1979 .sign = FTR_UNSIGNED, 1980 .min_field_value = 1, 1981 }, 1982 #ifdef CONFIG_ARM64_PAN 1983 { 1984 .desc = "Privileged Access Never", 1985 .capability = ARM64_HAS_PAN, 1986 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1987 .matches = has_cpuid_feature, 1988 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1989 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1990 .field_width = 4, 1991 .sign = FTR_UNSIGNED, 1992 .min_field_value = 1, 1993 .cpu_enable = cpu_enable_pan, 1994 }, 1995 #endif /* CONFIG_ARM64_PAN */ 1996 #ifdef CONFIG_ARM64_EPAN 1997 { 1998 .desc = "Enhanced Privileged Access Never", 1999 .capability = ARM64_HAS_EPAN, 2000 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2001 .matches = has_cpuid_feature, 2002 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2003 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 2004 .field_width = 4, 2005 .sign = FTR_UNSIGNED, 2006 .min_field_value = 3, 2007 }, 2008 #endif /* CONFIG_ARM64_EPAN */ 2009 #ifdef CONFIG_ARM64_LSE_ATOMICS 2010 { 2011 .desc = "LSE atomic instructions", 2012 .capability = ARM64_HAS_LSE_ATOMICS, 2013 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2014 .matches = has_cpuid_feature, 2015 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2016 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 2017 .field_width = 4, 2018 .sign = FTR_UNSIGNED, 2019 .min_field_value = 2, 2020 }, 2021 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2022 { 2023 .desc = "Software prefetching using PRFM", 2024 .capability = ARM64_HAS_NO_HW_PREFETCH, 2025 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2026 .matches = has_no_hw_prefetch, 2027 }, 2028 { 2029 .desc = "Virtualization Host Extensions", 2030 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2031 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2032 .matches = runs_at_el2, 2033 .cpu_enable = cpu_copy_el2regs, 2034 }, 2035 { 2036 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2037 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2038 .matches = has_32bit_el0, 2039 .sys_reg = SYS_ID_AA64PFR0_EL1, 2040 .sign = FTR_UNSIGNED, 2041 .field_pos = ID_AA64PFR0_EL0_SHIFT, 2042 .field_width = 4, 2043 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT, 2044 }, 2045 #ifdef CONFIG_KVM 2046 { 2047 .desc = "32-bit EL1 Support", 2048 .capability = ARM64_HAS_32BIT_EL1, 2049 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2050 .matches = has_cpuid_feature, 2051 .sys_reg = SYS_ID_AA64PFR0_EL1, 2052 .sign = FTR_UNSIGNED, 2053 .field_pos = ID_AA64PFR0_EL1_SHIFT, 2054 .field_width = 4, 2055 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT, 2056 }, 2057 { 2058 .desc = "Protected KVM", 2059 .capability = ARM64_KVM_PROTECTED_MODE, 2060 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2061 .matches = is_kvm_protected_mode, 2062 }, 2063 #endif 2064 { 2065 .desc = "Kernel page table isolation (KPTI)", 2066 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2067 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2068 /* 2069 * The ID feature fields below are used to indicate that 2070 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2071 * more details. 2072 */ 2073 .sys_reg = SYS_ID_AA64PFR0_EL1, 2074 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 2075 .field_width = 4, 2076 .min_field_value = 1, 2077 .matches = unmap_kernel_at_el0, 2078 .cpu_enable = kpti_install_ng_mappings, 2079 }, 2080 { 2081 /* FP/SIMD is not implemented */ 2082 .capability = ARM64_HAS_NO_FPSIMD, 2083 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2084 .min_field_value = 0, 2085 .matches = has_no_fpsimd, 2086 }, 2087 #ifdef CONFIG_ARM64_PMEM 2088 { 2089 .desc = "Data cache clean to Point of Persistence", 2090 .capability = ARM64_HAS_DCPOP, 2091 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2092 .matches = has_cpuid_feature, 2093 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2094 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 2095 .field_width = 4, 2096 .min_field_value = 1, 2097 }, 2098 { 2099 .desc = "Data cache clean to Point of Deep Persistence", 2100 .capability = ARM64_HAS_DCPODP, 2101 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2102 .matches = has_cpuid_feature, 2103 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2104 .sign = FTR_UNSIGNED, 2105 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 2106 .field_width = 4, 2107 .min_field_value = 2, 2108 }, 2109 #endif 2110 #ifdef CONFIG_ARM64_SVE 2111 { 2112 .desc = "Scalable Vector Extension", 2113 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2114 .capability = ARM64_SVE, 2115 .sys_reg = SYS_ID_AA64PFR0_EL1, 2116 .sign = FTR_UNSIGNED, 2117 .field_pos = ID_AA64PFR0_SVE_SHIFT, 2118 .field_width = 4, 2119 .min_field_value = ID_AA64PFR0_SVE, 2120 .matches = has_cpuid_feature, 2121 .cpu_enable = sve_kernel_enable, 2122 }, 2123 #endif /* CONFIG_ARM64_SVE */ 2124 #ifdef CONFIG_ARM64_RAS_EXTN 2125 { 2126 .desc = "RAS Extension Support", 2127 .capability = ARM64_HAS_RAS_EXTN, 2128 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2129 .matches = has_cpuid_feature, 2130 .sys_reg = SYS_ID_AA64PFR0_EL1, 2131 .sign = FTR_UNSIGNED, 2132 .field_pos = ID_AA64PFR0_RAS_SHIFT, 2133 .field_width = 4, 2134 .min_field_value = ID_AA64PFR0_RAS_V1, 2135 .cpu_enable = cpu_clear_disr, 2136 }, 2137 #endif /* CONFIG_ARM64_RAS_EXTN */ 2138 #ifdef CONFIG_ARM64_AMU_EXTN 2139 { 2140 /* 2141 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 2142 * Therefore, don't provide .desc as we don't want the detection 2143 * message to be shown until at least one CPU is detected to 2144 * support the feature. 2145 */ 2146 .capability = ARM64_HAS_AMU_EXTN, 2147 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2148 .matches = has_amu, 2149 .sys_reg = SYS_ID_AA64PFR0_EL1, 2150 .sign = FTR_UNSIGNED, 2151 .field_pos = ID_AA64PFR0_AMU_SHIFT, 2152 .field_width = 4, 2153 .min_field_value = ID_AA64PFR0_AMU, 2154 .cpu_enable = cpu_amu_enable, 2155 }, 2156 #endif /* CONFIG_ARM64_AMU_EXTN */ 2157 { 2158 .desc = "Data cache clean to the PoU not required for I/D coherence", 2159 .capability = ARM64_HAS_CACHE_IDC, 2160 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2161 .matches = has_cache_idc, 2162 .cpu_enable = cpu_emulate_effective_ctr, 2163 }, 2164 { 2165 .desc = "Instruction cache invalidation not required for I/D coherence", 2166 .capability = ARM64_HAS_CACHE_DIC, 2167 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2168 .matches = has_cache_dic, 2169 }, 2170 { 2171 .desc = "Stage-2 Force Write-Back", 2172 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2173 .capability = ARM64_HAS_STAGE2_FWB, 2174 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2175 .sign = FTR_UNSIGNED, 2176 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 2177 .field_width = 4, 2178 .min_field_value = 1, 2179 .matches = has_cpuid_feature, 2180 }, 2181 { 2182 .desc = "ARMv8.4 Translation Table Level", 2183 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2184 .capability = ARM64_HAS_ARMv8_4_TTL, 2185 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2186 .sign = FTR_UNSIGNED, 2187 .field_pos = ID_AA64MMFR2_TTL_SHIFT, 2188 .field_width = 4, 2189 .min_field_value = 1, 2190 .matches = has_cpuid_feature, 2191 }, 2192 { 2193 .desc = "TLB range maintenance instructions", 2194 .capability = ARM64_HAS_TLB_RANGE, 2195 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2196 .matches = has_cpuid_feature, 2197 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2198 .field_pos = ID_AA64ISAR0_TLB_SHIFT, 2199 .field_width = 4, 2200 .sign = FTR_UNSIGNED, 2201 .min_field_value = ID_AA64ISAR0_TLB_RANGE, 2202 }, 2203 #ifdef CONFIG_ARM64_HW_AFDBM 2204 { 2205 /* 2206 * Since we turn this on always, we don't want the user to 2207 * think that the feature is available when it may not be. 2208 * So hide the description. 2209 * 2210 * .desc = "Hardware pagetable Dirty Bit Management", 2211 * 2212 */ 2213 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2214 .capability = ARM64_HW_DBM, 2215 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2216 .sign = FTR_UNSIGNED, 2217 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 2218 .field_width = 4, 2219 .min_field_value = 2, 2220 .matches = has_hw_dbm, 2221 .cpu_enable = cpu_enable_hw_dbm, 2222 }, 2223 #endif 2224 { 2225 .desc = "CRC32 instructions", 2226 .capability = ARM64_HAS_CRC32, 2227 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2228 .matches = has_cpuid_feature, 2229 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2230 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 2231 .field_width = 4, 2232 .min_field_value = 1, 2233 }, 2234 { 2235 .desc = "Speculative Store Bypassing Safe (SSBS)", 2236 .capability = ARM64_SSBS, 2237 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2238 .matches = has_cpuid_feature, 2239 .sys_reg = SYS_ID_AA64PFR1_EL1, 2240 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 2241 .field_width = 4, 2242 .sign = FTR_UNSIGNED, 2243 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 2244 }, 2245 #ifdef CONFIG_ARM64_CNP 2246 { 2247 .desc = "Common not Private translations", 2248 .capability = ARM64_HAS_CNP, 2249 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2250 .matches = has_useable_cnp, 2251 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2252 .sign = FTR_UNSIGNED, 2253 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 2254 .field_width = 4, 2255 .min_field_value = 1, 2256 .cpu_enable = cpu_enable_cnp, 2257 }, 2258 #endif 2259 { 2260 .desc = "Speculation barrier (SB)", 2261 .capability = ARM64_HAS_SB, 2262 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2263 .matches = has_cpuid_feature, 2264 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2265 .field_pos = ID_AA64ISAR1_SB_SHIFT, 2266 .field_width = 4, 2267 .sign = FTR_UNSIGNED, 2268 .min_field_value = 1, 2269 }, 2270 #ifdef CONFIG_ARM64_PTR_AUTH 2271 { 2272 .desc = "Address authentication (architected QARMA5 algorithm)", 2273 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2274 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2275 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2276 .sign = FTR_UNSIGNED, 2277 .field_pos = ID_AA64ISAR1_APA_SHIFT, 2278 .field_width = 4, 2279 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 2280 .matches = has_address_auth_cpucap, 2281 }, 2282 { 2283 .desc = "Address authentication (architected QARMA3 algorithm)", 2284 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2285 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2286 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2287 .sign = FTR_UNSIGNED, 2288 .field_pos = ID_AA64ISAR2_APA3_SHIFT, 2289 .field_width = 4, 2290 .min_field_value = ID_AA64ISAR2_APA3_ARCHITECTED, 2291 .matches = has_address_auth_cpucap, 2292 }, 2293 { 2294 .desc = "Address authentication (IMP DEF algorithm)", 2295 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2296 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2297 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2298 .sign = FTR_UNSIGNED, 2299 .field_pos = ID_AA64ISAR1_API_SHIFT, 2300 .field_width = 4, 2301 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 2302 .matches = has_address_auth_cpucap, 2303 }, 2304 { 2305 .capability = ARM64_HAS_ADDRESS_AUTH, 2306 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2307 .matches = has_address_auth_metacap, 2308 }, 2309 { 2310 .desc = "Generic authentication (architected QARMA5 algorithm)", 2311 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2312 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2313 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2314 .sign = FTR_UNSIGNED, 2315 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 2316 .field_width = 4, 2317 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 2318 .matches = has_cpuid_feature, 2319 }, 2320 { 2321 .desc = "Generic authentication (architected QARMA3 algorithm)", 2322 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2323 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2324 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2325 .sign = FTR_UNSIGNED, 2326 .field_pos = ID_AA64ISAR2_GPA3_SHIFT, 2327 .field_width = 4, 2328 .min_field_value = ID_AA64ISAR2_GPA3_ARCHITECTED, 2329 .matches = has_cpuid_feature, 2330 }, 2331 { 2332 .desc = "Generic authentication (IMP DEF algorithm)", 2333 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2334 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2335 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2336 .sign = FTR_UNSIGNED, 2337 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 2338 .field_width = 4, 2339 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 2340 .matches = has_cpuid_feature, 2341 }, 2342 { 2343 .capability = ARM64_HAS_GENERIC_AUTH, 2344 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2345 .matches = has_generic_auth, 2346 }, 2347 #endif /* CONFIG_ARM64_PTR_AUTH */ 2348 #ifdef CONFIG_ARM64_PSEUDO_NMI 2349 { 2350 /* 2351 * Depends on having GICv3 2352 */ 2353 .desc = "IRQ priority masking", 2354 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2355 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2356 .matches = can_use_gic_priorities, 2357 .sys_reg = SYS_ID_AA64PFR0_EL1, 2358 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2359 .field_width = 4, 2360 .sign = FTR_UNSIGNED, 2361 .min_field_value = 1, 2362 }, 2363 #endif 2364 #ifdef CONFIG_ARM64_E0PD 2365 { 2366 .desc = "E0PD", 2367 .capability = ARM64_HAS_E0PD, 2368 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2369 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2370 .sign = FTR_UNSIGNED, 2371 .field_width = 4, 2372 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2373 .matches = has_cpuid_feature, 2374 .min_field_value = 1, 2375 .cpu_enable = cpu_enable_e0pd, 2376 }, 2377 #endif 2378 #ifdef CONFIG_ARCH_RANDOM 2379 { 2380 .desc = "Random Number Generator", 2381 .capability = ARM64_HAS_RNG, 2382 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2383 .matches = has_cpuid_feature, 2384 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2385 .field_pos = ID_AA64ISAR0_RNDR_SHIFT, 2386 .field_width = 4, 2387 .sign = FTR_UNSIGNED, 2388 .min_field_value = 1, 2389 }, 2390 #endif 2391 #ifdef CONFIG_ARM64_BTI 2392 { 2393 .desc = "Branch Target Identification", 2394 .capability = ARM64_BTI, 2395 #ifdef CONFIG_ARM64_BTI_KERNEL 2396 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2397 #else 2398 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2399 #endif 2400 .matches = has_cpuid_feature, 2401 .cpu_enable = bti_enable, 2402 .sys_reg = SYS_ID_AA64PFR1_EL1, 2403 .field_pos = ID_AA64PFR1_BT_SHIFT, 2404 .field_width = 4, 2405 .min_field_value = ID_AA64PFR1_BT_BTI, 2406 .sign = FTR_UNSIGNED, 2407 }, 2408 #endif 2409 #ifdef CONFIG_ARM64_MTE 2410 { 2411 .desc = "Memory Tagging Extension", 2412 .capability = ARM64_MTE, 2413 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2414 .matches = has_cpuid_feature, 2415 .sys_reg = SYS_ID_AA64PFR1_EL1, 2416 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2417 .field_width = 4, 2418 .min_field_value = ID_AA64PFR1_MTE, 2419 .sign = FTR_UNSIGNED, 2420 .cpu_enable = cpu_enable_mte, 2421 }, 2422 { 2423 .desc = "Asymmetric MTE Tag Check Fault", 2424 .capability = ARM64_MTE_ASYMM, 2425 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2426 .matches = has_cpuid_feature, 2427 .sys_reg = SYS_ID_AA64PFR1_EL1, 2428 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2429 .field_width = 4, 2430 .min_field_value = ID_AA64PFR1_MTE_ASYMM, 2431 .sign = FTR_UNSIGNED, 2432 }, 2433 #endif /* CONFIG_ARM64_MTE */ 2434 { 2435 .desc = "RCpc load-acquire (LDAPR)", 2436 .capability = ARM64_HAS_LDAPR, 2437 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2438 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2439 .sign = FTR_UNSIGNED, 2440 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, 2441 .field_width = 4, 2442 .matches = has_cpuid_feature, 2443 .min_field_value = 1, 2444 }, 2445 {}, 2446 }; 2447 2448 #define HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ 2449 .matches = has_cpuid_feature, \ 2450 .sys_reg = reg, \ 2451 .field_pos = field, \ 2452 .field_width = width, \ 2453 .sign = s, \ 2454 .min_field_value = min_value, 2455 2456 #define __HWCAP_CAP(name, cap_type, cap) \ 2457 .desc = name, \ 2458 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2459 .hwcap_type = cap_type, \ 2460 .hwcap = cap, \ 2461 2462 #define HWCAP_CAP(reg, field, width, s, min_value, cap_type, cap) \ 2463 { \ 2464 __HWCAP_CAP(#cap, cap_type, cap) \ 2465 HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ 2466 } 2467 2468 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2469 { \ 2470 __HWCAP_CAP(#cap, cap_type, cap) \ 2471 .matches = cpucap_multi_entry_cap_matches, \ 2472 .match_list = list, \ 2473 } 2474 2475 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2476 { \ 2477 __HWCAP_CAP(#cap, cap_type, cap) \ 2478 .matches = match, \ 2479 } 2480 2481 #ifdef CONFIG_ARM64_PTR_AUTH 2482 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2483 { 2484 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 2485 4, FTR_UNSIGNED, 2486 ID_AA64ISAR1_APA_ARCHITECTED) 2487 }, 2488 { 2489 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT, 2490 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_ARCHITECTED) 2491 }, 2492 { 2493 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 2494 4, FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 2495 }, 2496 {}, 2497 }; 2498 2499 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2500 { 2501 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 2502 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 2503 }, 2504 { 2505 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT, 2506 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_ARCHITECTED) 2507 }, 2508 { 2509 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 2510 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 2511 }, 2512 {}, 2513 }; 2514 #endif 2515 2516 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2517 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2518 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2519 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2520 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2521 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2522 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2523 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2524 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2525 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2526 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2527 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2528 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2529 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2530 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2531 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2532 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2533 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2534 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2535 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2536 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2537 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2538 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2539 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2540 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2541 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2542 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2543 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2544 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2545 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2546 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2547 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2548 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2549 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2550 #ifdef CONFIG_ARM64_SVE 2551 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2552 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2553 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2554 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2555 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2556 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2557 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2558 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2559 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2560 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2561 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2562 #endif 2563 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2564 #ifdef CONFIG_ARM64_BTI 2565 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2566 #endif 2567 #ifdef CONFIG_ARM64_PTR_AUTH 2568 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2569 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2570 #endif 2571 #ifdef CONFIG_ARM64_MTE 2572 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), 2573 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3), 2574 #endif /* CONFIG_ARM64_MTE */ 2575 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), 2576 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), 2577 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2578 {}, 2579 }; 2580 2581 #ifdef CONFIG_COMPAT 2582 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2583 { 2584 /* 2585 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2586 * in line with that of arm32 as in vfp_init(). We make sure that the 2587 * check is future proof, by making sure value is non-zero. 2588 */ 2589 u32 mvfr1; 2590 2591 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2592 if (scope == SCOPE_SYSTEM) 2593 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2594 else 2595 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2596 2597 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2598 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2599 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2600 } 2601 #endif 2602 2603 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2604 #ifdef CONFIG_COMPAT 2605 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2606 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2607 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2608 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2609 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2610 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2611 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2612 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2613 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2614 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2615 #endif 2616 {}, 2617 }; 2618 2619 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2620 { 2621 switch (cap->hwcap_type) { 2622 case CAP_HWCAP: 2623 cpu_set_feature(cap->hwcap); 2624 break; 2625 #ifdef CONFIG_COMPAT 2626 case CAP_COMPAT_HWCAP: 2627 compat_elf_hwcap |= (u32)cap->hwcap; 2628 break; 2629 case CAP_COMPAT_HWCAP2: 2630 compat_elf_hwcap2 |= (u32)cap->hwcap; 2631 break; 2632 #endif 2633 default: 2634 WARN_ON(1); 2635 break; 2636 } 2637 } 2638 2639 /* Check if we have a particular HWCAP enabled */ 2640 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2641 { 2642 bool rc; 2643 2644 switch (cap->hwcap_type) { 2645 case CAP_HWCAP: 2646 rc = cpu_have_feature(cap->hwcap); 2647 break; 2648 #ifdef CONFIG_COMPAT 2649 case CAP_COMPAT_HWCAP: 2650 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2651 break; 2652 case CAP_COMPAT_HWCAP2: 2653 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2654 break; 2655 #endif 2656 default: 2657 WARN_ON(1); 2658 rc = false; 2659 } 2660 2661 return rc; 2662 } 2663 2664 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2665 { 2666 /* We support emulation of accesses to CPU ID feature registers */ 2667 cpu_set_named_feature(CPUID); 2668 for (; hwcaps->matches; hwcaps++) 2669 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2670 cap_set_elf_hwcap(hwcaps); 2671 } 2672 2673 static void update_cpu_capabilities(u16 scope_mask) 2674 { 2675 int i; 2676 const struct arm64_cpu_capabilities *caps; 2677 2678 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2679 for (i = 0; i < ARM64_NCAPS; i++) { 2680 caps = cpu_hwcaps_ptrs[i]; 2681 if (!caps || !(caps->type & scope_mask) || 2682 cpus_have_cap(caps->capability) || 2683 !caps->matches(caps, cpucap_default_scope(caps))) 2684 continue; 2685 2686 if (caps->desc) 2687 pr_info("detected: %s\n", caps->desc); 2688 cpus_set_cap(caps->capability); 2689 2690 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2691 set_bit(caps->capability, boot_capabilities); 2692 } 2693 } 2694 2695 /* 2696 * Enable all the available capabilities on this CPU. The capabilities 2697 * with BOOT_CPU scope are handled separately and hence skipped here. 2698 */ 2699 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2700 { 2701 int i; 2702 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2703 2704 for_each_available_cap(i) { 2705 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2706 2707 if (WARN_ON(!cap)) 2708 continue; 2709 2710 if (!(cap->type & non_boot_scope)) 2711 continue; 2712 2713 if (cap->cpu_enable) 2714 cap->cpu_enable(cap); 2715 } 2716 return 0; 2717 } 2718 2719 /* 2720 * Run through the enabled capabilities and enable() it on all active 2721 * CPUs 2722 */ 2723 static void __init enable_cpu_capabilities(u16 scope_mask) 2724 { 2725 int i; 2726 const struct arm64_cpu_capabilities *caps; 2727 bool boot_scope; 2728 2729 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2730 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2731 2732 for (i = 0; i < ARM64_NCAPS; i++) { 2733 unsigned int num; 2734 2735 caps = cpu_hwcaps_ptrs[i]; 2736 if (!caps || !(caps->type & scope_mask)) 2737 continue; 2738 num = caps->capability; 2739 if (!cpus_have_cap(num)) 2740 continue; 2741 2742 /* Ensure cpus_have_const_cap(num) works */ 2743 static_branch_enable(&cpu_hwcap_keys[num]); 2744 2745 if (boot_scope && caps->cpu_enable) 2746 /* 2747 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2748 * before any secondary CPU boots. Thus, each secondary 2749 * will enable the capability as appropriate via 2750 * check_local_cpu_capabilities(). The only exception is 2751 * the boot CPU, for which the capability must be 2752 * enabled here. This approach avoids costly 2753 * stop_machine() calls for this case. 2754 */ 2755 caps->cpu_enable(caps); 2756 } 2757 2758 /* 2759 * For all non-boot scope capabilities, use stop_machine() 2760 * as it schedules the work allowing us to modify PSTATE, 2761 * instead of on_each_cpu() which uses an IPI, giving us a 2762 * PSTATE that disappears when we return. 2763 */ 2764 if (!boot_scope) 2765 stop_machine(cpu_enable_non_boot_scope_capabilities, 2766 NULL, cpu_online_mask); 2767 } 2768 2769 /* 2770 * Run through the list of capabilities to check for conflicts. 2771 * If the system has already detected a capability, take necessary 2772 * action on this CPU. 2773 */ 2774 static void verify_local_cpu_caps(u16 scope_mask) 2775 { 2776 int i; 2777 bool cpu_has_cap, system_has_cap; 2778 const struct arm64_cpu_capabilities *caps; 2779 2780 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2781 2782 for (i = 0; i < ARM64_NCAPS; i++) { 2783 caps = cpu_hwcaps_ptrs[i]; 2784 if (!caps || !(caps->type & scope_mask)) 2785 continue; 2786 2787 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2788 system_has_cap = cpus_have_cap(caps->capability); 2789 2790 if (system_has_cap) { 2791 /* 2792 * Check if the new CPU misses an advertised feature, 2793 * which is not safe to miss. 2794 */ 2795 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2796 break; 2797 /* 2798 * We have to issue cpu_enable() irrespective of 2799 * whether the CPU has it or not, as it is enabeld 2800 * system wide. It is upto the call back to take 2801 * appropriate action on this CPU. 2802 */ 2803 if (caps->cpu_enable) 2804 caps->cpu_enable(caps); 2805 } else { 2806 /* 2807 * Check if the CPU has this capability if it isn't 2808 * safe to have when the system doesn't. 2809 */ 2810 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2811 break; 2812 } 2813 } 2814 2815 if (i < ARM64_NCAPS) { 2816 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2817 smp_processor_id(), caps->capability, 2818 caps->desc, system_has_cap, cpu_has_cap); 2819 2820 if (cpucap_panic_on_conflict(caps)) 2821 cpu_panic_kernel(); 2822 else 2823 cpu_die_early(); 2824 } 2825 } 2826 2827 /* 2828 * Check for CPU features that are used in early boot 2829 * based on the Boot CPU value. 2830 */ 2831 static void check_early_cpu_features(void) 2832 { 2833 verify_cpu_asid_bits(); 2834 2835 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2836 } 2837 2838 static void 2839 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2840 { 2841 2842 for (; caps->matches; caps++) 2843 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2844 pr_crit("CPU%d: missing HWCAP: %s\n", 2845 smp_processor_id(), caps->desc); 2846 cpu_die_early(); 2847 } 2848 } 2849 2850 static void verify_local_elf_hwcaps(void) 2851 { 2852 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 2853 2854 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 2855 __verify_local_elf_hwcaps(compat_elf_hwcaps); 2856 } 2857 2858 static void verify_sve_features(void) 2859 { 2860 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2861 u64 zcr = read_zcr_features(); 2862 2863 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2864 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2865 2866 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) { 2867 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2868 smp_processor_id()); 2869 cpu_die_early(); 2870 } 2871 2872 /* Add checks on other ZCR bits here if necessary */ 2873 } 2874 2875 static void verify_hyp_capabilities(void) 2876 { 2877 u64 safe_mmfr1, mmfr0, mmfr1; 2878 int parange, ipa_max; 2879 unsigned int safe_vmid_bits, vmid_bits; 2880 2881 if (!IS_ENABLED(CONFIG_KVM)) 2882 return; 2883 2884 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 2885 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 2886 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 2887 2888 /* Verify VMID bits */ 2889 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 2890 vmid_bits = get_vmid_bits(mmfr1); 2891 if (vmid_bits < safe_vmid_bits) { 2892 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 2893 cpu_die_early(); 2894 } 2895 2896 /* Verify IPA range */ 2897 parange = cpuid_feature_extract_unsigned_field(mmfr0, 2898 ID_AA64MMFR0_PARANGE_SHIFT); 2899 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 2900 if (ipa_max < get_kvm_ipa_limit()) { 2901 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 2902 cpu_die_early(); 2903 } 2904 } 2905 2906 /* 2907 * Run through the enabled system capabilities and enable() it on this CPU. 2908 * The capabilities were decided based on the available CPUs at the boot time. 2909 * Any new CPU should match the system wide status of the capability. If the 2910 * new CPU doesn't have a capability which the system now has enabled, we 2911 * cannot do anything to fix it up and could cause unexpected failures. So 2912 * we park the CPU. 2913 */ 2914 static void verify_local_cpu_capabilities(void) 2915 { 2916 /* 2917 * The capabilities with SCOPE_BOOT_CPU are checked from 2918 * check_early_cpu_features(), as they need to be verified 2919 * on all secondary CPUs. 2920 */ 2921 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2922 verify_local_elf_hwcaps(); 2923 2924 if (system_supports_sve()) 2925 verify_sve_features(); 2926 2927 if (is_hyp_mode_available()) 2928 verify_hyp_capabilities(); 2929 } 2930 2931 void check_local_cpu_capabilities(void) 2932 { 2933 /* 2934 * All secondary CPUs should conform to the early CPU features 2935 * in use by the kernel based on boot CPU. 2936 */ 2937 check_early_cpu_features(); 2938 2939 /* 2940 * If we haven't finalised the system capabilities, this CPU gets 2941 * a chance to update the errata work arounds and local features. 2942 * Otherwise, this CPU should verify that it has all the system 2943 * advertised capabilities. 2944 */ 2945 if (!system_capabilities_finalized()) 2946 update_cpu_capabilities(SCOPE_LOCAL_CPU); 2947 else 2948 verify_local_cpu_capabilities(); 2949 } 2950 2951 static void __init setup_boot_cpu_capabilities(void) 2952 { 2953 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 2954 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 2955 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 2956 enable_cpu_capabilities(SCOPE_BOOT_CPU); 2957 } 2958 2959 bool this_cpu_has_cap(unsigned int n) 2960 { 2961 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 2962 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2963 2964 if (cap) 2965 return cap->matches(cap, SCOPE_LOCAL_CPU); 2966 } 2967 2968 return false; 2969 } 2970 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 2971 2972 /* 2973 * This helper function is used in a narrow window when, 2974 * - The system wide safe registers are set with all the SMP CPUs and, 2975 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 2976 * In all other cases cpus_have_{const_}cap() should be used. 2977 */ 2978 static bool __maybe_unused __system_matches_cap(unsigned int n) 2979 { 2980 if (n < ARM64_NCAPS) { 2981 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2982 2983 if (cap) 2984 return cap->matches(cap, SCOPE_SYSTEM); 2985 } 2986 return false; 2987 } 2988 2989 void cpu_set_feature(unsigned int num) 2990 { 2991 WARN_ON(num >= MAX_CPU_FEATURES); 2992 elf_hwcap |= BIT(num); 2993 } 2994 EXPORT_SYMBOL_GPL(cpu_set_feature); 2995 2996 bool cpu_have_feature(unsigned int num) 2997 { 2998 WARN_ON(num >= MAX_CPU_FEATURES); 2999 return elf_hwcap & BIT(num); 3000 } 3001 EXPORT_SYMBOL_GPL(cpu_have_feature); 3002 3003 unsigned long cpu_get_elf_hwcap(void) 3004 { 3005 /* 3006 * We currently only populate the first 32 bits of AT_HWCAP. Please 3007 * note that for userspace compatibility we guarantee that bits 62 3008 * and 63 will always be returned as 0. 3009 */ 3010 return lower_32_bits(elf_hwcap); 3011 } 3012 3013 unsigned long cpu_get_elf_hwcap2(void) 3014 { 3015 return upper_32_bits(elf_hwcap); 3016 } 3017 3018 static void __init setup_system_capabilities(void) 3019 { 3020 /* 3021 * We have finalised the system-wide safe feature 3022 * registers, finalise the capabilities that depend 3023 * on it. Also enable all the available capabilities, 3024 * that are not enabled already. 3025 */ 3026 update_cpu_capabilities(SCOPE_SYSTEM); 3027 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3028 } 3029 3030 void __init setup_cpu_features(void) 3031 { 3032 u32 cwg; 3033 3034 setup_system_capabilities(); 3035 setup_elf_hwcaps(arm64_elf_hwcaps); 3036 3037 if (system_supports_32bit_el0()) 3038 setup_elf_hwcaps(compat_elf_hwcaps); 3039 3040 if (system_uses_ttbr0_pan()) 3041 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3042 3043 sve_setup(); 3044 minsigstksz_setup(); 3045 3046 /* Advertise that we have computed the system capabilities */ 3047 finalize_system_capabilities(); 3048 3049 /* 3050 * Check for sane CTR_EL0.CWG value. 3051 */ 3052 cwg = cache_type_cwg(); 3053 if (!cwg) 3054 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3055 ARCH_DMA_MINALIGN); 3056 } 3057 3058 static int enable_mismatched_32bit_el0(unsigned int cpu) 3059 { 3060 /* 3061 * The first 32-bit-capable CPU we detected and so can no longer 3062 * be offlined by userspace. -1 indicates we haven't yet onlined 3063 * a 32-bit-capable CPU. 3064 */ 3065 static int lucky_winner = -1; 3066 3067 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3068 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3069 3070 if (cpu_32bit) { 3071 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3072 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3073 } 3074 3075 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3076 return 0; 3077 3078 if (lucky_winner >= 0) 3079 return 0; 3080 3081 /* 3082 * We've detected a mismatch. We need to keep one of our CPUs with 3083 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3084 * every CPU in the system for a 32-bit task. 3085 */ 3086 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3087 cpu_active_mask); 3088 get_cpu_device(lucky_winner)->offline_disabled = true; 3089 setup_elf_hwcaps(compat_elf_hwcaps); 3090 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3091 cpu, lucky_winner); 3092 return 0; 3093 } 3094 3095 static int __init init_32bit_el0_mask(void) 3096 { 3097 if (!allow_mismatched_32bit_el0) 3098 return 0; 3099 3100 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3101 return -ENOMEM; 3102 3103 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3104 "arm64/mismatched_32bit_el0:online", 3105 enable_mismatched_32bit_el0, NULL); 3106 } 3107 subsys_initcall_sync(init_32bit_el0_mask); 3108 3109 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3110 { 3111 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 3112 } 3113 3114 /* 3115 * We emulate only the following system register space. 3116 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 3117 * See Table C5-6 System instruction encodings for System register accesses, 3118 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3119 */ 3120 static inline bool __attribute_const__ is_emulated(u32 id) 3121 { 3122 return (sys_reg_Op0(id) == 0x3 && 3123 sys_reg_CRn(id) == 0x0 && 3124 sys_reg_Op1(id) == 0x0 && 3125 (sys_reg_CRm(id) == 0 || 3126 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 3127 } 3128 3129 /* 3130 * With CRm == 0, reg should be one of : 3131 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3132 */ 3133 static inline int emulate_id_reg(u32 id, u64 *valp) 3134 { 3135 switch (id) { 3136 case SYS_MIDR_EL1: 3137 *valp = read_cpuid_id(); 3138 break; 3139 case SYS_MPIDR_EL1: 3140 *valp = SYS_MPIDR_SAFE_VAL; 3141 break; 3142 case SYS_REVIDR_EL1: 3143 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3144 *valp = 0; 3145 break; 3146 default: 3147 return -EINVAL; 3148 } 3149 3150 return 0; 3151 } 3152 3153 static int emulate_sys_reg(u32 id, u64 *valp) 3154 { 3155 struct arm64_ftr_reg *regp; 3156 3157 if (!is_emulated(id)) 3158 return -EINVAL; 3159 3160 if (sys_reg_CRm(id) == 0) 3161 return emulate_id_reg(id, valp); 3162 3163 regp = get_arm64_ftr_reg_nowarn(id); 3164 if (regp) 3165 *valp = arm64_ftr_reg_user_value(regp); 3166 else 3167 /* 3168 * The untracked registers are either IMPLEMENTATION DEFINED 3169 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3170 */ 3171 *valp = 0; 3172 return 0; 3173 } 3174 3175 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3176 { 3177 int rc; 3178 u64 val; 3179 3180 rc = emulate_sys_reg(sys_reg, &val); 3181 if (!rc) { 3182 pt_regs_write_reg(regs, rt, val); 3183 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3184 } 3185 return rc; 3186 } 3187 3188 static int emulate_mrs(struct pt_regs *regs, u32 insn) 3189 { 3190 u32 sys_reg, rt; 3191 3192 /* 3193 * sys_reg values are defined as used in mrs/msr instruction. 3194 * shift the imm value to get the encoding. 3195 */ 3196 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3197 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3198 return do_emulate_mrs(regs, sys_reg, rt); 3199 } 3200 3201 static struct undef_hook mrs_hook = { 3202 .instr_mask = 0xffff0000, 3203 .instr_val = 0xd5380000, 3204 .pstate_mask = PSR_AA32_MODE_MASK, 3205 .pstate_val = PSR_MODE_EL0t, 3206 .fn = emulate_mrs, 3207 }; 3208 3209 static int __init enable_mrs_emulation(void) 3210 { 3211 register_undef_hook(&mrs_hook); 3212 return 0; 3213 } 3214 3215 core_initcall(enable_mrs_emulation); 3216 3217 enum mitigation_state arm64_get_meltdown_state(void) 3218 { 3219 if (__meltdown_safe) 3220 return SPECTRE_UNAFFECTED; 3221 3222 if (arm64_kernel_unmapped_at_el0()) 3223 return SPECTRE_MITIGATED; 3224 3225 return SPECTRE_VULNERABLE; 3226 } 3227 3228 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3229 char *buf) 3230 { 3231 switch (arm64_get_meltdown_state()) { 3232 case SPECTRE_UNAFFECTED: 3233 return sprintf(buf, "Not affected\n"); 3234 3235 case SPECTRE_MITIGATED: 3236 return sprintf(buf, "Mitigation: PTI\n"); 3237 3238 default: 3239 return sprintf(buf, "Vulnerable\n"); 3240 } 3241 } 3242