1 /* 2 * Contains CPU feature definitions 3 * 4 * Copyright (C) 2015 ARM Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #define pr_fmt(fmt) "CPU features: " fmt 20 21 #include <linux/bsearch.h> 22 #include <linux/cpumask.h> 23 #include <linux/sort.h> 24 #include <linux/stop_machine.h> 25 #include <linux/types.h> 26 #include <linux/mm.h> 27 #include <asm/cpu.h> 28 #include <asm/cpufeature.h> 29 #include <asm/cpu_ops.h> 30 #include <asm/mmu_context.h> 31 #include <asm/processor.h> 32 #include <asm/sysreg.h> 33 #include <asm/traps.h> 34 #include <asm/virt.h> 35 36 unsigned long elf_hwcap __read_mostly; 37 EXPORT_SYMBOL_GPL(elf_hwcap); 38 39 #ifdef CONFIG_COMPAT 40 #define COMPAT_ELF_HWCAP_DEFAULT \ 41 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 42 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 43 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ 44 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ 45 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ 46 COMPAT_HWCAP_LPAE) 47 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 48 unsigned int compat_elf_hwcap2 __read_mostly; 49 #endif 50 51 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 52 EXPORT_SYMBOL(cpu_hwcaps); 53 54 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p) 55 { 56 /* file-wide pr_fmt adds "CPU features: " prefix */ 57 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 58 return 0; 59 } 60 61 static struct notifier_block cpu_hwcaps_notifier = { 62 .notifier_call = dump_cpu_hwcaps 63 }; 64 65 static int __init register_cpu_hwcaps_dumper(void) 66 { 67 atomic_notifier_chain_register(&panic_notifier_list, 68 &cpu_hwcaps_notifier); 69 return 0; 70 } 71 __initcall(register_cpu_hwcaps_dumper); 72 73 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 74 EXPORT_SYMBOL(cpu_hwcap_keys); 75 76 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 77 { \ 78 .sign = SIGNED, \ 79 .visible = VISIBLE, \ 80 .strict = STRICT, \ 81 .type = TYPE, \ 82 .shift = SHIFT, \ 83 .width = WIDTH, \ 84 .safe_val = SAFE_VAL, \ 85 } 86 87 /* Define a feature with unsigned values */ 88 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 89 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 90 91 /* Define a feature with a signed value */ 92 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 93 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 94 95 #define ARM64_FTR_END \ 96 { \ 97 .width = 0, \ 98 } 99 100 /* meta feature for alternatives */ 101 static bool __maybe_unused 102 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused); 103 104 105 /* 106 * NOTE: Any changes to the visibility of features should be kept in 107 * sync with the documentation of the CPU feature register ABI. 108 */ 109 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 110 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 111 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 112 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 113 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 114 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 115 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 116 ARM64_FTR_END, 117 }; 118 119 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 120 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 121 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 122 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 123 ARM64_FTR_END, 124 }; 125 126 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 127 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0), 128 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 129 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 130 /* Linux doesn't care about the EL3 */ 131 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0), 132 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0), 133 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 134 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 135 ARM64_FTR_END, 136 }; 137 138 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 139 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 140 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 141 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 142 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 143 /* Linux shouldn't care about secure memory */ 144 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 145 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 146 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 147 /* 148 * Differing PARange is fine as long as all peripherals and memory are mapped 149 * within the minimum PARange of all CPUs 150 */ 151 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 152 ARM64_FTR_END, 153 }; 154 155 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 156 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 157 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 158 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 159 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 160 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 161 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 162 ARM64_FTR_END, 163 }; 164 165 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 166 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 167 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 169 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 170 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 171 ARM64_FTR_END, 172 }; 173 174 static const struct arm64_ftr_bits ftr_ctr[] = { 175 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */ 176 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */ 177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */ 178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */ 179 /* 180 * Linux can handle differing I-cache policies. Userspace JITs will 181 * make use of *minLine. 182 * If we have differing I-cache policies, report it as the weakest - VIPT. 183 */ 184 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */ 186 ARM64_FTR_END, 187 }; 188 189 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 190 .name = "SYS_CTR_EL0", 191 .ftr_bits = ftr_ctr 192 }; 193 194 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 195 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */ 196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */ 197 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */ 198 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */ 199 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */ 200 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */ 201 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */ 202 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */ 203 ARM64_FTR_END, 204 }; 205 206 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0), 208 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 212 /* 213 * We can instantiate multiple PMU instances with different levels 214 * of support. 215 */ 216 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 219 ARM64_FTR_END, 220 }; 221 222 static const struct arm64_ftr_bits ftr_mvfr2[] = { 223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */ 224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */ 225 ARM64_FTR_END, 226 }; 227 228 static const struct arm64_ftr_bits ftr_dczid[] = { 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */ 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */ 231 ARM64_FTR_END, 232 }; 233 234 235 static const struct arm64_ftr_bits ftr_id_isar5[] = { 236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0), 242 ARM64_FTR_END, 243 }; 244 245 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */ 247 ARM64_FTR_END, 248 }; 249 250 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */ 252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */ 253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */ 254 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */ 255 ARM64_FTR_END, 256 }; 257 258 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 260 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 263 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 264 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 265 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 266 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 267 ARM64_FTR_END, 268 }; 269 270 /* 271 * Common ftr bits for a 32bit register with all hidden, strict 272 * attributes, with 4bit feature fields and a default safe value of 273 * 0. Covers the following 32bit registers: 274 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 275 */ 276 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 282 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 285 ARM64_FTR_END, 286 }; 287 288 /* Table for a single 32bit feature value */ 289 static const struct arm64_ftr_bits ftr_single32[] = { 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 291 ARM64_FTR_END, 292 }; 293 294 static const struct arm64_ftr_bits ftr_raz[] = { 295 ARM64_FTR_END, 296 }; 297 298 #define ARM64_FTR_REG(id, table) { \ 299 .sys_id = id, \ 300 .reg = &(struct arm64_ftr_reg){ \ 301 .name = #id, \ 302 .ftr_bits = &((table)[0]), \ 303 }} 304 305 static const struct __ftr_reg_entry { 306 u32 sys_id; 307 struct arm64_ftr_reg *reg; 308 } arm64_ftr_regs[] = { 309 310 /* Op1 = 0, CRn = 0, CRm = 1 */ 311 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 312 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits), 313 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 314 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 315 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 316 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 317 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 318 319 /* Op1 = 0, CRn = 0, CRm = 2 */ 320 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits), 321 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 322 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 323 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 324 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits), 325 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 326 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 327 328 /* Op1 = 0, CRn = 0, CRm = 3 */ 329 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 330 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 331 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 332 333 /* Op1 = 0, CRn = 0, CRm = 4 */ 334 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 335 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz), 336 337 /* Op1 = 0, CRn = 0, CRm = 5 */ 338 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 339 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 340 341 /* Op1 = 0, CRn = 0, CRm = 6 */ 342 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 343 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), 344 345 /* Op1 = 0, CRn = 0, CRm = 7 */ 346 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 347 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), 348 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 349 350 /* Op1 = 3, CRn = 0, CRm = 0 */ 351 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 352 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 353 354 /* Op1 = 3, CRn = 14, CRm = 0 */ 355 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 356 }; 357 358 static int search_cmp_ftr_reg(const void *id, const void *regp) 359 { 360 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 361 } 362 363 /* 364 * get_arm64_ftr_reg - Lookup a feature register entry using its 365 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the 366 * ascending order of sys_id , we use binary search to find a matching 367 * entry. 368 * 369 * returns - Upon success, matching ftr_reg entry for id. 370 * - NULL on failure. It is upto the caller to decide 371 * the impact of a failure. 372 */ 373 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 374 { 375 const struct __ftr_reg_entry *ret; 376 377 ret = bsearch((const void *)(unsigned long)sys_id, 378 arm64_ftr_regs, 379 ARRAY_SIZE(arm64_ftr_regs), 380 sizeof(arm64_ftr_regs[0]), 381 search_cmp_ftr_reg); 382 if (ret) 383 return ret->reg; 384 return NULL; 385 } 386 387 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 388 s64 ftr_val) 389 { 390 u64 mask = arm64_ftr_mask(ftrp); 391 392 reg &= ~mask; 393 reg |= (ftr_val << ftrp->shift) & mask; 394 return reg; 395 } 396 397 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 398 s64 cur) 399 { 400 s64 ret = 0; 401 402 switch (ftrp->type) { 403 case FTR_EXACT: 404 ret = ftrp->safe_val; 405 break; 406 case FTR_LOWER_SAFE: 407 ret = new < cur ? new : cur; 408 break; 409 case FTR_HIGHER_SAFE: 410 ret = new > cur ? new : cur; 411 break; 412 default: 413 BUG(); 414 } 415 416 return ret; 417 } 418 419 static void __init sort_ftr_regs(void) 420 { 421 int i; 422 423 /* Check that the array is sorted so that we can do the binary search */ 424 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++) 425 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 426 } 427 428 /* 429 * Initialise the CPU feature register from Boot CPU values. 430 * Also initiliases the strict_mask for the register. 431 * Any bits that are not covered by an arm64_ftr_bits entry are considered 432 * RES0 for the system-wide value, and must strictly match. 433 */ 434 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 435 { 436 u64 val = 0; 437 u64 strict_mask = ~0x0ULL; 438 u64 user_mask = 0; 439 u64 valid_mask = 0; 440 441 const struct arm64_ftr_bits *ftrp; 442 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 443 444 BUG_ON(!reg); 445 446 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 447 u64 ftr_mask = arm64_ftr_mask(ftrp); 448 s64 ftr_new = arm64_ftr_value(ftrp, new); 449 450 val = arm64_ftr_set_value(ftrp, val, ftr_new); 451 452 valid_mask |= ftr_mask; 453 if (!ftrp->strict) 454 strict_mask &= ~ftr_mask; 455 if (ftrp->visible) 456 user_mask |= ftr_mask; 457 else 458 reg->user_val = arm64_ftr_set_value(ftrp, 459 reg->user_val, 460 ftrp->safe_val); 461 } 462 463 val &= valid_mask; 464 465 reg->sys_val = val; 466 reg->strict_mask = strict_mask; 467 reg->user_mask = user_mask; 468 } 469 470 void __init init_cpu_features(struct cpuinfo_arm64 *info) 471 { 472 /* Before we start using the tables, make sure it is sorted */ 473 sort_ftr_regs(); 474 475 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 476 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 477 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 478 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 479 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 480 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 481 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 482 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 483 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 484 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 485 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 486 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 487 488 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 489 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 490 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 491 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 492 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 493 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 494 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 495 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 496 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 497 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 498 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 499 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 500 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 501 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 502 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 503 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 504 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 505 } 506 507 } 508 509 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 510 { 511 const struct arm64_ftr_bits *ftrp; 512 513 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 514 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 515 s64 ftr_new = arm64_ftr_value(ftrp, new); 516 517 if (ftr_cur == ftr_new) 518 continue; 519 /* Find a safe value */ 520 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 521 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 522 } 523 524 } 525 526 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 527 { 528 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 529 530 BUG_ON(!regp); 531 update_cpu_ftr_reg(regp, val); 532 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 533 return 0; 534 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 535 regp->name, boot, cpu, val); 536 return 1; 537 } 538 539 /* 540 * Update system wide CPU feature registers with the values from a 541 * non-boot CPU. Also performs SANITY checks to make sure that there 542 * aren't any insane variations from that of the boot CPU. 543 */ 544 void update_cpu_features(int cpu, 545 struct cpuinfo_arm64 *info, 546 struct cpuinfo_arm64 *boot) 547 { 548 int taint = 0; 549 550 /* 551 * The kernel can handle differing I-cache policies, but otherwise 552 * caches should look identical. Userspace JITs will make use of 553 * *minLine. 554 */ 555 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 556 info->reg_ctr, boot->reg_ctr); 557 558 /* 559 * Userspace may perform DC ZVA instructions. Mismatched block sizes 560 * could result in too much or too little memory being zeroed if a 561 * process is preempted and migrated between CPUs. 562 */ 563 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 564 info->reg_dczid, boot->reg_dczid); 565 566 /* If different, timekeeping will be broken (especially with KVM) */ 567 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 568 info->reg_cntfrq, boot->reg_cntfrq); 569 570 /* 571 * The kernel uses self-hosted debug features and expects CPUs to 572 * support identical debug features. We presently need CTX_CMPs, WRPs, 573 * and BRPs to be identical. 574 * ID_AA64DFR1 is currently RES0. 575 */ 576 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 577 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 578 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 579 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 580 /* 581 * Even in big.LITTLE, processors should be identical instruction-set 582 * wise. 583 */ 584 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 585 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 586 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 587 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 588 589 /* 590 * Differing PARange support is fine as long as all peripherals and 591 * memory are mapped within the minimum PARange of all CPUs. 592 * Linux should not care about secure memory. 593 */ 594 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 595 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 596 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 597 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 598 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 599 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 600 601 /* 602 * EL3 is not our concern. 603 * ID_AA64PFR1 is currently RES0. 604 */ 605 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 606 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 607 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 608 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 609 610 /* 611 * If we have AArch32, we care about 32-bit features for compat. 612 * If the system doesn't support AArch32, don't update them. 613 */ 614 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 615 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 616 617 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 618 info->reg_id_dfr0, boot->reg_id_dfr0); 619 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 620 info->reg_id_isar0, boot->reg_id_isar0); 621 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 622 info->reg_id_isar1, boot->reg_id_isar1); 623 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 624 info->reg_id_isar2, boot->reg_id_isar2); 625 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 626 info->reg_id_isar3, boot->reg_id_isar3); 627 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 628 info->reg_id_isar4, boot->reg_id_isar4); 629 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 630 info->reg_id_isar5, boot->reg_id_isar5); 631 632 /* 633 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 634 * ACTLR formats could differ across CPUs and therefore would have to 635 * be trapped for virtualization anyway. 636 */ 637 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 638 info->reg_id_mmfr0, boot->reg_id_mmfr0); 639 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 640 info->reg_id_mmfr1, boot->reg_id_mmfr1); 641 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 642 info->reg_id_mmfr2, boot->reg_id_mmfr2); 643 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 644 info->reg_id_mmfr3, boot->reg_id_mmfr3); 645 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 646 info->reg_id_pfr0, boot->reg_id_pfr0); 647 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 648 info->reg_id_pfr1, boot->reg_id_pfr1); 649 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 650 info->reg_mvfr0, boot->reg_mvfr0); 651 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 652 info->reg_mvfr1, boot->reg_mvfr1); 653 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 654 info->reg_mvfr2, boot->reg_mvfr2); 655 } 656 657 /* 658 * Mismatched CPU features are a recipe for disaster. Don't even 659 * pretend to support them. 660 */ 661 if (taint) { 662 pr_warn_once("Unsupported CPU feature variation detected.\n"); 663 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 664 } 665 } 666 667 u64 read_sanitised_ftr_reg(u32 id) 668 { 669 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 670 671 /* We shouldn't get a request for an unsupported register */ 672 BUG_ON(!regp); 673 return regp->sys_val; 674 } 675 676 #define read_sysreg_case(r) \ 677 case r: return read_sysreg_s(r) 678 679 /* 680 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 681 * Read the system register on the current CPU 682 */ 683 static u64 __read_sysreg_by_encoding(u32 sys_id) 684 { 685 switch (sys_id) { 686 read_sysreg_case(SYS_ID_PFR0_EL1); 687 read_sysreg_case(SYS_ID_PFR1_EL1); 688 read_sysreg_case(SYS_ID_DFR0_EL1); 689 read_sysreg_case(SYS_ID_MMFR0_EL1); 690 read_sysreg_case(SYS_ID_MMFR1_EL1); 691 read_sysreg_case(SYS_ID_MMFR2_EL1); 692 read_sysreg_case(SYS_ID_MMFR3_EL1); 693 read_sysreg_case(SYS_ID_ISAR0_EL1); 694 read_sysreg_case(SYS_ID_ISAR1_EL1); 695 read_sysreg_case(SYS_ID_ISAR2_EL1); 696 read_sysreg_case(SYS_ID_ISAR3_EL1); 697 read_sysreg_case(SYS_ID_ISAR4_EL1); 698 read_sysreg_case(SYS_ID_ISAR5_EL1); 699 read_sysreg_case(SYS_MVFR0_EL1); 700 read_sysreg_case(SYS_MVFR1_EL1); 701 read_sysreg_case(SYS_MVFR2_EL1); 702 703 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 704 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 705 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 706 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 707 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 708 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 709 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 710 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 711 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 712 713 read_sysreg_case(SYS_CNTFRQ_EL0); 714 read_sysreg_case(SYS_CTR_EL0); 715 read_sysreg_case(SYS_DCZID_EL0); 716 717 default: 718 BUG(); 719 return 0; 720 } 721 } 722 723 #include <linux/irqchip/arm-gic-v3.h> 724 725 static bool 726 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 727 { 728 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 729 730 return val >= entry->min_field_value; 731 } 732 733 static bool 734 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 735 { 736 u64 val; 737 738 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 739 if (scope == SCOPE_SYSTEM) 740 val = read_sanitised_ftr_reg(entry->sys_reg); 741 else 742 val = __read_sysreg_by_encoding(entry->sys_reg); 743 744 return feature_matches(val, entry); 745 } 746 747 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 748 { 749 bool has_sre; 750 751 if (!has_cpuid_feature(entry, scope)) 752 return false; 753 754 has_sre = gic_enable_sre(); 755 if (!has_sre) 756 pr_warn_once("%s present but disabled by higher exception level\n", 757 entry->desc); 758 759 return has_sre; 760 } 761 762 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 763 { 764 u32 midr = read_cpuid_id(); 765 766 /* Cavium ThunderX pass 1.x and 2.x */ 767 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, 768 MIDR_CPU_VAR_REV(0, 0), 769 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 770 } 771 772 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 773 { 774 return is_kernel_in_hyp_mode(); 775 } 776 777 static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry, 778 int __unused) 779 { 780 phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start); 781 782 /* 783 * Activate the lower HYP offset only if: 784 * - the idmap doesn't clash with it, 785 * - the kernel is not running at EL2. 786 */ 787 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode(); 788 } 789 790 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 791 { 792 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 793 794 return cpuid_feature_extract_signed_field(pfr0, 795 ID_AA64PFR0_FP_SHIFT) < 0; 796 } 797 798 static const struct arm64_cpu_capabilities arm64_features[] = { 799 { 800 .desc = "GIC system register CPU interface", 801 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 802 .def_scope = SCOPE_SYSTEM, 803 .matches = has_useable_gicv3_cpuif, 804 .sys_reg = SYS_ID_AA64PFR0_EL1, 805 .field_pos = ID_AA64PFR0_GIC_SHIFT, 806 .sign = FTR_UNSIGNED, 807 .min_field_value = 1, 808 }, 809 #ifdef CONFIG_ARM64_PAN 810 { 811 .desc = "Privileged Access Never", 812 .capability = ARM64_HAS_PAN, 813 .def_scope = SCOPE_SYSTEM, 814 .matches = has_cpuid_feature, 815 .sys_reg = SYS_ID_AA64MMFR1_EL1, 816 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 817 .sign = FTR_UNSIGNED, 818 .min_field_value = 1, 819 .enable = cpu_enable_pan, 820 }, 821 #endif /* CONFIG_ARM64_PAN */ 822 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS) 823 { 824 .desc = "LSE atomic instructions", 825 .capability = ARM64_HAS_LSE_ATOMICS, 826 .def_scope = SCOPE_SYSTEM, 827 .matches = has_cpuid_feature, 828 .sys_reg = SYS_ID_AA64ISAR0_EL1, 829 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 830 .sign = FTR_UNSIGNED, 831 .min_field_value = 2, 832 }, 833 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */ 834 { 835 .desc = "Software prefetching using PRFM", 836 .capability = ARM64_HAS_NO_HW_PREFETCH, 837 .def_scope = SCOPE_SYSTEM, 838 .matches = has_no_hw_prefetch, 839 }, 840 #ifdef CONFIG_ARM64_UAO 841 { 842 .desc = "User Access Override", 843 .capability = ARM64_HAS_UAO, 844 .def_scope = SCOPE_SYSTEM, 845 .matches = has_cpuid_feature, 846 .sys_reg = SYS_ID_AA64MMFR2_EL1, 847 .field_pos = ID_AA64MMFR2_UAO_SHIFT, 848 .min_field_value = 1, 849 /* 850 * We rely on stop_machine() calling uao_thread_switch() to set 851 * UAO immediately after patching. 852 */ 853 }, 854 #endif /* CONFIG_ARM64_UAO */ 855 #ifdef CONFIG_ARM64_PAN 856 { 857 .capability = ARM64_ALT_PAN_NOT_UAO, 858 .def_scope = SCOPE_SYSTEM, 859 .matches = cpufeature_pan_not_uao, 860 }, 861 #endif /* CONFIG_ARM64_PAN */ 862 { 863 .desc = "Virtualization Host Extensions", 864 .capability = ARM64_HAS_VIRT_HOST_EXTN, 865 .def_scope = SCOPE_SYSTEM, 866 .matches = runs_at_el2, 867 }, 868 { 869 .desc = "32-bit EL0 Support", 870 .capability = ARM64_HAS_32BIT_EL0, 871 .def_scope = SCOPE_SYSTEM, 872 .matches = has_cpuid_feature, 873 .sys_reg = SYS_ID_AA64PFR0_EL1, 874 .sign = FTR_UNSIGNED, 875 .field_pos = ID_AA64PFR0_EL0_SHIFT, 876 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 877 }, 878 { 879 .desc = "Reduced HYP mapping offset", 880 .capability = ARM64_HYP_OFFSET_LOW, 881 .def_scope = SCOPE_SYSTEM, 882 .matches = hyp_offset_low, 883 }, 884 { 885 /* FP/SIMD is not implemented */ 886 .capability = ARM64_HAS_NO_FPSIMD, 887 .def_scope = SCOPE_SYSTEM, 888 .min_field_value = 0, 889 .matches = has_no_fpsimd, 890 }, 891 {}, 892 }; 893 894 #define HWCAP_CAP(reg, field, s, min_value, type, cap) \ 895 { \ 896 .desc = #cap, \ 897 .def_scope = SCOPE_SYSTEM, \ 898 .matches = has_cpuid_feature, \ 899 .sys_reg = reg, \ 900 .field_pos = field, \ 901 .sign = s, \ 902 .min_field_value = min_value, \ 903 .hwcap_type = type, \ 904 .hwcap = cap, \ 905 } 906 907 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 908 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL), 909 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES), 910 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1), 911 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2), 912 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32), 913 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS), 914 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM), 915 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP), 916 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP), 917 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD), 918 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP), 919 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT), 920 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), 921 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC), 922 {}, 923 }; 924 925 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 926 #ifdef CONFIG_COMPAT 927 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 928 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 929 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 930 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 931 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 932 #endif 933 {}, 934 }; 935 936 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 937 { 938 switch (cap->hwcap_type) { 939 case CAP_HWCAP: 940 elf_hwcap |= cap->hwcap; 941 break; 942 #ifdef CONFIG_COMPAT 943 case CAP_COMPAT_HWCAP: 944 compat_elf_hwcap |= (u32)cap->hwcap; 945 break; 946 case CAP_COMPAT_HWCAP2: 947 compat_elf_hwcap2 |= (u32)cap->hwcap; 948 break; 949 #endif 950 default: 951 WARN_ON(1); 952 break; 953 } 954 } 955 956 /* Check if we have a particular HWCAP enabled */ 957 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 958 { 959 bool rc; 960 961 switch (cap->hwcap_type) { 962 case CAP_HWCAP: 963 rc = (elf_hwcap & cap->hwcap) != 0; 964 break; 965 #ifdef CONFIG_COMPAT 966 case CAP_COMPAT_HWCAP: 967 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 968 break; 969 case CAP_COMPAT_HWCAP2: 970 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 971 break; 972 #endif 973 default: 974 WARN_ON(1); 975 rc = false; 976 } 977 978 return rc; 979 } 980 981 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 982 { 983 /* We support emulation of accesses to CPU ID feature registers */ 984 elf_hwcap |= HWCAP_CPUID; 985 for (; hwcaps->matches; hwcaps++) 986 if (hwcaps->matches(hwcaps, hwcaps->def_scope)) 987 cap_set_elf_hwcap(hwcaps); 988 } 989 990 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, 991 const char *info) 992 { 993 for (; caps->matches; caps++) { 994 if (!caps->matches(caps, caps->def_scope)) 995 continue; 996 997 if (!cpus_have_cap(caps->capability) && caps->desc) 998 pr_info("%s %s\n", info, caps->desc); 999 cpus_set_cap(caps->capability); 1000 } 1001 } 1002 1003 /* 1004 * Run through the enabled capabilities and enable() it on all active 1005 * CPUs 1006 */ 1007 void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) 1008 { 1009 for (; caps->matches; caps++) { 1010 unsigned int num = caps->capability; 1011 1012 if (!cpus_have_cap(num)) 1013 continue; 1014 1015 /* Ensure cpus_have_const_cap(num) works */ 1016 static_branch_enable(&cpu_hwcap_keys[num]); 1017 1018 if (caps->enable) { 1019 /* 1020 * Use stop_machine() as it schedules the work allowing 1021 * us to modify PSTATE, instead of on_each_cpu() which 1022 * uses an IPI, giving us a PSTATE that disappears when 1023 * we return. 1024 */ 1025 stop_machine(caps->enable, NULL, cpu_online_mask); 1026 } 1027 } 1028 } 1029 1030 /* 1031 * Flag to indicate if we have computed the system wide 1032 * capabilities based on the boot time active CPUs. This 1033 * will be used to determine if a new booting CPU should 1034 * go through the verification process to make sure that it 1035 * supports the system capabilities, without using a hotplug 1036 * notifier. 1037 */ 1038 static bool sys_caps_initialised; 1039 1040 static inline void set_sys_caps_initialised(void) 1041 { 1042 sys_caps_initialised = true; 1043 } 1044 1045 /* 1046 * Check for CPU features that are used in early boot 1047 * based on the Boot CPU value. 1048 */ 1049 static void check_early_cpu_features(void) 1050 { 1051 verify_cpu_run_el(); 1052 verify_cpu_asid_bits(); 1053 } 1054 1055 static void 1056 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 1057 { 1058 1059 for (; caps->matches; caps++) 1060 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 1061 pr_crit("CPU%d: missing HWCAP: %s\n", 1062 smp_processor_id(), caps->desc); 1063 cpu_die_early(); 1064 } 1065 } 1066 1067 static void 1068 verify_local_cpu_features(const struct arm64_cpu_capabilities *caps) 1069 { 1070 for (; caps->matches; caps++) { 1071 if (!cpus_have_cap(caps->capability)) 1072 continue; 1073 /* 1074 * If the new CPU misses an advertised feature, we cannot proceed 1075 * further, park the cpu. 1076 */ 1077 if (!caps->matches(caps, SCOPE_LOCAL_CPU)) { 1078 pr_crit("CPU%d: missing feature: %s\n", 1079 smp_processor_id(), caps->desc); 1080 cpu_die_early(); 1081 } 1082 if (caps->enable) 1083 caps->enable(NULL); 1084 } 1085 } 1086 1087 /* 1088 * Run through the enabled system capabilities and enable() it on this CPU. 1089 * The capabilities were decided based on the available CPUs at the boot time. 1090 * Any new CPU should match the system wide status of the capability. If the 1091 * new CPU doesn't have a capability which the system now has enabled, we 1092 * cannot do anything to fix it up and could cause unexpected failures. So 1093 * we park the CPU. 1094 */ 1095 static void verify_local_cpu_capabilities(void) 1096 { 1097 verify_local_cpu_errata_workarounds(); 1098 verify_local_cpu_features(arm64_features); 1099 verify_local_elf_hwcaps(arm64_elf_hwcaps); 1100 if (system_supports_32bit_el0()) 1101 verify_local_elf_hwcaps(compat_elf_hwcaps); 1102 } 1103 1104 void check_local_cpu_capabilities(void) 1105 { 1106 /* 1107 * All secondary CPUs should conform to the early CPU features 1108 * in use by the kernel based on boot CPU. 1109 */ 1110 check_early_cpu_features(); 1111 1112 /* 1113 * If we haven't finalised the system capabilities, this CPU gets 1114 * a chance to update the errata work arounds. 1115 * Otherwise, this CPU should verify that it has all the system 1116 * advertised capabilities. 1117 */ 1118 if (!sys_caps_initialised) 1119 update_cpu_errata_workarounds(); 1120 else 1121 verify_local_cpu_capabilities(); 1122 } 1123 1124 static void __init setup_feature_capabilities(void) 1125 { 1126 update_cpu_capabilities(arm64_features, "detected feature:"); 1127 enable_cpu_capabilities(arm64_features); 1128 } 1129 1130 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 1131 EXPORT_SYMBOL(arm64_const_caps_ready); 1132 1133 static void __init mark_const_caps_ready(void) 1134 { 1135 static_branch_enable(&arm64_const_caps_ready); 1136 } 1137 1138 /* 1139 * Check if the current CPU has a given feature capability. 1140 * Should be called from non-preemptible context. 1141 */ 1142 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array, 1143 unsigned int cap) 1144 { 1145 const struct arm64_cpu_capabilities *caps; 1146 1147 if (WARN_ON(preemptible())) 1148 return false; 1149 1150 for (caps = cap_array; caps->desc; caps++) 1151 if (caps->capability == cap && caps->matches) 1152 return caps->matches(caps, SCOPE_LOCAL_CPU); 1153 1154 return false; 1155 } 1156 1157 extern const struct arm64_cpu_capabilities arm64_errata[]; 1158 1159 bool this_cpu_has_cap(unsigned int cap) 1160 { 1161 return (__this_cpu_has_cap(arm64_features, cap) || 1162 __this_cpu_has_cap(arm64_errata, cap)); 1163 } 1164 1165 void __init setup_cpu_features(void) 1166 { 1167 u32 cwg; 1168 int cls; 1169 1170 /* Set the CPU feature capabilies */ 1171 setup_feature_capabilities(); 1172 enable_errata_workarounds(); 1173 mark_const_caps_ready(); 1174 setup_elf_hwcaps(arm64_elf_hwcaps); 1175 1176 if (system_supports_32bit_el0()) 1177 setup_elf_hwcaps(compat_elf_hwcaps); 1178 1179 /* Advertise that we have computed the system capabilities */ 1180 set_sys_caps_initialised(); 1181 1182 /* 1183 * Check for sane CTR_EL0.CWG value. 1184 */ 1185 cwg = cache_type_cwg(); 1186 cls = cache_line_size(); 1187 if (!cwg) 1188 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", 1189 cls); 1190 if (L1_CACHE_BYTES < cls) 1191 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", 1192 L1_CACHE_BYTES, cls); 1193 } 1194 1195 static bool __maybe_unused 1196 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) 1197 { 1198 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO)); 1199 } 1200 1201 /* 1202 * We emulate only the following system register space. 1203 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 1204 * See Table C5-6 System instruction encodings for System register accesses, 1205 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 1206 */ 1207 static inline bool __attribute_const__ is_emulated(u32 id) 1208 { 1209 return (sys_reg_Op0(id) == 0x3 && 1210 sys_reg_CRn(id) == 0x0 && 1211 sys_reg_Op1(id) == 0x0 && 1212 (sys_reg_CRm(id) == 0 || 1213 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 1214 } 1215 1216 /* 1217 * With CRm == 0, reg should be one of : 1218 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 1219 */ 1220 static inline int emulate_id_reg(u32 id, u64 *valp) 1221 { 1222 switch (id) { 1223 case SYS_MIDR_EL1: 1224 *valp = read_cpuid_id(); 1225 break; 1226 case SYS_MPIDR_EL1: 1227 *valp = SYS_MPIDR_SAFE_VAL; 1228 break; 1229 case SYS_REVIDR_EL1: 1230 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 1231 *valp = 0; 1232 break; 1233 default: 1234 return -EINVAL; 1235 } 1236 1237 return 0; 1238 } 1239 1240 static int emulate_sys_reg(u32 id, u64 *valp) 1241 { 1242 struct arm64_ftr_reg *regp; 1243 1244 if (!is_emulated(id)) 1245 return -EINVAL; 1246 1247 if (sys_reg_CRm(id) == 0) 1248 return emulate_id_reg(id, valp); 1249 1250 regp = get_arm64_ftr_reg(id); 1251 if (regp) 1252 *valp = arm64_ftr_reg_user_value(regp); 1253 else 1254 /* 1255 * The untracked registers are either IMPLEMENTATION DEFINED 1256 * (e.g, ID_AFR0_EL1) or reserved RAZ. 1257 */ 1258 *valp = 0; 1259 return 0; 1260 } 1261 1262 static int emulate_mrs(struct pt_regs *regs, u32 insn) 1263 { 1264 int rc; 1265 u32 sys_reg, dst; 1266 u64 val; 1267 1268 /* 1269 * sys_reg values are defined as used in mrs/msr instruction. 1270 * shift the imm value to get the encoding. 1271 */ 1272 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 1273 rc = emulate_sys_reg(sys_reg, &val); 1274 if (!rc) { 1275 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 1276 pt_regs_write_reg(regs, dst, val); 1277 regs->pc += 4; 1278 } 1279 1280 return rc; 1281 } 1282 1283 static struct undef_hook mrs_hook = { 1284 .instr_mask = 0xfff00000, 1285 .instr_val = 0xd5300000, 1286 .pstate_mask = COMPAT_PSR_MODE_MASK, 1287 .pstate_val = PSR_MODE_EL0t, 1288 .fn = emulate_mrs, 1289 }; 1290 1291 static int __init enable_mrs_emulation(void) 1292 { 1293 register_undef_hook(&mrs_hook); 1294 return 0; 1295 } 1296 1297 late_initcall(enable_mrs_emulation); 1298