1 /* 2 * Contains CPU feature definitions 3 * 4 * Copyright (C) 2015 ARM Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #define pr_fmt(fmt) "CPU features: " fmt 20 21 #include <linux/bsearch.h> 22 #include <linux/cpumask.h> 23 #include <linux/sort.h> 24 #include <linux/stop_machine.h> 25 #include <linux/types.h> 26 #include <linux/mm.h> 27 #include <asm/cpu.h> 28 #include <asm/cpufeature.h> 29 #include <asm/cpu_ops.h> 30 #include <asm/mmu_context.h> 31 #include <asm/processor.h> 32 #include <asm/sysreg.h> 33 #include <asm/traps.h> 34 #include <asm/virt.h> 35 36 unsigned long elf_hwcap __read_mostly; 37 EXPORT_SYMBOL_GPL(elf_hwcap); 38 39 #ifdef CONFIG_COMPAT 40 #define COMPAT_ELF_HWCAP_DEFAULT \ 41 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 42 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 43 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ 44 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ 45 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ 46 COMPAT_HWCAP_LPAE) 47 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 48 unsigned int compat_elf_hwcap2 __read_mostly; 49 #endif 50 51 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 52 EXPORT_SYMBOL(cpu_hwcaps); 53 54 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 55 EXPORT_SYMBOL(cpu_hwcap_keys); 56 57 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 58 { \ 59 .sign = SIGNED, \ 60 .visible = VISIBLE, \ 61 .strict = STRICT, \ 62 .type = TYPE, \ 63 .shift = SHIFT, \ 64 .width = WIDTH, \ 65 .safe_val = SAFE_VAL, \ 66 } 67 68 /* Define a feature with unsigned values */ 69 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 70 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 71 72 /* Define a feature with a signed value */ 73 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 74 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 75 76 #define ARM64_FTR_END \ 77 { \ 78 .width = 0, \ 79 } 80 81 /* meta feature for alternatives */ 82 static bool __maybe_unused 83 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused); 84 85 86 /* 87 * NOTE: Any changes to the visibility of features should be kept in 88 * sync with the documentation of the CPU feature register ABI. 89 */ 90 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 91 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 92 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 93 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 94 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 95 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 96 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 97 ARM64_FTR_END, 98 }; 99 100 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 101 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0), 102 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 103 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 104 /* Linux doesn't care about the EL3 */ 105 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0), 106 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0), 107 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 108 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 109 ARM64_FTR_END, 110 }; 111 112 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 113 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 114 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 115 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 116 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 117 /* Linux shouldn't care about secure memory */ 118 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 119 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 120 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 121 /* 122 * Differing PARange is fine as long as all peripherals and memory are mapped 123 * within the minimum PARange of all CPUs 124 */ 125 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 126 ARM64_FTR_END, 127 }; 128 129 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 130 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 131 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 132 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 133 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 134 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 135 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 136 ARM64_FTR_END, 137 }; 138 139 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 140 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 141 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 142 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 143 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 144 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 145 ARM64_FTR_END, 146 }; 147 148 static const struct arm64_ftr_bits ftr_ctr[] = { 149 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */ 150 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */ 151 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */ 152 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */ 153 /* 154 * Linux can handle differing I-cache policies. Userspace JITs will 155 * make use of *minLine. 156 * If we have differing I-cache policies, report it as the weakest - AIVIVT. 157 */ 158 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_AIVIVT), /* L1Ip */ 159 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */ 160 ARM64_FTR_END, 161 }; 162 163 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 164 .name = "SYS_CTR_EL0", 165 .ftr_bits = ftr_ctr 166 }; 167 168 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 169 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */ 170 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */ 171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */ 172 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */ 173 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */ 174 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */ 175 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */ 176 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */ 177 ARM64_FTR_END, 178 }; 179 180 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 181 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0), 182 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 183 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 184 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 185 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 186 /* 187 * We can instantiate multiple PMU instances with different levels 188 * of support. 189 */ 190 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), 192 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 193 ARM64_FTR_END, 194 }; 195 196 static const struct arm64_ftr_bits ftr_mvfr2[] = { 197 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */ 198 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */ 199 ARM64_FTR_END, 200 }; 201 202 static const struct arm64_ftr_bits ftr_dczid[] = { 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */ 204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */ 205 ARM64_FTR_END, 206 }; 207 208 209 static const struct arm64_ftr_bits ftr_id_isar5[] = { 210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0), 216 ARM64_FTR_END, 217 }; 218 219 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */ 221 ARM64_FTR_END, 222 }; 223 224 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */ 226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */ 227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */ 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */ 229 ARM64_FTR_END, 230 }; 231 232 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 234 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ 235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 241 ARM64_FTR_END, 242 }; 243 244 /* 245 * Common ftr bits for a 32bit register with all hidden, strict 246 * attributes, with 4bit feature fields and a default safe value of 247 * 0. Covers the following 32bit registers: 248 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 249 */ 250 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 254 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 255 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 257 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 259 ARM64_FTR_END, 260 }; 261 262 /* Table for a single 32bit feature value */ 263 static const struct arm64_ftr_bits ftr_single32[] = { 264 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 265 ARM64_FTR_END, 266 }; 267 268 static const struct arm64_ftr_bits ftr_raz[] = { 269 ARM64_FTR_END, 270 }; 271 272 #define ARM64_FTR_REG(id, table) { \ 273 .sys_id = id, \ 274 .reg = &(struct arm64_ftr_reg){ \ 275 .name = #id, \ 276 .ftr_bits = &((table)[0]), \ 277 }} 278 279 static const struct __ftr_reg_entry { 280 u32 sys_id; 281 struct arm64_ftr_reg *reg; 282 } arm64_ftr_regs[] = { 283 284 /* Op1 = 0, CRn = 0, CRm = 1 */ 285 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 286 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits), 287 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 288 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 289 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 290 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 291 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 292 293 /* Op1 = 0, CRn = 0, CRm = 2 */ 294 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits), 295 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 296 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 297 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 298 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits), 299 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 300 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 301 302 /* Op1 = 0, CRn = 0, CRm = 3 */ 303 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 304 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 305 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 306 307 /* Op1 = 0, CRn = 0, CRm = 4 */ 308 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 309 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz), 310 311 /* Op1 = 0, CRn = 0, CRm = 5 */ 312 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 313 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 314 315 /* Op1 = 0, CRn = 0, CRm = 6 */ 316 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 317 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_raz), 318 319 /* Op1 = 0, CRn = 0, CRm = 7 */ 320 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 321 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), 322 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 323 324 /* Op1 = 3, CRn = 0, CRm = 0 */ 325 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 326 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 327 328 /* Op1 = 3, CRn = 14, CRm = 0 */ 329 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 330 }; 331 332 static int search_cmp_ftr_reg(const void *id, const void *regp) 333 { 334 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 335 } 336 337 /* 338 * get_arm64_ftr_reg - Lookup a feature register entry using its 339 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the 340 * ascending order of sys_id , we use binary search to find a matching 341 * entry. 342 * 343 * returns - Upon success, matching ftr_reg entry for id. 344 * - NULL on failure. It is upto the caller to decide 345 * the impact of a failure. 346 */ 347 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 348 { 349 const struct __ftr_reg_entry *ret; 350 351 ret = bsearch((const void *)(unsigned long)sys_id, 352 arm64_ftr_regs, 353 ARRAY_SIZE(arm64_ftr_regs), 354 sizeof(arm64_ftr_regs[0]), 355 search_cmp_ftr_reg); 356 if (ret) 357 return ret->reg; 358 return NULL; 359 } 360 361 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 362 s64 ftr_val) 363 { 364 u64 mask = arm64_ftr_mask(ftrp); 365 366 reg &= ~mask; 367 reg |= (ftr_val << ftrp->shift) & mask; 368 return reg; 369 } 370 371 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 372 s64 cur) 373 { 374 s64 ret = 0; 375 376 switch (ftrp->type) { 377 case FTR_EXACT: 378 ret = ftrp->safe_val; 379 break; 380 case FTR_LOWER_SAFE: 381 ret = new < cur ? new : cur; 382 break; 383 case FTR_HIGHER_SAFE: 384 ret = new > cur ? new : cur; 385 break; 386 default: 387 BUG(); 388 } 389 390 return ret; 391 } 392 393 static void __init sort_ftr_regs(void) 394 { 395 int i; 396 397 /* Check that the array is sorted so that we can do the binary search */ 398 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++) 399 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 400 } 401 402 /* 403 * Initialise the CPU feature register from Boot CPU values. 404 * Also initiliases the strict_mask for the register. 405 * Any bits that are not covered by an arm64_ftr_bits entry are considered 406 * RES0 for the system-wide value, and must strictly match. 407 */ 408 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 409 { 410 u64 val = 0; 411 u64 strict_mask = ~0x0ULL; 412 u64 user_mask = 0; 413 u64 valid_mask = 0; 414 415 const struct arm64_ftr_bits *ftrp; 416 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 417 418 BUG_ON(!reg); 419 420 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 421 u64 ftr_mask = arm64_ftr_mask(ftrp); 422 s64 ftr_new = arm64_ftr_value(ftrp, new); 423 424 val = arm64_ftr_set_value(ftrp, val, ftr_new); 425 426 valid_mask |= ftr_mask; 427 if (!ftrp->strict) 428 strict_mask &= ~ftr_mask; 429 if (ftrp->visible) 430 user_mask |= ftr_mask; 431 else 432 reg->user_val = arm64_ftr_set_value(ftrp, 433 reg->user_val, 434 ftrp->safe_val); 435 } 436 437 val &= valid_mask; 438 439 reg->sys_val = val; 440 reg->strict_mask = strict_mask; 441 reg->user_mask = user_mask; 442 } 443 444 void __init init_cpu_features(struct cpuinfo_arm64 *info) 445 { 446 /* Before we start using the tables, make sure it is sorted */ 447 sort_ftr_regs(); 448 449 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 450 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 451 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 452 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 453 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 454 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 455 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 456 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 457 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 458 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 459 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 460 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 461 462 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 463 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 464 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 465 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 466 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 467 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 468 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 469 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 470 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 471 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 472 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 473 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 474 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 475 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 476 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 477 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 478 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 479 } 480 481 } 482 483 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 484 { 485 const struct arm64_ftr_bits *ftrp; 486 487 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 488 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 489 s64 ftr_new = arm64_ftr_value(ftrp, new); 490 491 if (ftr_cur == ftr_new) 492 continue; 493 /* Find a safe value */ 494 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 495 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 496 } 497 498 } 499 500 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 501 { 502 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 503 504 BUG_ON(!regp); 505 update_cpu_ftr_reg(regp, val); 506 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 507 return 0; 508 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 509 regp->name, boot, cpu, val); 510 return 1; 511 } 512 513 /* 514 * Update system wide CPU feature registers with the values from a 515 * non-boot CPU. Also performs SANITY checks to make sure that there 516 * aren't any insane variations from that of the boot CPU. 517 */ 518 void update_cpu_features(int cpu, 519 struct cpuinfo_arm64 *info, 520 struct cpuinfo_arm64 *boot) 521 { 522 int taint = 0; 523 524 /* 525 * The kernel can handle differing I-cache policies, but otherwise 526 * caches should look identical. Userspace JITs will make use of 527 * *minLine. 528 */ 529 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 530 info->reg_ctr, boot->reg_ctr); 531 532 /* 533 * Userspace may perform DC ZVA instructions. Mismatched block sizes 534 * could result in too much or too little memory being zeroed if a 535 * process is preempted and migrated between CPUs. 536 */ 537 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 538 info->reg_dczid, boot->reg_dczid); 539 540 /* If different, timekeeping will be broken (especially with KVM) */ 541 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 542 info->reg_cntfrq, boot->reg_cntfrq); 543 544 /* 545 * The kernel uses self-hosted debug features and expects CPUs to 546 * support identical debug features. We presently need CTX_CMPs, WRPs, 547 * and BRPs to be identical. 548 * ID_AA64DFR1 is currently RES0. 549 */ 550 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 551 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 552 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 553 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 554 /* 555 * Even in big.LITTLE, processors should be identical instruction-set 556 * wise. 557 */ 558 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 559 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 560 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 561 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 562 563 /* 564 * Differing PARange support is fine as long as all peripherals and 565 * memory are mapped within the minimum PARange of all CPUs. 566 * Linux should not care about secure memory. 567 */ 568 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 569 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 570 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 571 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 572 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 573 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 574 575 /* 576 * EL3 is not our concern. 577 * ID_AA64PFR1 is currently RES0. 578 */ 579 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 580 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 581 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 582 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 583 584 /* 585 * If we have AArch32, we care about 32-bit features for compat. 586 * If the system doesn't support AArch32, don't update them. 587 */ 588 if (id_aa64pfr0_32bit_el0(read_system_reg(SYS_ID_AA64PFR0_EL1)) && 589 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 590 591 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 592 info->reg_id_dfr0, boot->reg_id_dfr0); 593 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 594 info->reg_id_isar0, boot->reg_id_isar0); 595 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 596 info->reg_id_isar1, boot->reg_id_isar1); 597 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 598 info->reg_id_isar2, boot->reg_id_isar2); 599 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 600 info->reg_id_isar3, boot->reg_id_isar3); 601 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 602 info->reg_id_isar4, boot->reg_id_isar4); 603 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 604 info->reg_id_isar5, boot->reg_id_isar5); 605 606 /* 607 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 608 * ACTLR formats could differ across CPUs and therefore would have to 609 * be trapped for virtualization anyway. 610 */ 611 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 612 info->reg_id_mmfr0, boot->reg_id_mmfr0); 613 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 614 info->reg_id_mmfr1, boot->reg_id_mmfr1); 615 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 616 info->reg_id_mmfr2, boot->reg_id_mmfr2); 617 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 618 info->reg_id_mmfr3, boot->reg_id_mmfr3); 619 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 620 info->reg_id_pfr0, boot->reg_id_pfr0); 621 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 622 info->reg_id_pfr1, boot->reg_id_pfr1); 623 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 624 info->reg_mvfr0, boot->reg_mvfr0); 625 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 626 info->reg_mvfr1, boot->reg_mvfr1); 627 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 628 info->reg_mvfr2, boot->reg_mvfr2); 629 } 630 631 /* 632 * Mismatched CPU features are a recipe for disaster. Don't even 633 * pretend to support them. 634 */ 635 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC, 636 "Unsupported CPU feature variation.\n"); 637 } 638 639 u64 read_system_reg(u32 id) 640 { 641 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 642 643 /* We shouldn't get a request for an unsupported register */ 644 BUG_ON(!regp); 645 return regp->sys_val; 646 } 647 648 #define read_sysreg_case(r) \ 649 case r: return read_sysreg_s(r) 650 651 /* 652 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated. 653 * Read the system register on the current CPU 654 */ 655 static u64 __raw_read_system_reg(u32 sys_id) 656 { 657 switch (sys_id) { 658 read_sysreg_case(SYS_ID_PFR0_EL1); 659 read_sysreg_case(SYS_ID_PFR1_EL1); 660 read_sysreg_case(SYS_ID_DFR0_EL1); 661 read_sysreg_case(SYS_ID_MMFR0_EL1); 662 read_sysreg_case(SYS_ID_MMFR1_EL1); 663 read_sysreg_case(SYS_ID_MMFR2_EL1); 664 read_sysreg_case(SYS_ID_MMFR3_EL1); 665 read_sysreg_case(SYS_ID_ISAR0_EL1); 666 read_sysreg_case(SYS_ID_ISAR1_EL1); 667 read_sysreg_case(SYS_ID_ISAR2_EL1); 668 read_sysreg_case(SYS_ID_ISAR3_EL1); 669 read_sysreg_case(SYS_ID_ISAR4_EL1); 670 read_sysreg_case(SYS_ID_ISAR5_EL1); 671 read_sysreg_case(SYS_MVFR0_EL1); 672 read_sysreg_case(SYS_MVFR1_EL1); 673 read_sysreg_case(SYS_MVFR2_EL1); 674 675 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 676 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 677 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 678 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 679 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 680 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 681 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 682 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 683 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 684 685 read_sysreg_case(SYS_CNTFRQ_EL0); 686 read_sysreg_case(SYS_CTR_EL0); 687 read_sysreg_case(SYS_DCZID_EL0); 688 689 default: 690 BUG(); 691 return 0; 692 } 693 } 694 695 #include <linux/irqchip/arm-gic-v3.h> 696 697 static bool 698 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 699 { 700 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 701 702 return val >= entry->min_field_value; 703 } 704 705 static bool 706 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 707 { 708 u64 val; 709 710 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 711 if (scope == SCOPE_SYSTEM) 712 val = read_system_reg(entry->sys_reg); 713 else 714 val = __raw_read_system_reg(entry->sys_reg); 715 716 return feature_matches(val, entry); 717 } 718 719 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 720 { 721 bool has_sre; 722 723 if (!has_cpuid_feature(entry, scope)) 724 return false; 725 726 has_sre = gic_enable_sre(); 727 if (!has_sre) 728 pr_warn_once("%s present but disabled by higher exception level\n", 729 entry->desc); 730 731 return has_sre; 732 } 733 734 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 735 { 736 u32 midr = read_cpuid_id(); 737 738 /* Cavium ThunderX pass 1.x and 2.x */ 739 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, 740 MIDR_CPU_VAR_REV(0, 0), 741 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 742 } 743 744 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 745 { 746 return is_kernel_in_hyp_mode(); 747 } 748 749 static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry, 750 int __unused) 751 { 752 phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start); 753 754 /* 755 * Activate the lower HYP offset only if: 756 * - the idmap doesn't clash with it, 757 * - the kernel is not running at EL2. 758 */ 759 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode(); 760 } 761 762 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 763 { 764 u64 pfr0 = read_system_reg(SYS_ID_AA64PFR0_EL1); 765 766 return cpuid_feature_extract_signed_field(pfr0, 767 ID_AA64PFR0_FP_SHIFT) < 0; 768 } 769 770 static const struct arm64_cpu_capabilities arm64_features[] = { 771 { 772 .desc = "GIC system register CPU interface", 773 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 774 .def_scope = SCOPE_SYSTEM, 775 .matches = has_useable_gicv3_cpuif, 776 .sys_reg = SYS_ID_AA64PFR0_EL1, 777 .field_pos = ID_AA64PFR0_GIC_SHIFT, 778 .sign = FTR_UNSIGNED, 779 .min_field_value = 1, 780 }, 781 #ifdef CONFIG_ARM64_PAN 782 { 783 .desc = "Privileged Access Never", 784 .capability = ARM64_HAS_PAN, 785 .def_scope = SCOPE_SYSTEM, 786 .matches = has_cpuid_feature, 787 .sys_reg = SYS_ID_AA64MMFR1_EL1, 788 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 789 .sign = FTR_UNSIGNED, 790 .min_field_value = 1, 791 .enable = cpu_enable_pan, 792 }, 793 #endif /* CONFIG_ARM64_PAN */ 794 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS) 795 { 796 .desc = "LSE atomic instructions", 797 .capability = ARM64_HAS_LSE_ATOMICS, 798 .def_scope = SCOPE_SYSTEM, 799 .matches = has_cpuid_feature, 800 .sys_reg = SYS_ID_AA64ISAR0_EL1, 801 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 802 .sign = FTR_UNSIGNED, 803 .min_field_value = 2, 804 }, 805 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */ 806 { 807 .desc = "Software prefetching using PRFM", 808 .capability = ARM64_HAS_NO_HW_PREFETCH, 809 .def_scope = SCOPE_SYSTEM, 810 .matches = has_no_hw_prefetch, 811 }, 812 #ifdef CONFIG_ARM64_UAO 813 { 814 .desc = "User Access Override", 815 .capability = ARM64_HAS_UAO, 816 .def_scope = SCOPE_SYSTEM, 817 .matches = has_cpuid_feature, 818 .sys_reg = SYS_ID_AA64MMFR2_EL1, 819 .field_pos = ID_AA64MMFR2_UAO_SHIFT, 820 .min_field_value = 1, 821 /* 822 * We rely on stop_machine() calling uao_thread_switch() to set 823 * UAO immediately after patching. 824 */ 825 }, 826 #endif /* CONFIG_ARM64_UAO */ 827 #ifdef CONFIG_ARM64_PAN 828 { 829 .capability = ARM64_ALT_PAN_NOT_UAO, 830 .def_scope = SCOPE_SYSTEM, 831 .matches = cpufeature_pan_not_uao, 832 }, 833 #endif /* CONFIG_ARM64_PAN */ 834 { 835 .desc = "Virtualization Host Extensions", 836 .capability = ARM64_HAS_VIRT_HOST_EXTN, 837 .def_scope = SCOPE_SYSTEM, 838 .matches = runs_at_el2, 839 }, 840 { 841 .desc = "32-bit EL0 Support", 842 .capability = ARM64_HAS_32BIT_EL0, 843 .def_scope = SCOPE_SYSTEM, 844 .matches = has_cpuid_feature, 845 .sys_reg = SYS_ID_AA64PFR0_EL1, 846 .sign = FTR_UNSIGNED, 847 .field_pos = ID_AA64PFR0_EL0_SHIFT, 848 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 849 }, 850 { 851 .desc = "Reduced HYP mapping offset", 852 .capability = ARM64_HYP_OFFSET_LOW, 853 .def_scope = SCOPE_SYSTEM, 854 .matches = hyp_offset_low, 855 }, 856 { 857 /* FP/SIMD is not implemented */ 858 .capability = ARM64_HAS_NO_FPSIMD, 859 .def_scope = SCOPE_SYSTEM, 860 .min_field_value = 0, 861 .matches = has_no_fpsimd, 862 }, 863 {}, 864 }; 865 866 #define HWCAP_CAP(reg, field, s, min_value, type, cap) \ 867 { \ 868 .desc = #cap, \ 869 .def_scope = SCOPE_SYSTEM, \ 870 .matches = has_cpuid_feature, \ 871 .sys_reg = reg, \ 872 .field_pos = field, \ 873 .sign = s, \ 874 .min_field_value = min_value, \ 875 .hwcap_type = type, \ 876 .hwcap = cap, \ 877 } 878 879 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 880 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL), 881 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES), 882 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1), 883 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2), 884 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32), 885 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS), 886 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM), 887 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP), 888 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP), 889 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD), 890 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP), 891 {}, 892 }; 893 894 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 895 #ifdef CONFIG_COMPAT 896 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 897 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 898 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 899 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 900 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 901 #endif 902 {}, 903 }; 904 905 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 906 { 907 switch (cap->hwcap_type) { 908 case CAP_HWCAP: 909 elf_hwcap |= cap->hwcap; 910 break; 911 #ifdef CONFIG_COMPAT 912 case CAP_COMPAT_HWCAP: 913 compat_elf_hwcap |= (u32)cap->hwcap; 914 break; 915 case CAP_COMPAT_HWCAP2: 916 compat_elf_hwcap2 |= (u32)cap->hwcap; 917 break; 918 #endif 919 default: 920 WARN_ON(1); 921 break; 922 } 923 } 924 925 /* Check if we have a particular HWCAP enabled */ 926 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 927 { 928 bool rc; 929 930 switch (cap->hwcap_type) { 931 case CAP_HWCAP: 932 rc = (elf_hwcap & cap->hwcap) != 0; 933 break; 934 #ifdef CONFIG_COMPAT 935 case CAP_COMPAT_HWCAP: 936 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 937 break; 938 case CAP_COMPAT_HWCAP2: 939 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 940 break; 941 #endif 942 default: 943 WARN_ON(1); 944 rc = false; 945 } 946 947 return rc; 948 } 949 950 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 951 { 952 /* We support emulation of accesses to CPU ID feature registers */ 953 elf_hwcap |= HWCAP_CPUID; 954 for (; hwcaps->matches; hwcaps++) 955 if (hwcaps->matches(hwcaps, hwcaps->def_scope)) 956 cap_set_elf_hwcap(hwcaps); 957 } 958 959 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, 960 const char *info) 961 { 962 for (; caps->matches; caps++) { 963 if (!caps->matches(caps, caps->def_scope)) 964 continue; 965 966 if (!cpus_have_cap(caps->capability) && caps->desc) 967 pr_info("%s %s\n", info, caps->desc); 968 cpus_set_cap(caps->capability); 969 } 970 } 971 972 /* 973 * Run through the enabled capabilities and enable() it on all active 974 * CPUs 975 */ 976 void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) 977 { 978 for (; caps->matches; caps++) 979 if (caps->enable && cpus_have_cap(caps->capability)) 980 /* 981 * Use stop_machine() as it schedules the work allowing 982 * us to modify PSTATE, instead of on_each_cpu() which 983 * uses an IPI, giving us a PSTATE that disappears when 984 * we return. 985 */ 986 stop_machine(caps->enable, NULL, cpu_online_mask); 987 } 988 989 /* 990 * Flag to indicate if we have computed the system wide 991 * capabilities based on the boot time active CPUs. This 992 * will be used to determine if a new booting CPU should 993 * go through the verification process to make sure that it 994 * supports the system capabilities, without using a hotplug 995 * notifier. 996 */ 997 static bool sys_caps_initialised; 998 999 static inline void set_sys_caps_initialised(void) 1000 { 1001 sys_caps_initialised = true; 1002 } 1003 1004 /* 1005 * Check for CPU features that are used in early boot 1006 * based on the Boot CPU value. 1007 */ 1008 static void check_early_cpu_features(void) 1009 { 1010 verify_cpu_run_el(); 1011 verify_cpu_asid_bits(); 1012 } 1013 1014 static void 1015 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 1016 { 1017 1018 for (; caps->matches; caps++) 1019 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 1020 pr_crit("CPU%d: missing HWCAP: %s\n", 1021 smp_processor_id(), caps->desc); 1022 cpu_die_early(); 1023 } 1024 } 1025 1026 static void 1027 verify_local_cpu_features(const struct arm64_cpu_capabilities *caps) 1028 { 1029 for (; caps->matches; caps++) { 1030 if (!cpus_have_cap(caps->capability)) 1031 continue; 1032 /* 1033 * If the new CPU misses an advertised feature, we cannot proceed 1034 * further, park the cpu. 1035 */ 1036 if (!caps->matches(caps, SCOPE_LOCAL_CPU)) { 1037 pr_crit("CPU%d: missing feature: %s\n", 1038 smp_processor_id(), caps->desc); 1039 cpu_die_early(); 1040 } 1041 if (caps->enable) 1042 caps->enable(NULL); 1043 } 1044 } 1045 1046 /* 1047 * Run through the enabled system capabilities and enable() it on this CPU. 1048 * The capabilities were decided based on the available CPUs at the boot time. 1049 * Any new CPU should match the system wide status of the capability. If the 1050 * new CPU doesn't have a capability which the system now has enabled, we 1051 * cannot do anything to fix it up and could cause unexpected failures. So 1052 * we park the CPU. 1053 */ 1054 static void verify_local_cpu_capabilities(void) 1055 { 1056 verify_local_cpu_errata_workarounds(); 1057 verify_local_cpu_features(arm64_features); 1058 verify_local_elf_hwcaps(arm64_elf_hwcaps); 1059 if (system_supports_32bit_el0()) 1060 verify_local_elf_hwcaps(compat_elf_hwcaps); 1061 } 1062 1063 void check_local_cpu_capabilities(void) 1064 { 1065 /* 1066 * All secondary CPUs should conform to the early CPU features 1067 * in use by the kernel based on boot CPU. 1068 */ 1069 check_early_cpu_features(); 1070 1071 /* 1072 * If we haven't finalised the system capabilities, this CPU gets 1073 * a chance to update the errata work arounds. 1074 * Otherwise, this CPU should verify that it has all the system 1075 * advertised capabilities. 1076 */ 1077 if (!sys_caps_initialised) 1078 update_cpu_errata_workarounds(); 1079 else 1080 verify_local_cpu_capabilities(); 1081 } 1082 1083 static void __init setup_feature_capabilities(void) 1084 { 1085 update_cpu_capabilities(arm64_features, "detected feature:"); 1086 enable_cpu_capabilities(arm64_features); 1087 } 1088 1089 /* 1090 * Check if the current CPU has a given feature capability. 1091 * Should be called from non-preemptible context. 1092 */ 1093 bool this_cpu_has_cap(unsigned int cap) 1094 { 1095 const struct arm64_cpu_capabilities *caps; 1096 1097 if (WARN_ON(preemptible())) 1098 return false; 1099 1100 for (caps = arm64_features; caps->desc; caps++) 1101 if (caps->capability == cap && caps->matches) 1102 return caps->matches(caps, SCOPE_LOCAL_CPU); 1103 1104 return false; 1105 } 1106 1107 void __init setup_cpu_features(void) 1108 { 1109 u32 cwg; 1110 int cls; 1111 1112 /* Set the CPU feature capabilies */ 1113 setup_feature_capabilities(); 1114 enable_errata_workarounds(); 1115 setup_elf_hwcaps(arm64_elf_hwcaps); 1116 1117 if (system_supports_32bit_el0()) 1118 setup_elf_hwcaps(compat_elf_hwcaps); 1119 1120 /* Advertise that we have computed the system capabilities */ 1121 set_sys_caps_initialised(); 1122 1123 /* 1124 * Check for sane CTR_EL0.CWG value. 1125 */ 1126 cwg = cache_type_cwg(); 1127 cls = cache_line_size(); 1128 if (!cwg) 1129 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", 1130 cls); 1131 if (L1_CACHE_BYTES < cls) 1132 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", 1133 L1_CACHE_BYTES, cls); 1134 } 1135 1136 static bool __maybe_unused 1137 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) 1138 { 1139 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO)); 1140 } 1141 1142 /* 1143 * We emulate only the following system register space. 1144 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 1145 * See Table C5-6 System instruction encodings for System register accesses, 1146 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 1147 */ 1148 static inline bool __attribute_const__ is_emulated(u32 id) 1149 { 1150 return (sys_reg_Op0(id) == 0x3 && 1151 sys_reg_CRn(id) == 0x0 && 1152 sys_reg_Op1(id) == 0x0 && 1153 (sys_reg_CRm(id) == 0 || 1154 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 1155 } 1156 1157 /* 1158 * With CRm == 0, reg should be one of : 1159 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 1160 */ 1161 static inline int emulate_id_reg(u32 id, u64 *valp) 1162 { 1163 switch (id) { 1164 case SYS_MIDR_EL1: 1165 *valp = read_cpuid_id(); 1166 break; 1167 case SYS_MPIDR_EL1: 1168 *valp = SYS_MPIDR_SAFE_VAL; 1169 break; 1170 case SYS_REVIDR_EL1: 1171 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 1172 *valp = 0; 1173 break; 1174 default: 1175 return -EINVAL; 1176 } 1177 1178 return 0; 1179 } 1180 1181 static int emulate_sys_reg(u32 id, u64 *valp) 1182 { 1183 struct arm64_ftr_reg *regp; 1184 1185 if (!is_emulated(id)) 1186 return -EINVAL; 1187 1188 if (sys_reg_CRm(id) == 0) 1189 return emulate_id_reg(id, valp); 1190 1191 regp = get_arm64_ftr_reg(id); 1192 if (regp) 1193 *valp = arm64_ftr_reg_user_value(regp); 1194 else 1195 /* 1196 * The untracked registers are either IMPLEMENTATION DEFINED 1197 * (e.g, ID_AFR0_EL1) or reserved RAZ. 1198 */ 1199 *valp = 0; 1200 return 0; 1201 } 1202 1203 static int emulate_mrs(struct pt_regs *regs, u32 insn) 1204 { 1205 int rc; 1206 u32 sys_reg, dst; 1207 u64 val; 1208 1209 /* 1210 * sys_reg values are defined as used in mrs/msr instruction. 1211 * shift the imm value to get the encoding. 1212 */ 1213 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 1214 rc = emulate_sys_reg(sys_reg, &val); 1215 if (!rc) { 1216 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 1217 pt_regs_write_reg(regs, dst, val); 1218 regs->pc += 4; 1219 } 1220 1221 return rc; 1222 } 1223 1224 static struct undef_hook mrs_hook = { 1225 .instr_mask = 0xfff00000, 1226 .instr_val = 0xd5300000, 1227 .pstate_mask = COMPAT_PSR_MODE_MASK, 1228 .pstate_val = PSR_MODE_EL0t, 1229 .fn = emulate_mrs, 1230 }; 1231 1232 static int __init enable_mrs_emulation(void) 1233 { 1234 register_undef_hook(&mrs_hook); 1235 return 0; 1236 } 1237 1238 late_initcall(enable_mrs_emulation); 1239