1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/sysfs.h> 71 #include <linux/types.h> 72 #include <linux/minmax.h> 73 #include <linux/mm.h> 74 #include <linux/cpu.h> 75 #include <linux/kasan.h> 76 #include <linux/percpu.h> 77 78 #include <asm/cpu.h> 79 #include <asm/cpufeature.h> 80 #include <asm/cpu_ops.h> 81 #include <asm/fpsimd.h> 82 #include <asm/hwcap.h> 83 #include <asm/insn.h> 84 #include <asm/kvm_host.h> 85 #include <asm/mmu_context.h> 86 #include <asm/mte.h> 87 #include <asm/processor.h> 88 #include <asm/smp.h> 89 #include <asm/sysreg.h> 90 #include <asm/traps.h> 91 #include <asm/vectors.h> 92 #include <asm/virt.h> 93 94 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 95 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 96 97 #ifdef CONFIG_COMPAT 98 #define COMPAT_ELF_HWCAP_DEFAULT \ 99 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 100 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 101 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 102 COMPAT_HWCAP_LPAE) 103 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 104 unsigned int compat_elf_hwcap2 __read_mostly; 105 #endif 106 107 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 108 EXPORT_SYMBOL(cpu_hwcaps); 109 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 110 111 DECLARE_BITMAP(boot_capabilities, ARM64_NCAPS); 112 113 bool arm64_use_ng_mappings = false; 114 EXPORT_SYMBOL(arm64_use_ng_mappings); 115 116 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 117 118 /* 119 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 120 * support it? 121 */ 122 static bool __read_mostly allow_mismatched_32bit_el0; 123 124 /* 125 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 126 * seen at least one CPU capable of 32-bit EL0. 127 */ 128 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 129 130 /* 131 * Mask of CPUs supporting 32-bit EL0. 132 * Only valid if arm64_mismatched_32bit_el0 is enabled. 133 */ 134 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 135 136 void dump_cpu_features(void) 137 { 138 /* file-wide pr_fmt adds "CPU features: " prefix */ 139 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 140 } 141 142 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 143 { \ 144 .sign = SIGNED, \ 145 .visible = VISIBLE, \ 146 .strict = STRICT, \ 147 .type = TYPE, \ 148 .shift = SHIFT, \ 149 .width = WIDTH, \ 150 .safe_val = SAFE_VAL, \ 151 } 152 153 /* Define a feature with unsigned values */ 154 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 155 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 156 157 /* Define a feature with a signed value */ 158 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 159 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 160 161 #define ARM64_FTR_END \ 162 { \ 163 .width = 0, \ 164 } 165 166 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 167 168 static bool __system_matches_cap(unsigned int n); 169 170 /* 171 * NOTE: Any changes to the visibility of features should be kept in 172 * sync with the documentation of the CPU feature register ABI. 173 */ 174 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 175 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 176 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 182 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 184 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 189 ARM64_FTR_END, 190 }; 191 192 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 199 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 200 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 202 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 207 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 208 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 209 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 211 ARM64_FTR_END, 212 }; 213 214 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 215 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 219 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 221 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 224 ARM64_FTR_END, 225 }; 226 227 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 235 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 238 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 239 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 244 ARM64_FTR_END, 245 }; 246 247 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 249 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 255 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 256 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 257 ARM64_FTR_END, 258 }; 259 260 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 261 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 262 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 263 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 264 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 266 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 268 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 270 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 272 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 276 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 278 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 279 ARM64_FTR_END, 280 }; 281 282 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 284 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 286 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 288 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 289 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 290 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 292 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 293 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 294 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 295 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 296 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 297 ARM64_FTR_END, 298 }; 299 300 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 301 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 304 /* 305 * Page size not being supported at Stage-2 is not fatal. You 306 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 307 * your favourite nesting hypervisor. 308 * 309 * There is a small corner case where the hypervisor explicitly 310 * advertises a given granule size at Stage-2 (value 2) on some 311 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 312 * vCPUs. Although this is not forbidden by the architecture, it 313 * indicates that the hypervisor is being silly (or buggy). 314 * 315 * We make no effort to cope with this and pretend that if these 316 * fields are inconsistent across vCPUs, then it isn't worth 317 * trying to bring KVM up. 318 */ 319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 322 /* 323 * We already refuse to boot CPUs that don't support our configured 324 * page size, so we can only detect mismatches for a page size other 325 * than the one we're currently using. Unfortunately, SoCs like this 326 * exist in the wild so, even though we don't like it, we'll have to go 327 * along with it and treat them as non-strict. 328 */ 329 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 330 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 332 333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 334 /* Linux shouldn't care about secure memory */ 335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 338 /* 339 * Differing PARange is fine as long as all peripherals and memory are mapped 340 * within the minimum PARange of all CPUs 341 */ 342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 343 ARM64_FTR_END, 344 }; 345 346 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 357 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 359 ARM64_FTR_END, 360 }; 361 362 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 369 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 378 ARM64_FTR_END, 379 }; 380 381 static const struct arm64_ftr_bits ftr_ctr[] = { 382 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 383 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 384 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 385 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 386 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 387 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 388 /* 389 * Linux can handle differing I-cache policies. Userspace JITs will 390 * make use of *minLine. 391 * If we have differing I-cache policies, report it as the weakest - VIPT. 392 */ 393 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 394 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 395 ARM64_FTR_END, 396 }; 397 398 static struct arm64_ftr_override __ro_after_init no_override = { }; 399 400 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 401 .name = "SYS_CTR_EL0", 402 .ftr_bits = ftr_ctr, 403 .override = &no_override, 404 }; 405 406 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 407 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 410 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 411 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 412 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 415 ARM64_FTR_END, 416 }; 417 418 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 419 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 423 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 424 /* 425 * We can instantiate multiple PMU instances with different levels 426 * of support. 427 */ 428 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 430 ARM64_FTR_END, 431 }; 432 433 static const struct arm64_ftr_bits ftr_mvfr0[] = { 434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 442 ARM64_FTR_END, 443 }; 444 445 static const struct arm64_ftr_bits ftr_mvfr1[] = { 446 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 450 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 451 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 454 ARM64_FTR_END, 455 }; 456 457 static const struct arm64_ftr_bits ftr_mvfr2[] = { 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 460 ARM64_FTR_END, 461 }; 462 463 static const struct arm64_ftr_bits ftr_dczid[] = { 464 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 465 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 466 ARM64_FTR_END, 467 }; 468 469 static const struct arm64_ftr_bits ftr_gmid[] = { 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 471 ARM64_FTR_END, 472 }; 473 474 static const struct arm64_ftr_bits ftr_id_isar0[] = { 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 482 ARM64_FTR_END, 483 }; 484 485 static const struct arm64_ftr_bits ftr_id_isar5[] = { 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 492 ARM64_FTR_END, 493 }; 494 495 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 503 504 /* 505 * SpecSEI = 1 indicates that the PE might generate an SError on an 506 * external abort on speculative read. It is safe to assume that an 507 * SError might be generated than it will not be. Hence it has been 508 * classified as FTR_HIGHER_SAFE. 509 */ 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 511 ARM64_FTR_END, 512 }; 513 514 static const struct arm64_ftr_bits ftr_id_isar4[] = { 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 522 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 523 ARM64_FTR_END, 524 }; 525 526 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 528 ARM64_FTR_END, 529 }; 530 531 static const struct arm64_ftr_bits ftr_id_isar6[] = { 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 539 ARM64_FTR_END, 540 }; 541 542 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 549 ARM64_FTR_END, 550 }; 551 552 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 561 ARM64_FTR_END, 562 }; 563 564 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 565 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 566 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 567 ARM64_FTR_END, 568 }; 569 570 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 571 /* [31:28] TraceFilt */ 572 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 578 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 579 ARM64_FTR_END, 580 }; 581 582 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 583 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 584 ARM64_FTR_END, 585 }; 586 587 static const struct arm64_ftr_bits ftr_zcr[] = { 588 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 589 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0), /* LEN */ 590 ARM64_FTR_END, 591 }; 592 593 static const struct arm64_ftr_bits ftr_smcr[] = { 594 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 595 SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0), /* LEN */ 596 ARM64_FTR_END, 597 }; 598 599 /* 600 * Common ftr bits for a 32bit register with all hidden, strict 601 * attributes, with 4bit feature fields and a default safe value of 602 * 0. Covers the following 32bit registers: 603 * id_isar[1-3], id_mmfr[1-3] 604 */ 605 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 608 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 609 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 610 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 611 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 612 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 613 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 614 ARM64_FTR_END, 615 }; 616 617 /* Table for a single 32bit feature value */ 618 static const struct arm64_ftr_bits ftr_single32[] = { 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 620 ARM64_FTR_END, 621 }; 622 623 static const struct arm64_ftr_bits ftr_raz[] = { 624 ARM64_FTR_END, 625 }; 626 627 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 628 .sys_id = id, \ 629 .reg = &(struct arm64_ftr_reg){ \ 630 .name = id_str, \ 631 .override = (ovr), \ 632 .ftr_bits = &((table)[0]), \ 633 }} 634 635 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 636 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 637 638 #define ARM64_FTR_REG(id, table) \ 639 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 640 641 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 642 struct arm64_ftr_override __ro_after_init id_aa64pfr0_override; 643 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 644 struct arm64_ftr_override __ro_after_init id_aa64zfr0_override; 645 struct arm64_ftr_override __ro_after_init id_aa64smfr0_override; 646 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 647 struct arm64_ftr_override __ro_after_init id_aa64isar2_override; 648 649 static const struct __ftr_reg_entry { 650 u32 sys_id; 651 struct arm64_ftr_reg *reg; 652 } arm64_ftr_regs[] = { 653 654 /* Op1 = 0, CRn = 0, CRm = 1 */ 655 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 656 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 657 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 658 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 659 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 660 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 661 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 662 663 /* Op1 = 0, CRn = 0, CRm = 2 */ 664 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 665 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 666 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 667 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 668 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 669 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 670 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 671 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 672 673 /* Op1 = 0, CRn = 0, CRm = 3 */ 674 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 675 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 676 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 677 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 678 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 679 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 680 681 /* Op1 = 0, CRn = 0, CRm = 4 */ 682 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 683 &id_aa64pfr0_override), 684 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 685 &id_aa64pfr1_override), 686 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 687 &id_aa64zfr0_override), 688 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 689 &id_aa64smfr0_override), 690 691 /* Op1 = 0, CRn = 0, CRm = 5 */ 692 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 693 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 694 695 /* Op1 = 0, CRn = 0, CRm = 6 */ 696 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 697 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 698 &id_aa64isar1_override), 699 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 700 &id_aa64isar2_override), 701 702 /* Op1 = 0, CRn = 0, CRm = 7 */ 703 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 704 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 705 &id_aa64mmfr1_override), 706 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 707 708 /* Op1 = 0, CRn = 1, CRm = 2 */ 709 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 710 ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr), 711 712 /* Op1 = 1, CRn = 0, CRm = 0 */ 713 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 714 715 /* Op1 = 3, CRn = 0, CRm = 0 */ 716 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 717 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 718 719 /* Op1 = 3, CRn = 14, CRm = 0 */ 720 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 721 }; 722 723 static int search_cmp_ftr_reg(const void *id, const void *regp) 724 { 725 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 726 } 727 728 /* 729 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 730 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 731 * ascending order of sys_id, we use binary search to find a matching 732 * entry. 733 * 734 * returns - Upon success, matching ftr_reg entry for id. 735 * - NULL on failure. It is upto the caller to decide 736 * the impact of a failure. 737 */ 738 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 739 { 740 const struct __ftr_reg_entry *ret; 741 742 ret = bsearch((const void *)(unsigned long)sys_id, 743 arm64_ftr_regs, 744 ARRAY_SIZE(arm64_ftr_regs), 745 sizeof(arm64_ftr_regs[0]), 746 search_cmp_ftr_reg); 747 if (ret) 748 return ret->reg; 749 return NULL; 750 } 751 752 /* 753 * get_arm64_ftr_reg - Looks up a feature register entry using 754 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 755 * 756 * returns - Upon success, matching ftr_reg entry for id. 757 * - NULL on failure but with an WARN_ON(). 758 */ 759 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 760 { 761 struct arm64_ftr_reg *reg; 762 763 reg = get_arm64_ftr_reg_nowarn(sys_id); 764 765 /* 766 * Requesting a non-existent register search is an error. Warn 767 * and let the caller handle it. 768 */ 769 WARN_ON(!reg); 770 return reg; 771 } 772 773 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 774 s64 ftr_val) 775 { 776 u64 mask = arm64_ftr_mask(ftrp); 777 778 reg &= ~mask; 779 reg |= (ftr_val << ftrp->shift) & mask; 780 return reg; 781 } 782 783 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 784 s64 cur) 785 { 786 s64 ret = 0; 787 788 switch (ftrp->type) { 789 case FTR_EXACT: 790 ret = ftrp->safe_val; 791 break; 792 case FTR_LOWER_SAFE: 793 ret = min(new, cur); 794 break; 795 case FTR_HIGHER_OR_ZERO_SAFE: 796 if (!cur || !new) 797 break; 798 fallthrough; 799 case FTR_HIGHER_SAFE: 800 ret = max(new, cur); 801 break; 802 default: 803 BUG(); 804 } 805 806 return ret; 807 } 808 809 static void __init sort_ftr_regs(void) 810 { 811 unsigned int i; 812 813 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 814 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 815 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 816 unsigned int j = 0; 817 818 /* 819 * Features here must be sorted in descending order with respect 820 * to their shift values and should not overlap with each other. 821 */ 822 for (; ftr_bits->width != 0; ftr_bits++, j++) { 823 unsigned int width = ftr_reg->ftr_bits[j].width; 824 unsigned int shift = ftr_reg->ftr_bits[j].shift; 825 unsigned int prev_shift; 826 827 WARN((shift + width) > 64, 828 "%s has invalid feature at shift %d\n", 829 ftr_reg->name, shift); 830 831 /* 832 * Skip the first feature. There is nothing to 833 * compare against for now. 834 */ 835 if (j == 0) 836 continue; 837 838 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 839 WARN((shift + width) > prev_shift, 840 "%s has feature overlap at shift %d\n", 841 ftr_reg->name, shift); 842 } 843 844 /* 845 * Skip the first register. There is nothing to 846 * compare against for now. 847 */ 848 if (i == 0) 849 continue; 850 /* 851 * Registers here must be sorted in ascending order with respect 852 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 853 * to work correctly. 854 */ 855 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 856 } 857 } 858 859 /* 860 * Initialise the CPU feature register from Boot CPU values. 861 * Also initiliases the strict_mask for the register. 862 * Any bits that are not covered by an arm64_ftr_bits entry are considered 863 * RES0 for the system-wide value, and must strictly match. 864 */ 865 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 866 { 867 u64 val = 0; 868 u64 strict_mask = ~0x0ULL; 869 u64 user_mask = 0; 870 u64 valid_mask = 0; 871 872 const struct arm64_ftr_bits *ftrp; 873 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 874 875 if (!reg) 876 return; 877 878 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 879 u64 ftr_mask = arm64_ftr_mask(ftrp); 880 s64 ftr_new = arm64_ftr_value(ftrp, new); 881 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 882 883 if ((ftr_mask & reg->override->mask) == ftr_mask) { 884 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 885 char *str = NULL; 886 887 if (ftr_ovr != tmp) { 888 /* Unsafe, remove the override */ 889 reg->override->mask &= ~ftr_mask; 890 reg->override->val &= ~ftr_mask; 891 tmp = ftr_ovr; 892 str = "ignoring override"; 893 } else if (ftr_new != tmp) { 894 /* Override was valid */ 895 ftr_new = tmp; 896 str = "forced"; 897 } else if (ftr_ovr == tmp) { 898 /* Override was the safe value */ 899 str = "already set"; 900 } 901 902 if (str) 903 pr_warn("%s[%d:%d]: %s to %llx\n", 904 reg->name, 905 ftrp->shift + ftrp->width - 1, 906 ftrp->shift, str, tmp); 907 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 908 reg->override->val &= ~ftr_mask; 909 pr_warn("%s[%d:%d]: impossible override, ignored\n", 910 reg->name, 911 ftrp->shift + ftrp->width - 1, 912 ftrp->shift); 913 } 914 915 val = arm64_ftr_set_value(ftrp, val, ftr_new); 916 917 valid_mask |= ftr_mask; 918 if (!ftrp->strict) 919 strict_mask &= ~ftr_mask; 920 if (ftrp->visible) 921 user_mask |= ftr_mask; 922 else 923 reg->user_val = arm64_ftr_set_value(ftrp, 924 reg->user_val, 925 ftrp->safe_val); 926 } 927 928 val &= valid_mask; 929 930 reg->sys_val = val; 931 reg->strict_mask = strict_mask; 932 reg->user_mask = user_mask; 933 } 934 935 extern const struct arm64_cpu_capabilities arm64_errata[]; 936 static const struct arm64_cpu_capabilities arm64_features[]; 937 938 static void __init 939 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 940 { 941 for (; caps->matches; caps++) { 942 if (WARN(caps->capability >= ARM64_NCAPS, 943 "Invalid capability %d\n", caps->capability)) 944 continue; 945 if (WARN(cpu_hwcaps_ptrs[caps->capability], 946 "Duplicate entry for capability %d\n", 947 caps->capability)) 948 continue; 949 cpu_hwcaps_ptrs[caps->capability] = caps; 950 } 951 } 952 953 static void __init init_cpu_hwcaps_indirect_list(void) 954 { 955 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 956 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 957 } 958 959 static void __init setup_boot_cpu_capabilities(void); 960 961 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 962 { 963 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 964 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 965 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 966 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 967 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 968 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 969 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 970 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 971 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 972 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 973 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 974 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 975 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 976 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 977 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 978 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 979 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 980 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 981 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 982 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 983 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 984 } 985 986 void __init init_cpu_features(struct cpuinfo_arm64 *info) 987 { 988 /* Before we start using the tables, make sure it is sorted */ 989 sort_ftr_regs(); 990 991 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 992 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 993 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 994 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 995 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 996 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 997 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 998 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 999 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1000 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1001 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1002 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1003 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1004 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1005 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1006 1007 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1008 init_32bit_cpu_features(&info->aarch32); 1009 1010 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1011 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1012 info->reg_zcr = read_zcr_features(); 1013 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 1014 vec_init_vq_map(ARM64_VEC_SVE); 1015 } 1016 1017 if (IS_ENABLED(CONFIG_ARM64_SME) && 1018 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1019 info->reg_smcr = read_smcr_features(); 1020 /* 1021 * We mask out SMPS since even if the hardware 1022 * supports priorities the kernel does not at present 1023 * and we block access to them. 1024 */ 1025 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1026 init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr); 1027 vec_init_vq_map(ARM64_VEC_SME); 1028 } 1029 1030 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1031 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1032 1033 /* 1034 * Initialize the indirect array of CPU hwcaps capabilities pointers 1035 * before we handle the boot CPU below. 1036 */ 1037 init_cpu_hwcaps_indirect_list(); 1038 1039 /* 1040 * Detect and enable early CPU capabilities based on the boot CPU, 1041 * after we have initialised the CPU feature infrastructure. 1042 */ 1043 setup_boot_cpu_capabilities(); 1044 } 1045 1046 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1047 { 1048 const struct arm64_ftr_bits *ftrp; 1049 1050 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1051 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1052 s64 ftr_new = arm64_ftr_value(ftrp, new); 1053 1054 if (ftr_cur == ftr_new) 1055 continue; 1056 /* Find a safe value */ 1057 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1058 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1059 } 1060 1061 } 1062 1063 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1064 { 1065 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1066 1067 if (!regp) 1068 return 0; 1069 1070 update_cpu_ftr_reg(regp, val); 1071 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1072 return 0; 1073 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1074 regp->name, boot, cpu, val); 1075 return 1; 1076 } 1077 1078 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1079 { 1080 const struct arm64_ftr_bits *ftrp; 1081 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1082 1083 if (!regp) 1084 return; 1085 1086 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1087 if (ftrp->shift == field) { 1088 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1089 break; 1090 } 1091 } 1092 1093 /* Bogus field? */ 1094 WARN_ON(!ftrp->width); 1095 } 1096 1097 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1098 struct cpuinfo_arm64 *boot) 1099 { 1100 static bool boot_cpu_32bit_regs_overridden = false; 1101 1102 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1103 return; 1104 1105 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1106 return; 1107 1108 boot->aarch32 = info->aarch32; 1109 init_32bit_cpu_features(&boot->aarch32); 1110 boot_cpu_32bit_regs_overridden = true; 1111 } 1112 1113 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1114 struct cpuinfo_32bit *boot) 1115 { 1116 int taint = 0; 1117 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1118 1119 /* 1120 * If we don't have AArch32 at EL1, then relax the strictness of 1121 * EL1-dependent register fields to avoid spurious sanity check fails. 1122 */ 1123 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1124 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1125 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1126 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1127 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1128 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1129 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1130 } 1131 1132 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1133 info->reg_id_dfr0, boot->reg_id_dfr0); 1134 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1135 info->reg_id_dfr1, boot->reg_id_dfr1); 1136 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1137 info->reg_id_isar0, boot->reg_id_isar0); 1138 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1139 info->reg_id_isar1, boot->reg_id_isar1); 1140 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1141 info->reg_id_isar2, boot->reg_id_isar2); 1142 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1143 info->reg_id_isar3, boot->reg_id_isar3); 1144 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1145 info->reg_id_isar4, boot->reg_id_isar4); 1146 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1147 info->reg_id_isar5, boot->reg_id_isar5); 1148 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1149 info->reg_id_isar6, boot->reg_id_isar6); 1150 1151 /* 1152 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1153 * ACTLR formats could differ across CPUs and therefore would have to 1154 * be trapped for virtualization anyway. 1155 */ 1156 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1157 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1158 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1159 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1160 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1161 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1162 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1163 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1164 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1165 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1166 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1167 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1168 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1169 info->reg_id_pfr0, boot->reg_id_pfr0); 1170 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1171 info->reg_id_pfr1, boot->reg_id_pfr1); 1172 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1173 info->reg_id_pfr2, boot->reg_id_pfr2); 1174 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1175 info->reg_mvfr0, boot->reg_mvfr0); 1176 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1177 info->reg_mvfr1, boot->reg_mvfr1); 1178 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1179 info->reg_mvfr2, boot->reg_mvfr2); 1180 1181 return taint; 1182 } 1183 1184 /* 1185 * Update system wide CPU feature registers with the values from a 1186 * non-boot CPU. Also performs SANITY checks to make sure that there 1187 * aren't any insane variations from that of the boot CPU. 1188 */ 1189 void update_cpu_features(int cpu, 1190 struct cpuinfo_arm64 *info, 1191 struct cpuinfo_arm64 *boot) 1192 { 1193 int taint = 0; 1194 1195 /* 1196 * The kernel can handle differing I-cache policies, but otherwise 1197 * caches should look identical. Userspace JITs will make use of 1198 * *minLine. 1199 */ 1200 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1201 info->reg_ctr, boot->reg_ctr); 1202 1203 /* 1204 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1205 * could result in too much or too little memory being zeroed if a 1206 * process is preempted and migrated between CPUs. 1207 */ 1208 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1209 info->reg_dczid, boot->reg_dczid); 1210 1211 /* If different, timekeeping will be broken (especially with KVM) */ 1212 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1213 info->reg_cntfrq, boot->reg_cntfrq); 1214 1215 /* 1216 * The kernel uses self-hosted debug features and expects CPUs to 1217 * support identical debug features. We presently need CTX_CMPs, WRPs, 1218 * and BRPs to be identical. 1219 * ID_AA64DFR1 is currently RES0. 1220 */ 1221 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1222 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1223 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1224 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1225 /* 1226 * Even in big.LITTLE, processors should be identical instruction-set 1227 * wise. 1228 */ 1229 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1230 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1231 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1232 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1233 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1234 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1235 1236 /* 1237 * Differing PARange support is fine as long as all peripherals and 1238 * memory are mapped within the minimum PARange of all CPUs. 1239 * Linux should not care about secure memory. 1240 */ 1241 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1242 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1243 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1244 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1245 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1246 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1247 1248 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1249 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1250 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1251 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1252 1253 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1254 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1255 1256 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1257 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1258 1259 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1260 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1261 info->reg_zcr = read_zcr_features(); 1262 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1263 info->reg_zcr, boot->reg_zcr); 1264 1265 /* Probe vector lengths */ 1266 if (!system_capabilities_finalized()) 1267 vec_update_vq_map(ARM64_VEC_SVE); 1268 } 1269 1270 if (IS_ENABLED(CONFIG_ARM64_SME) && 1271 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1272 info->reg_smcr = read_smcr_features(); 1273 /* 1274 * We mask out SMPS since even if the hardware 1275 * supports priorities the kernel does not at present 1276 * and we block access to them. 1277 */ 1278 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1279 taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu, 1280 info->reg_smcr, boot->reg_smcr); 1281 1282 /* Probe vector lengths */ 1283 if (!system_capabilities_finalized()) 1284 vec_update_vq_map(ARM64_VEC_SME); 1285 } 1286 1287 /* 1288 * The kernel uses the LDGM/STGM instructions and the number of tags 1289 * they read/write depends on the GMID_EL1.BS field. Check that the 1290 * value is the same on all CPUs. 1291 */ 1292 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1293 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1294 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1295 info->reg_gmid, boot->reg_gmid); 1296 } 1297 1298 /* 1299 * If we don't have AArch32 at all then skip the checks entirely 1300 * as the register values may be UNKNOWN and we're not going to be 1301 * using them for anything. 1302 * 1303 * This relies on a sanitised view of the AArch64 ID registers 1304 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1305 */ 1306 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1307 lazy_init_32bit_cpu_features(info, boot); 1308 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1309 &boot->aarch32); 1310 } 1311 1312 /* 1313 * Mismatched CPU features are a recipe for disaster. Don't even 1314 * pretend to support them. 1315 */ 1316 if (taint) { 1317 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1318 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1319 } 1320 } 1321 1322 u64 read_sanitised_ftr_reg(u32 id) 1323 { 1324 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1325 1326 if (!regp) 1327 return 0; 1328 return regp->sys_val; 1329 } 1330 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1331 1332 #define read_sysreg_case(r) \ 1333 case r: val = read_sysreg_s(r); break; 1334 1335 /* 1336 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1337 * Read the system register on the current CPU 1338 */ 1339 u64 __read_sysreg_by_encoding(u32 sys_id) 1340 { 1341 struct arm64_ftr_reg *regp; 1342 u64 val; 1343 1344 switch (sys_id) { 1345 read_sysreg_case(SYS_ID_PFR0_EL1); 1346 read_sysreg_case(SYS_ID_PFR1_EL1); 1347 read_sysreg_case(SYS_ID_PFR2_EL1); 1348 read_sysreg_case(SYS_ID_DFR0_EL1); 1349 read_sysreg_case(SYS_ID_DFR1_EL1); 1350 read_sysreg_case(SYS_ID_MMFR0_EL1); 1351 read_sysreg_case(SYS_ID_MMFR1_EL1); 1352 read_sysreg_case(SYS_ID_MMFR2_EL1); 1353 read_sysreg_case(SYS_ID_MMFR3_EL1); 1354 read_sysreg_case(SYS_ID_MMFR4_EL1); 1355 read_sysreg_case(SYS_ID_MMFR5_EL1); 1356 read_sysreg_case(SYS_ID_ISAR0_EL1); 1357 read_sysreg_case(SYS_ID_ISAR1_EL1); 1358 read_sysreg_case(SYS_ID_ISAR2_EL1); 1359 read_sysreg_case(SYS_ID_ISAR3_EL1); 1360 read_sysreg_case(SYS_ID_ISAR4_EL1); 1361 read_sysreg_case(SYS_ID_ISAR5_EL1); 1362 read_sysreg_case(SYS_ID_ISAR6_EL1); 1363 read_sysreg_case(SYS_MVFR0_EL1); 1364 read_sysreg_case(SYS_MVFR1_EL1); 1365 read_sysreg_case(SYS_MVFR2_EL1); 1366 1367 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1368 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1369 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1370 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1371 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1372 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1373 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1374 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1375 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1376 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1377 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1378 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1379 1380 read_sysreg_case(SYS_CNTFRQ_EL0); 1381 read_sysreg_case(SYS_CTR_EL0); 1382 read_sysreg_case(SYS_DCZID_EL0); 1383 1384 default: 1385 BUG(); 1386 return 0; 1387 } 1388 1389 regp = get_arm64_ftr_reg(sys_id); 1390 if (regp) { 1391 val &= ~regp->override->mask; 1392 val |= (regp->override->val & regp->override->mask); 1393 } 1394 1395 return val; 1396 } 1397 1398 #include <linux/irqchip/arm-gic-v3.h> 1399 1400 static bool 1401 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1402 { 1403 return true; 1404 } 1405 1406 static bool 1407 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1408 { 1409 int val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1410 entry->field_width, 1411 entry->sign); 1412 1413 return val >= entry->min_field_value; 1414 } 1415 1416 static u64 1417 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1418 { 1419 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1420 if (scope == SCOPE_SYSTEM) 1421 return read_sanitised_ftr_reg(entry->sys_reg); 1422 else 1423 return __read_sysreg_by_encoding(entry->sys_reg); 1424 } 1425 1426 static bool 1427 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1428 { 1429 int mask; 1430 struct arm64_ftr_reg *regp; 1431 u64 val = read_scoped_sysreg(entry, scope); 1432 1433 regp = get_arm64_ftr_reg(entry->sys_reg); 1434 if (!regp) 1435 return false; 1436 1437 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1438 entry->field_pos, 1439 entry->field_width); 1440 if (!mask) 1441 return false; 1442 1443 return feature_matches(val, entry); 1444 } 1445 1446 static bool 1447 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1448 { 1449 u64 val = read_scoped_sysreg(entry, scope); 1450 return feature_matches(val, entry); 1451 } 1452 1453 const struct cpumask *system_32bit_el0_cpumask(void) 1454 { 1455 if (!system_supports_32bit_el0()) 1456 return cpu_none_mask; 1457 1458 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1459 return cpu_32bit_el0_mask; 1460 1461 return cpu_possible_mask; 1462 } 1463 1464 static int __init parse_32bit_el0_param(char *str) 1465 { 1466 allow_mismatched_32bit_el0 = true; 1467 return 0; 1468 } 1469 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1470 1471 static ssize_t aarch32_el0_show(struct device *dev, 1472 struct device_attribute *attr, char *buf) 1473 { 1474 const struct cpumask *mask = system_32bit_el0_cpumask(); 1475 1476 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1477 } 1478 static const DEVICE_ATTR_RO(aarch32_el0); 1479 1480 static int __init aarch32_el0_sysfs_init(void) 1481 { 1482 if (!allow_mismatched_32bit_el0) 1483 return 0; 1484 1485 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0); 1486 } 1487 device_initcall(aarch32_el0_sysfs_init); 1488 1489 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1490 { 1491 if (!has_cpuid_feature(entry, scope)) 1492 return allow_mismatched_32bit_el0; 1493 1494 if (scope == SCOPE_SYSTEM) 1495 pr_info("detected: 32-bit EL0 Support\n"); 1496 1497 return true; 1498 } 1499 1500 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1501 { 1502 bool has_sre; 1503 1504 if (!has_cpuid_feature(entry, scope)) 1505 return false; 1506 1507 has_sre = gic_enable_sre(); 1508 if (!has_sre) 1509 pr_warn_once("%s present but disabled by higher exception level\n", 1510 entry->desc); 1511 1512 return has_sre; 1513 } 1514 1515 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1516 { 1517 u32 midr = read_cpuid_id(); 1518 1519 /* Cavium ThunderX pass 1.x and 2.x */ 1520 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1521 MIDR_CPU_VAR_REV(0, 0), 1522 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1523 } 1524 1525 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1526 { 1527 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1528 1529 return cpuid_feature_extract_signed_field(pfr0, 1530 ID_AA64PFR0_EL1_FP_SHIFT) < 0; 1531 } 1532 1533 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1534 int scope) 1535 { 1536 u64 ctr; 1537 1538 if (scope == SCOPE_SYSTEM) 1539 ctr = arm64_ftr_reg_ctrel0.sys_val; 1540 else 1541 ctr = read_cpuid_effective_cachetype(); 1542 1543 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1544 } 1545 1546 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1547 { 1548 /* 1549 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1550 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1551 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1552 * value. 1553 */ 1554 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1555 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1556 } 1557 1558 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1559 int scope) 1560 { 1561 u64 ctr; 1562 1563 if (scope == SCOPE_SYSTEM) 1564 ctr = arm64_ftr_reg_ctrel0.sys_val; 1565 else 1566 ctr = read_cpuid_cachetype(); 1567 1568 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1569 } 1570 1571 static bool __maybe_unused 1572 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1573 { 1574 /* 1575 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1576 * may share TLB entries with a CPU stuck in the crashed 1577 * kernel. 1578 */ 1579 if (is_kdump_kernel()) 1580 return false; 1581 1582 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1583 return false; 1584 1585 return has_cpuid_feature(entry, scope); 1586 } 1587 1588 /* 1589 * This check is triggered during the early boot before the cpufeature 1590 * is initialised. Checking the status on the local CPU allows the boot 1591 * CPU to detect the need for non-global mappings and thus avoiding a 1592 * pagetable re-write after all the CPUs are booted. This check will be 1593 * anyway run on individual CPUs, allowing us to get the consistent 1594 * state once the SMP CPUs are up and thus make the switch to non-global 1595 * mappings if required. 1596 */ 1597 bool kaslr_requires_kpti(void) 1598 { 1599 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1600 return false; 1601 1602 /* 1603 * E0PD does a similar job to KPTI so can be used instead 1604 * where available. 1605 */ 1606 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1607 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1608 if (cpuid_feature_extract_unsigned_field(mmfr2, 1609 ID_AA64MMFR2_EL1_E0PD_SHIFT)) 1610 return false; 1611 } 1612 1613 /* 1614 * Systems affected by Cavium erratum 24756 are incompatible 1615 * with KPTI. 1616 */ 1617 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1618 extern const struct midr_range cavium_erratum_27456_cpus[]; 1619 1620 if (is_midr_in_range_list(read_cpuid_id(), 1621 cavium_erratum_27456_cpus)) 1622 return false; 1623 } 1624 1625 return kaslr_offset() > 0; 1626 } 1627 1628 static bool __meltdown_safe = true; 1629 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1630 1631 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1632 int scope) 1633 { 1634 /* List of CPUs that are not vulnerable and don't need KPTI */ 1635 static const struct midr_range kpti_safe_list[] = { 1636 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1637 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1638 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1639 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1640 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1641 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1642 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1643 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1644 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1645 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1646 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1647 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1648 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1649 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1650 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1651 { /* sentinel */ } 1652 }; 1653 char const *str = "kpti command line option"; 1654 bool meltdown_safe; 1655 1656 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1657 1658 /* Defer to CPU feature registers */ 1659 if (has_cpuid_feature(entry, scope)) 1660 meltdown_safe = true; 1661 1662 if (!meltdown_safe) 1663 __meltdown_safe = false; 1664 1665 /* 1666 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1667 * ThunderX leads to apparent I-cache corruption of kernel text, which 1668 * ends as well as you might imagine. Don't even try. We cannot rely 1669 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1670 * because cpucap detection order may change. However, since we know 1671 * affected CPUs are always in a homogeneous configuration, it is 1672 * safe to rely on this_cpu_has_cap() here. 1673 */ 1674 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1675 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1676 __kpti_forced = -1; 1677 } 1678 1679 /* Useful for KASLR robustness */ 1680 if (kaslr_requires_kpti()) { 1681 if (!__kpti_forced) { 1682 str = "KASLR"; 1683 __kpti_forced = 1; 1684 } 1685 } 1686 1687 if (cpu_mitigations_off() && !__kpti_forced) { 1688 str = "mitigations=off"; 1689 __kpti_forced = -1; 1690 } 1691 1692 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1693 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1694 return false; 1695 } 1696 1697 /* Forced? */ 1698 if (__kpti_forced) { 1699 pr_info_once("kernel page table isolation forced %s by %s\n", 1700 __kpti_forced > 0 ? "ON" : "OFF", str); 1701 return __kpti_forced > 0; 1702 } 1703 1704 return !meltdown_safe; 1705 } 1706 1707 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1708 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1709 1710 extern 1711 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1712 phys_addr_t size, pgprot_t prot, 1713 phys_addr_t (*pgtable_alloc)(int), int flags); 1714 1715 static phys_addr_t kpti_ng_temp_alloc; 1716 1717 static phys_addr_t kpti_ng_pgd_alloc(int shift) 1718 { 1719 kpti_ng_temp_alloc -= PAGE_SIZE; 1720 return kpti_ng_temp_alloc; 1721 } 1722 1723 static void 1724 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1725 { 1726 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1727 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1728 kpti_remap_fn *remap_fn; 1729 1730 int cpu = smp_processor_id(); 1731 int levels = CONFIG_PGTABLE_LEVELS; 1732 int order = order_base_2(levels); 1733 u64 kpti_ng_temp_pgd_pa = 0; 1734 pgd_t *kpti_ng_temp_pgd; 1735 u64 alloc = 0; 1736 1737 if (__this_cpu_read(this_cpu_vector) == vectors) { 1738 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1739 1740 __this_cpu_write(this_cpu_vector, v); 1741 } 1742 1743 /* 1744 * We don't need to rewrite the page-tables if either we've done 1745 * it already or we have KASLR enabled and therefore have not 1746 * created any global mappings at all. 1747 */ 1748 if (arm64_use_ng_mappings) 1749 return; 1750 1751 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1752 1753 if (!cpu) { 1754 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1755 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1756 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1757 1758 // 1759 // Create a minimal page table hierarchy that permits us to map 1760 // the swapper page tables temporarily as we traverse them. 1761 // 1762 // The physical pages are laid out as follows: 1763 // 1764 // +--------+-/-------+-/------ +-\\--------+ 1765 // : PTE[] : | PMD[] : | PUD[] : || PGD[] : 1766 // +--------+-\-------+-\------ +-//--------+ 1767 // ^ 1768 // The first page is mapped into this hierarchy at a PMD_SHIFT 1769 // aligned virtual address, so that we can manipulate the PTE 1770 // level entries while the mapping is active. The first entry 1771 // covers the PTE[] page itself, the remaining entries are free 1772 // to be used as a ad-hoc fixmap. 1773 // 1774 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1775 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1776 kpti_ng_pgd_alloc, 0); 1777 } 1778 1779 cpu_install_idmap(); 1780 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1781 cpu_uninstall_idmap(); 1782 1783 if (!cpu) { 1784 free_pages(alloc, order); 1785 arm64_use_ng_mappings = true; 1786 } 1787 } 1788 #else 1789 static void 1790 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1791 { 1792 } 1793 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1794 1795 static int __init parse_kpti(char *str) 1796 { 1797 bool enabled; 1798 int ret = strtobool(str, &enabled); 1799 1800 if (ret) 1801 return ret; 1802 1803 __kpti_forced = enabled ? 1 : -1; 1804 return 0; 1805 } 1806 early_param("kpti", parse_kpti); 1807 1808 #ifdef CONFIG_ARM64_HW_AFDBM 1809 static inline void __cpu_enable_hw_dbm(void) 1810 { 1811 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1812 1813 write_sysreg(tcr, tcr_el1); 1814 isb(); 1815 local_flush_tlb_all(); 1816 } 1817 1818 static bool cpu_has_broken_dbm(void) 1819 { 1820 /* List of CPUs which have broken DBM support. */ 1821 static const struct midr_range cpus[] = { 1822 #ifdef CONFIG_ARM64_ERRATUM_1024718 1823 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1824 /* Kryo4xx Silver (rdpe => r1p0) */ 1825 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1826 #endif 1827 #ifdef CONFIG_ARM64_ERRATUM_2051678 1828 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1829 #endif 1830 {}, 1831 }; 1832 1833 return is_midr_in_range_list(read_cpuid_id(), cpus); 1834 } 1835 1836 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1837 { 1838 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1839 !cpu_has_broken_dbm(); 1840 } 1841 1842 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1843 { 1844 if (cpu_can_use_dbm(cap)) 1845 __cpu_enable_hw_dbm(); 1846 } 1847 1848 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1849 int __unused) 1850 { 1851 static bool detected = false; 1852 /* 1853 * DBM is a non-conflicting feature. i.e, the kernel can safely 1854 * run a mix of CPUs with and without the feature. So, we 1855 * unconditionally enable the capability to allow any late CPU 1856 * to use the feature. We only enable the control bits on the 1857 * CPU, if it actually supports. 1858 * 1859 * We have to make sure we print the "feature" detection only 1860 * when at least one CPU actually uses it. So check if this CPU 1861 * can actually use it and print the message exactly once. 1862 * 1863 * This is safe as all CPUs (including secondary CPUs - due to the 1864 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1865 * goes through the "matches" check exactly once. Also if a CPU 1866 * matches the criteria, it is guaranteed that the CPU will turn 1867 * the DBM on, as the capability is unconditionally enabled. 1868 */ 1869 if (!detected && cpu_can_use_dbm(cap)) { 1870 detected = true; 1871 pr_info("detected: Hardware dirty bit management\n"); 1872 } 1873 1874 return true; 1875 } 1876 1877 #endif 1878 1879 #ifdef CONFIG_ARM64_AMU_EXTN 1880 1881 /* 1882 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1883 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1884 * information regarding all the events that it supports. When a CPU bit is 1885 * set in the cpumask, the user of this feature can only rely on the presence 1886 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1887 * counters are enabled or access to these counters is enabled by code 1888 * executed at higher exception levels (firmware). 1889 */ 1890 static struct cpumask amu_cpus __read_mostly; 1891 1892 bool cpu_has_amu_feat(int cpu) 1893 { 1894 return cpumask_test_cpu(cpu, &amu_cpus); 1895 } 1896 1897 int get_cpu_with_amu_feat(void) 1898 { 1899 return cpumask_any(&amu_cpus); 1900 } 1901 1902 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1903 { 1904 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1905 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1906 smp_processor_id()); 1907 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1908 1909 /* 0 reference values signal broken/disabled counters */ 1910 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 1911 update_freq_counters_refs(); 1912 } 1913 } 1914 1915 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1916 int __unused) 1917 { 1918 /* 1919 * The AMU extension is a non-conflicting feature: the kernel can 1920 * safely run a mix of CPUs with and without support for the 1921 * activity monitors extension. Therefore, unconditionally enable 1922 * the capability to allow any late CPU to use the feature. 1923 * 1924 * With this feature unconditionally enabled, the cpu_enable 1925 * function will be called for all CPUs that match the criteria, 1926 * including secondary and hotplugged, marking this feature as 1927 * present on that respective CPU. The enable function will also 1928 * print a detection message. 1929 */ 1930 1931 return true; 1932 } 1933 #else 1934 int get_cpu_with_amu_feat(void) 1935 { 1936 return nr_cpu_ids; 1937 } 1938 #endif 1939 1940 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1941 { 1942 return is_kernel_in_hyp_mode(); 1943 } 1944 1945 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1946 { 1947 /* 1948 * Copy register values that aren't redirected by hardware. 1949 * 1950 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1951 * this value to tpidr_el2 before we patch the code. Once we've done 1952 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1953 * do anything here. 1954 */ 1955 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1956 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1957 } 1958 1959 #ifdef CONFIG_ARM64_PAN 1960 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1961 { 1962 /* 1963 * We modify PSTATE. This won't work from irq context as the PSTATE 1964 * is discarded once we return from the exception. 1965 */ 1966 WARN_ON_ONCE(in_interrupt()); 1967 1968 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1969 set_pstate_pan(1); 1970 } 1971 #endif /* CONFIG_ARM64_PAN */ 1972 1973 #ifdef CONFIG_ARM64_RAS_EXTN 1974 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1975 { 1976 /* Firmware may have left a deferred SError in this register. */ 1977 write_sysreg_s(0, SYS_DISR_EL1); 1978 } 1979 #endif /* CONFIG_ARM64_RAS_EXTN */ 1980 1981 #ifdef CONFIG_ARM64_PTR_AUTH 1982 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1983 { 1984 int boot_val, sec_val; 1985 1986 /* We don't expect to be called with SCOPE_SYSTEM */ 1987 WARN_ON(scope == SCOPE_SYSTEM); 1988 /* 1989 * The ptr-auth feature levels are not intercompatible with lower 1990 * levels. Hence we must match ptr-auth feature level of the secondary 1991 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1992 * from the sanitised register whereas direct register read is done for 1993 * the secondary CPUs. 1994 * The sanitised feature state is guaranteed to match that of the 1995 * boot CPU as a mismatched secondary CPU is parked before it gets 1996 * a chance to update the state, with the capability. 1997 */ 1998 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1999 entry->field_pos, entry->sign); 2000 if (scope & SCOPE_BOOT_CPU) 2001 return boot_val >= entry->min_field_value; 2002 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2003 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2004 entry->field_pos, entry->sign); 2005 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2006 } 2007 2008 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2009 int scope) 2010 { 2011 bool api = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2012 bool apa = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2013 bool apa3 = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2014 2015 return apa || apa3 || api; 2016 } 2017 2018 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2019 int __unused) 2020 { 2021 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2022 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2023 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2024 2025 return gpa || gpa3 || gpi; 2026 } 2027 #endif /* CONFIG_ARM64_PTR_AUTH */ 2028 2029 #ifdef CONFIG_ARM64_E0PD 2030 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2031 { 2032 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2033 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2034 } 2035 #endif /* CONFIG_ARM64_E0PD */ 2036 2037 #ifdef CONFIG_ARM64_PSEUDO_NMI 2038 static bool enable_pseudo_nmi; 2039 2040 static int __init early_enable_pseudo_nmi(char *p) 2041 { 2042 return strtobool(p, &enable_pseudo_nmi); 2043 } 2044 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 2045 2046 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2047 int scope) 2048 { 2049 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 2050 } 2051 #endif 2052 2053 #ifdef CONFIG_ARM64_BTI 2054 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2055 { 2056 /* 2057 * Use of X16/X17 for tail-calls and trampolines that jump to 2058 * function entry points using BR is a requirement for 2059 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2060 * So, be strict and forbid other BRs using other registers to 2061 * jump onto a PACIxSP instruction: 2062 */ 2063 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2064 isb(); 2065 } 2066 #endif /* CONFIG_ARM64_BTI */ 2067 2068 #ifdef CONFIG_ARM64_MTE 2069 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2070 { 2071 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2072 2073 mte_cpu_setup(); 2074 2075 /* 2076 * Clear the tags in the zero page. This needs to be done via the 2077 * linear map which has the Tagged attribute. 2078 */ 2079 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2080 mte_clear_page_tags(lm_alias(empty_zero_page)); 2081 set_page_mte_tagged(ZERO_PAGE(0)); 2082 } 2083 2084 kasan_init_hw_tags_cpu(); 2085 } 2086 #endif /* CONFIG_ARM64_MTE */ 2087 2088 static void elf_hwcap_fixup(void) 2089 { 2090 #ifdef CONFIG_ARM64_ERRATUM_1742098 2091 if (cpus_have_const_cap(ARM64_WORKAROUND_1742098)) 2092 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2093 #endif /* ARM64_ERRATUM_1742098 */ 2094 } 2095 2096 #ifdef CONFIG_KVM 2097 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2098 { 2099 return kvm_get_mode() == KVM_MODE_PROTECTED; 2100 } 2101 #endif /* CONFIG_KVM */ 2102 2103 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2104 { 2105 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2106 } 2107 2108 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2109 { 2110 set_pstate_dit(1); 2111 } 2112 2113 /* Internal helper functions to match cpu capability type */ 2114 static bool 2115 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2116 { 2117 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2118 } 2119 2120 static bool 2121 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2122 { 2123 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2124 } 2125 2126 static bool 2127 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2128 { 2129 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2130 } 2131 2132 static const struct arm64_cpu_capabilities arm64_features[] = { 2133 { 2134 .capability = ARM64_ALWAYS_BOOT, 2135 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2136 .matches = has_always, 2137 }, 2138 { 2139 .capability = ARM64_ALWAYS_SYSTEM, 2140 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2141 .matches = has_always, 2142 }, 2143 { 2144 .desc = "GIC system register CPU interface", 2145 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 2146 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2147 .matches = has_useable_gicv3_cpuif, 2148 .sys_reg = SYS_ID_AA64PFR0_EL1, 2149 .field_pos = ID_AA64PFR0_EL1_GIC_SHIFT, 2150 .field_width = 4, 2151 .sign = FTR_UNSIGNED, 2152 .min_field_value = 1, 2153 }, 2154 { 2155 .desc = "Enhanced Counter Virtualization", 2156 .capability = ARM64_HAS_ECV, 2157 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2158 .matches = has_cpuid_feature, 2159 .sys_reg = SYS_ID_AA64MMFR0_EL1, 2160 .field_pos = ID_AA64MMFR0_EL1_ECV_SHIFT, 2161 .field_width = 4, 2162 .sign = FTR_UNSIGNED, 2163 .min_field_value = 1, 2164 }, 2165 #ifdef CONFIG_ARM64_PAN 2166 { 2167 .desc = "Privileged Access Never", 2168 .capability = ARM64_HAS_PAN, 2169 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2170 .matches = has_cpuid_feature, 2171 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2172 .field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT, 2173 .field_width = 4, 2174 .sign = FTR_UNSIGNED, 2175 .min_field_value = 1, 2176 .cpu_enable = cpu_enable_pan, 2177 }, 2178 #endif /* CONFIG_ARM64_PAN */ 2179 #ifdef CONFIG_ARM64_EPAN 2180 { 2181 .desc = "Enhanced Privileged Access Never", 2182 .capability = ARM64_HAS_EPAN, 2183 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2184 .matches = has_cpuid_feature, 2185 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2186 .field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT, 2187 .field_width = 4, 2188 .sign = FTR_UNSIGNED, 2189 .min_field_value = 3, 2190 }, 2191 #endif /* CONFIG_ARM64_EPAN */ 2192 #ifdef CONFIG_ARM64_LSE_ATOMICS 2193 { 2194 .desc = "LSE atomic instructions", 2195 .capability = ARM64_HAS_LSE_ATOMICS, 2196 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2197 .matches = has_cpuid_feature, 2198 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2199 .field_pos = ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 2200 .field_width = 4, 2201 .sign = FTR_UNSIGNED, 2202 .min_field_value = 2, 2203 }, 2204 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2205 { 2206 .desc = "Software prefetching using PRFM", 2207 .capability = ARM64_HAS_NO_HW_PREFETCH, 2208 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2209 .matches = has_no_hw_prefetch, 2210 }, 2211 { 2212 .desc = "Virtualization Host Extensions", 2213 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2214 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2215 .matches = runs_at_el2, 2216 .cpu_enable = cpu_copy_el2regs, 2217 }, 2218 { 2219 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2220 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2221 .matches = has_32bit_el0, 2222 .sys_reg = SYS_ID_AA64PFR0_EL1, 2223 .sign = FTR_UNSIGNED, 2224 .field_pos = ID_AA64PFR0_EL1_EL0_SHIFT, 2225 .field_width = 4, 2226 .min_field_value = ID_AA64PFR0_EL1_ELx_32BIT_64BIT, 2227 }, 2228 #ifdef CONFIG_KVM 2229 { 2230 .desc = "32-bit EL1 Support", 2231 .capability = ARM64_HAS_32BIT_EL1, 2232 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2233 .matches = has_cpuid_feature, 2234 .sys_reg = SYS_ID_AA64PFR0_EL1, 2235 .sign = FTR_UNSIGNED, 2236 .field_pos = ID_AA64PFR0_EL1_EL1_SHIFT, 2237 .field_width = 4, 2238 .min_field_value = ID_AA64PFR0_EL1_ELx_32BIT_64BIT, 2239 }, 2240 { 2241 .desc = "Protected KVM", 2242 .capability = ARM64_KVM_PROTECTED_MODE, 2243 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2244 .matches = is_kvm_protected_mode, 2245 }, 2246 #endif 2247 { 2248 .desc = "Kernel page table isolation (KPTI)", 2249 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2250 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2251 /* 2252 * The ID feature fields below are used to indicate that 2253 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2254 * more details. 2255 */ 2256 .sys_reg = SYS_ID_AA64PFR0_EL1, 2257 .field_pos = ID_AA64PFR0_EL1_CSV3_SHIFT, 2258 .field_width = 4, 2259 .min_field_value = 1, 2260 .matches = unmap_kernel_at_el0, 2261 .cpu_enable = kpti_install_ng_mappings, 2262 }, 2263 { 2264 /* FP/SIMD is not implemented */ 2265 .capability = ARM64_HAS_NO_FPSIMD, 2266 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2267 .min_field_value = 0, 2268 .matches = has_no_fpsimd, 2269 }, 2270 #ifdef CONFIG_ARM64_PMEM 2271 { 2272 .desc = "Data cache clean to Point of Persistence", 2273 .capability = ARM64_HAS_DCPOP, 2274 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2275 .matches = has_cpuid_feature, 2276 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2277 .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT, 2278 .field_width = 4, 2279 .min_field_value = 1, 2280 }, 2281 { 2282 .desc = "Data cache clean to Point of Deep Persistence", 2283 .capability = ARM64_HAS_DCPODP, 2284 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2285 .matches = has_cpuid_feature, 2286 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2287 .sign = FTR_UNSIGNED, 2288 .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT, 2289 .field_width = 4, 2290 .min_field_value = 2, 2291 }, 2292 #endif 2293 #ifdef CONFIG_ARM64_SVE 2294 { 2295 .desc = "Scalable Vector Extension", 2296 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2297 .capability = ARM64_SVE, 2298 .sys_reg = SYS_ID_AA64PFR0_EL1, 2299 .sign = FTR_UNSIGNED, 2300 .field_pos = ID_AA64PFR0_EL1_SVE_SHIFT, 2301 .field_width = 4, 2302 .min_field_value = ID_AA64PFR0_EL1_SVE_IMP, 2303 .matches = has_cpuid_feature, 2304 .cpu_enable = sve_kernel_enable, 2305 }, 2306 #endif /* CONFIG_ARM64_SVE */ 2307 #ifdef CONFIG_ARM64_RAS_EXTN 2308 { 2309 .desc = "RAS Extension Support", 2310 .capability = ARM64_HAS_RAS_EXTN, 2311 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2312 .matches = has_cpuid_feature, 2313 .sys_reg = SYS_ID_AA64PFR0_EL1, 2314 .sign = FTR_UNSIGNED, 2315 .field_pos = ID_AA64PFR0_EL1_RAS_SHIFT, 2316 .field_width = 4, 2317 .min_field_value = ID_AA64PFR0_EL1_RAS_IMP, 2318 .cpu_enable = cpu_clear_disr, 2319 }, 2320 #endif /* CONFIG_ARM64_RAS_EXTN */ 2321 #ifdef CONFIG_ARM64_AMU_EXTN 2322 { 2323 /* 2324 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 2325 * Therefore, don't provide .desc as we don't want the detection 2326 * message to be shown until at least one CPU is detected to 2327 * support the feature. 2328 */ 2329 .capability = ARM64_HAS_AMU_EXTN, 2330 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2331 .matches = has_amu, 2332 .sys_reg = SYS_ID_AA64PFR0_EL1, 2333 .sign = FTR_UNSIGNED, 2334 .field_pos = ID_AA64PFR0_EL1_AMU_SHIFT, 2335 .field_width = 4, 2336 .min_field_value = ID_AA64PFR0_EL1_AMU_IMP, 2337 .cpu_enable = cpu_amu_enable, 2338 }, 2339 #endif /* CONFIG_ARM64_AMU_EXTN */ 2340 { 2341 .desc = "Data cache clean to the PoU not required for I/D coherence", 2342 .capability = ARM64_HAS_CACHE_IDC, 2343 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2344 .matches = has_cache_idc, 2345 .cpu_enable = cpu_emulate_effective_ctr, 2346 }, 2347 { 2348 .desc = "Instruction cache invalidation not required for I/D coherence", 2349 .capability = ARM64_HAS_CACHE_DIC, 2350 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2351 .matches = has_cache_dic, 2352 }, 2353 { 2354 .desc = "Stage-2 Force Write-Back", 2355 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2356 .capability = ARM64_HAS_STAGE2_FWB, 2357 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2358 .sign = FTR_UNSIGNED, 2359 .field_pos = ID_AA64MMFR2_EL1_FWB_SHIFT, 2360 .field_width = 4, 2361 .min_field_value = 1, 2362 .matches = has_cpuid_feature, 2363 }, 2364 { 2365 .desc = "ARMv8.4 Translation Table Level", 2366 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2367 .capability = ARM64_HAS_ARMv8_4_TTL, 2368 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2369 .sign = FTR_UNSIGNED, 2370 .field_pos = ID_AA64MMFR2_EL1_TTL_SHIFT, 2371 .field_width = 4, 2372 .min_field_value = 1, 2373 .matches = has_cpuid_feature, 2374 }, 2375 { 2376 .desc = "TLB range maintenance instructions", 2377 .capability = ARM64_HAS_TLB_RANGE, 2378 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2379 .matches = has_cpuid_feature, 2380 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2381 .field_pos = ID_AA64ISAR0_EL1_TLB_SHIFT, 2382 .field_width = 4, 2383 .sign = FTR_UNSIGNED, 2384 .min_field_value = ID_AA64ISAR0_EL1_TLB_RANGE, 2385 }, 2386 #ifdef CONFIG_ARM64_HW_AFDBM 2387 { 2388 /* 2389 * Since we turn this on always, we don't want the user to 2390 * think that the feature is available when it may not be. 2391 * So hide the description. 2392 * 2393 * .desc = "Hardware pagetable Dirty Bit Management", 2394 * 2395 */ 2396 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2397 .capability = ARM64_HW_DBM, 2398 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2399 .sign = FTR_UNSIGNED, 2400 .field_pos = ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 2401 .field_width = 4, 2402 .min_field_value = 2, 2403 .matches = has_hw_dbm, 2404 .cpu_enable = cpu_enable_hw_dbm, 2405 }, 2406 #endif 2407 { 2408 .desc = "CRC32 instructions", 2409 .capability = ARM64_HAS_CRC32, 2410 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2411 .matches = has_cpuid_feature, 2412 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2413 .field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT, 2414 .field_width = 4, 2415 .min_field_value = 1, 2416 }, 2417 { 2418 .desc = "Speculative Store Bypassing Safe (SSBS)", 2419 .capability = ARM64_SSBS, 2420 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2421 .matches = has_cpuid_feature, 2422 .sys_reg = SYS_ID_AA64PFR1_EL1, 2423 .field_pos = ID_AA64PFR1_EL1_SSBS_SHIFT, 2424 .field_width = 4, 2425 .sign = FTR_UNSIGNED, 2426 .min_field_value = ID_AA64PFR1_EL1_SSBS_IMP, 2427 }, 2428 #ifdef CONFIG_ARM64_CNP 2429 { 2430 .desc = "Common not Private translations", 2431 .capability = ARM64_HAS_CNP, 2432 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2433 .matches = has_useable_cnp, 2434 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2435 .sign = FTR_UNSIGNED, 2436 .field_pos = ID_AA64MMFR2_EL1_CnP_SHIFT, 2437 .field_width = 4, 2438 .min_field_value = 1, 2439 .cpu_enable = cpu_enable_cnp, 2440 }, 2441 #endif 2442 { 2443 .desc = "Speculation barrier (SB)", 2444 .capability = ARM64_HAS_SB, 2445 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2446 .matches = has_cpuid_feature, 2447 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2448 .field_pos = ID_AA64ISAR1_EL1_SB_SHIFT, 2449 .field_width = 4, 2450 .sign = FTR_UNSIGNED, 2451 .min_field_value = 1, 2452 }, 2453 #ifdef CONFIG_ARM64_PTR_AUTH 2454 { 2455 .desc = "Address authentication (architected QARMA5 algorithm)", 2456 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2457 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2458 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2459 .sign = FTR_UNSIGNED, 2460 .field_pos = ID_AA64ISAR1_EL1_APA_SHIFT, 2461 .field_width = 4, 2462 .min_field_value = ID_AA64ISAR1_EL1_APA_PAuth, 2463 .matches = has_address_auth_cpucap, 2464 }, 2465 { 2466 .desc = "Address authentication (architected QARMA3 algorithm)", 2467 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2468 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2469 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2470 .sign = FTR_UNSIGNED, 2471 .field_pos = ID_AA64ISAR2_EL1_APA3_SHIFT, 2472 .field_width = 4, 2473 .min_field_value = ID_AA64ISAR2_EL1_APA3_PAuth, 2474 .matches = has_address_auth_cpucap, 2475 }, 2476 { 2477 .desc = "Address authentication (IMP DEF algorithm)", 2478 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2479 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2480 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2481 .sign = FTR_UNSIGNED, 2482 .field_pos = ID_AA64ISAR1_EL1_API_SHIFT, 2483 .field_width = 4, 2484 .min_field_value = ID_AA64ISAR1_EL1_API_PAuth, 2485 .matches = has_address_auth_cpucap, 2486 }, 2487 { 2488 .capability = ARM64_HAS_ADDRESS_AUTH, 2489 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2490 .matches = has_address_auth_metacap, 2491 }, 2492 { 2493 .desc = "Generic authentication (architected QARMA5 algorithm)", 2494 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2495 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2496 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2497 .sign = FTR_UNSIGNED, 2498 .field_pos = ID_AA64ISAR1_EL1_GPA_SHIFT, 2499 .field_width = 4, 2500 .min_field_value = ID_AA64ISAR1_EL1_GPA_IMP, 2501 .matches = has_cpuid_feature, 2502 }, 2503 { 2504 .desc = "Generic authentication (architected QARMA3 algorithm)", 2505 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2506 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2507 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2508 .sign = FTR_UNSIGNED, 2509 .field_pos = ID_AA64ISAR2_EL1_GPA3_SHIFT, 2510 .field_width = 4, 2511 .min_field_value = ID_AA64ISAR2_EL1_GPA3_IMP, 2512 .matches = has_cpuid_feature, 2513 }, 2514 { 2515 .desc = "Generic authentication (IMP DEF algorithm)", 2516 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2517 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2518 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2519 .sign = FTR_UNSIGNED, 2520 .field_pos = ID_AA64ISAR1_EL1_GPI_SHIFT, 2521 .field_width = 4, 2522 .min_field_value = ID_AA64ISAR1_EL1_GPI_IMP, 2523 .matches = has_cpuid_feature, 2524 }, 2525 { 2526 .capability = ARM64_HAS_GENERIC_AUTH, 2527 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2528 .matches = has_generic_auth, 2529 }, 2530 #endif /* CONFIG_ARM64_PTR_AUTH */ 2531 #ifdef CONFIG_ARM64_PSEUDO_NMI 2532 { 2533 /* 2534 * Depends on having GICv3 2535 */ 2536 .desc = "IRQ priority masking", 2537 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2538 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2539 .matches = can_use_gic_priorities, 2540 .sys_reg = SYS_ID_AA64PFR0_EL1, 2541 .field_pos = ID_AA64PFR0_EL1_GIC_SHIFT, 2542 .field_width = 4, 2543 .sign = FTR_UNSIGNED, 2544 .min_field_value = 1, 2545 }, 2546 #endif 2547 #ifdef CONFIG_ARM64_E0PD 2548 { 2549 .desc = "E0PD", 2550 .capability = ARM64_HAS_E0PD, 2551 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2552 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2553 .sign = FTR_UNSIGNED, 2554 .field_width = 4, 2555 .field_pos = ID_AA64MMFR2_EL1_E0PD_SHIFT, 2556 .matches = has_cpuid_feature, 2557 .min_field_value = 1, 2558 .cpu_enable = cpu_enable_e0pd, 2559 }, 2560 #endif 2561 { 2562 .desc = "Random Number Generator", 2563 .capability = ARM64_HAS_RNG, 2564 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2565 .matches = has_cpuid_feature, 2566 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2567 .field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT, 2568 .field_width = 4, 2569 .sign = FTR_UNSIGNED, 2570 .min_field_value = 1, 2571 }, 2572 #ifdef CONFIG_ARM64_BTI 2573 { 2574 .desc = "Branch Target Identification", 2575 .capability = ARM64_BTI, 2576 #ifdef CONFIG_ARM64_BTI_KERNEL 2577 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2578 #else 2579 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2580 #endif 2581 .matches = has_cpuid_feature, 2582 .cpu_enable = bti_enable, 2583 .sys_reg = SYS_ID_AA64PFR1_EL1, 2584 .field_pos = ID_AA64PFR1_EL1_BT_SHIFT, 2585 .field_width = 4, 2586 .min_field_value = ID_AA64PFR1_EL1_BT_IMP, 2587 .sign = FTR_UNSIGNED, 2588 }, 2589 #endif 2590 #ifdef CONFIG_ARM64_MTE 2591 { 2592 .desc = "Memory Tagging Extension", 2593 .capability = ARM64_MTE, 2594 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2595 .matches = has_cpuid_feature, 2596 .sys_reg = SYS_ID_AA64PFR1_EL1, 2597 .field_pos = ID_AA64PFR1_EL1_MTE_SHIFT, 2598 .field_width = 4, 2599 .min_field_value = ID_AA64PFR1_EL1_MTE_MTE2, 2600 .sign = FTR_UNSIGNED, 2601 .cpu_enable = cpu_enable_mte, 2602 }, 2603 { 2604 .desc = "Asymmetric MTE Tag Check Fault", 2605 .capability = ARM64_MTE_ASYMM, 2606 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2607 .matches = has_cpuid_feature, 2608 .sys_reg = SYS_ID_AA64PFR1_EL1, 2609 .field_pos = ID_AA64PFR1_EL1_MTE_SHIFT, 2610 .field_width = 4, 2611 .min_field_value = ID_AA64PFR1_EL1_MTE_MTE3, 2612 .sign = FTR_UNSIGNED, 2613 }, 2614 #endif /* CONFIG_ARM64_MTE */ 2615 { 2616 .desc = "RCpc load-acquire (LDAPR)", 2617 .capability = ARM64_HAS_LDAPR, 2618 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2619 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2620 .sign = FTR_UNSIGNED, 2621 .field_pos = ID_AA64ISAR1_EL1_LRCPC_SHIFT, 2622 .field_width = 4, 2623 .matches = has_cpuid_feature, 2624 .min_field_value = 1, 2625 }, 2626 #ifdef CONFIG_ARM64_SME 2627 { 2628 .desc = "Scalable Matrix Extension", 2629 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2630 .capability = ARM64_SME, 2631 .sys_reg = SYS_ID_AA64PFR1_EL1, 2632 .sign = FTR_UNSIGNED, 2633 .field_pos = ID_AA64PFR1_EL1_SME_SHIFT, 2634 .field_width = 4, 2635 .min_field_value = ID_AA64PFR1_EL1_SME_IMP, 2636 .matches = has_cpuid_feature, 2637 .cpu_enable = sme_kernel_enable, 2638 }, 2639 /* FA64 should be sorted after the base SME capability */ 2640 { 2641 .desc = "FA64", 2642 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2643 .capability = ARM64_SME_FA64, 2644 .sys_reg = SYS_ID_AA64SMFR0_EL1, 2645 .sign = FTR_UNSIGNED, 2646 .field_pos = ID_AA64SMFR0_EL1_FA64_SHIFT, 2647 .field_width = 1, 2648 .min_field_value = ID_AA64SMFR0_EL1_FA64_IMP, 2649 .matches = has_cpuid_feature, 2650 .cpu_enable = fa64_kernel_enable, 2651 }, 2652 #endif /* CONFIG_ARM64_SME */ 2653 { 2654 .desc = "WFx with timeout", 2655 .capability = ARM64_HAS_WFXT, 2656 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2657 .sys_reg = SYS_ID_AA64ISAR2_EL1, 2658 .sign = FTR_UNSIGNED, 2659 .field_pos = ID_AA64ISAR2_EL1_WFxT_SHIFT, 2660 .field_width = 4, 2661 .matches = has_cpuid_feature, 2662 .min_field_value = ID_AA64ISAR2_EL1_WFxT_IMP, 2663 }, 2664 { 2665 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2666 .capability = ARM64_HAS_TIDCP1, 2667 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2668 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2669 .sign = FTR_UNSIGNED, 2670 .field_pos = ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 2671 .field_width = 4, 2672 .min_field_value = ID_AA64MMFR1_EL1_TIDCP1_IMP, 2673 .matches = has_cpuid_feature, 2674 .cpu_enable = cpu_trap_el0_impdef, 2675 }, 2676 { 2677 .desc = "Data independent timing control (DIT)", 2678 .capability = ARM64_HAS_DIT, 2679 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2680 .sys_reg = SYS_ID_AA64PFR0_EL1, 2681 .sign = FTR_UNSIGNED, 2682 .field_pos = ID_AA64PFR0_EL1_DIT_SHIFT, 2683 .field_width = 4, 2684 .min_field_value = ID_AA64PFR0_EL1_DIT_IMP, 2685 .matches = has_cpuid_feature, 2686 .cpu_enable = cpu_enable_dit, 2687 }, 2688 {}, 2689 }; 2690 2691 #define HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ 2692 .matches = has_user_cpuid_feature, \ 2693 .sys_reg = reg, \ 2694 .field_pos = field, \ 2695 .field_width = width, \ 2696 .sign = s, \ 2697 .min_field_value = min_value, 2698 2699 #define __HWCAP_CAP(name, cap_type, cap) \ 2700 .desc = name, \ 2701 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2702 .hwcap_type = cap_type, \ 2703 .hwcap = cap, \ 2704 2705 #define HWCAP_CAP(reg, field, width, s, min_value, cap_type, cap) \ 2706 { \ 2707 __HWCAP_CAP(#cap, cap_type, cap) \ 2708 HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \ 2709 } 2710 2711 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2712 { \ 2713 __HWCAP_CAP(#cap, cap_type, cap) \ 2714 .matches = cpucap_multi_entry_cap_matches, \ 2715 .match_list = list, \ 2716 } 2717 2718 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2719 { \ 2720 __HWCAP_CAP(#cap, cap_type, cap) \ 2721 .matches = match, \ 2722 } 2723 2724 #ifdef CONFIG_ARM64_PTR_AUTH 2725 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2726 { 2727 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_APA_SHIFT, 2728 4, FTR_UNSIGNED, 2729 ID_AA64ISAR1_EL1_APA_PAuth) 2730 }, 2731 { 2732 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_APA3_SHIFT, 2733 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_APA3_PAuth) 2734 }, 2735 { 2736 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT, 2737 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_API_PAuth) 2738 }, 2739 {}, 2740 }; 2741 2742 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2743 { 2744 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPA_SHIFT, 2745 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP) 2746 }, 2747 { 2748 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_GPA3_SHIFT, 2749 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_GPA3_IMP) 2750 }, 2751 { 2752 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT, 2753 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPI_IMP) 2754 }, 2755 {}, 2756 }; 2757 #endif 2758 2759 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2760 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2761 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2762 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2763 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2764 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2765 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2766 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2767 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2768 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2769 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2770 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2771 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2772 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2773 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2774 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2775 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2776 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2777 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2778 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2779 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2780 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2781 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2782 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2783 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2784 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2785 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2786 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2787 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2788 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2789 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2790 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_EBF16), 2791 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2792 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2793 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_EL1_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2794 #ifdef CONFIG_ARM64_SVE 2795 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_EL1_SVE_IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 2796 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 2797 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2798 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2799 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2800 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BitPerm_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2801 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2802 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 2803 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SHA3_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2804 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SM4_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2805 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_I8MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2806 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F32MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2807 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F64MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2808 #endif 2809 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_SSBS_SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2810 #ifdef CONFIG_ARM64_BTI 2811 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_BT_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_BT_IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 2812 #endif 2813 #ifdef CONFIG_ARM64_PTR_AUTH 2814 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2815 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2816 #endif 2817 #ifdef CONFIG_ARM64_MTE 2818 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 2819 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 2820 #endif /* CONFIG_ARM64_MTE */ 2821 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), 2822 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), 2823 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_CSSC_IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 2824 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_RPRFM_IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 2825 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2826 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 2827 #ifdef CONFIG_ARM64_SME 2828 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_SME_IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 2829 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 2830 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I16I64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 2831 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F64F64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 2832 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I8I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 2833 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 2834 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_B16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 2835 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F32F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 2836 #endif /* CONFIG_ARM64_SME */ 2837 {}, 2838 }; 2839 2840 #ifdef CONFIG_COMPAT 2841 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2842 { 2843 /* 2844 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2845 * in line with that of arm32 as in vfp_init(). We make sure that the 2846 * check is future proof, by making sure value is non-zero. 2847 */ 2848 u32 mvfr1; 2849 2850 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2851 if (scope == SCOPE_SYSTEM) 2852 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2853 else 2854 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2855 2856 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 2857 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 2858 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 2859 } 2860 #endif 2861 2862 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2863 #ifdef CONFIG_COMPAT 2864 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2865 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_EL1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2866 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2867 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_EL1_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2868 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_EL1_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2869 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2870 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2871 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2872 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2873 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2874 #endif 2875 {}, 2876 }; 2877 2878 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2879 { 2880 switch (cap->hwcap_type) { 2881 case CAP_HWCAP: 2882 cpu_set_feature(cap->hwcap); 2883 break; 2884 #ifdef CONFIG_COMPAT 2885 case CAP_COMPAT_HWCAP: 2886 compat_elf_hwcap |= (u32)cap->hwcap; 2887 break; 2888 case CAP_COMPAT_HWCAP2: 2889 compat_elf_hwcap2 |= (u32)cap->hwcap; 2890 break; 2891 #endif 2892 default: 2893 WARN_ON(1); 2894 break; 2895 } 2896 } 2897 2898 /* Check if we have a particular HWCAP enabled */ 2899 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2900 { 2901 bool rc; 2902 2903 switch (cap->hwcap_type) { 2904 case CAP_HWCAP: 2905 rc = cpu_have_feature(cap->hwcap); 2906 break; 2907 #ifdef CONFIG_COMPAT 2908 case CAP_COMPAT_HWCAP: 2909 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2910 break; 2911 case CAP_COMPAT_HWCAP2: 2912 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2913 break; 2914 #endif 2915 default: 2916 WARN_ON(1); 2917 rc = false; 2918 } 2919 2920 return rc; 2921 } 2922 2923 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2924 { 2925 /* We support emulation of accesses to CPU ID feature registers */ 2926 cpu_set_named_feature(CPUID); 2927 for (; hwcaps->matches; hwcaps++) 2928 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2929 cap_set_elf_hwcap(hwcaps); 2930 } 2931 2932 static void update_cpu_capabilities(u16 scope_mask) 2933 { 2934 int i; 2935 const struct arm64_cpu_capabilities *caps; 2936 2937 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2938 for (i = 0; i < ARM64_NCAPS; i++) { 2939 caps = cpu_hwcaps_ptrs[i]; 2940 if (!caps || !(caps->type & scope_mask) || 2941 cpus_have_cap(caps->capability) || 2942 !caps->matches(caps, cpucap_default_scope(caps))) 2943 continue; 2944 2945 if (caps->desc) 2946 pr_info("detected: %s\n", caps->desc); 2947 cpus_set_cap(caps->capability); 2948 2949 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2950 set_bit(caps->capability, boot_capabilities); 2951 } 2952 } 2953 2954 /* 2955 * Enable all the available capabilities on this CPU. The capabilities 2956 * with BOOT_CPU scope are handled separately and hence skipped here. 2957 */ 2958 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2959 { 2960 int i; 2961 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2962 2963 for_each_available_cap(i) { 2964 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2965 2966 if (WARN_ON(!cap)) 2967 continue; 2968 2969 if (!(cap->type & non_boot_scope)) 2970 continue; 2971 2972 if (cap->cpu_enable) 2973 cap->cpu_enable(cap); 2974 } 2975 return 0; 2976 } 2977 2978 /* 2979 * Run through the enabled capabilities and enable() it on all active 2980 * CPUs 2981 */ 2982 static void __init enable_cpu_capabilities(u16 scope_mask) 2983 { 2984 int i; 2985 const struct arm64_cpu_capabilities *caps; 2986 bool boot_scope; 2987 2988 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2989 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2990 2991 for (i = 0; i < ARM64_NCAPS; i++) { 2992 unsigned int num; 2993 2994 caps = cpu_hwcaps_ptrs[i]; 2995 if (!caps || !(caps->type & scope_mask)) 2996 continue; 2997 num = caps->capability; 2998 if (!cpus_have_cap(num)) 2999 continue; 3000 3001 if (boot_scope && caps->cpu_enable) 3002 /* 3003 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3004 * before any secondary CPU boots. Thus, each secondary 3005 * will enable the capability as appropriate via 3006 * check_local_cpu_capabilities(). The only exception is 3007 * the boot CPU, for which the capability must be 3008 * enabled here. This approach avoids costly 3009 * stop_machine() calls for this case. 3010 */ 3011 caps->cpu_enable(caps); 3012 } 3013 3014 /* 3015 * For all non-boot scope capabilities, use stop_machine() 3016 * as it schedules the work allowing us to modify PSTATE, 3017 * instead of on_each_cpu() which uses an IPI, giving us a 3018 * PSTATE that disappears when we return. 3019 */ 3020 if (!boot_scope) 3021 stop_machine(cpu_enable_non_boot_scope_capabilities, 3022 NULL, cpu_online_mask); 3023 } 3024 3025 /* 3026 * Run through the list of capabilities to check for conflicts. 3027 * If the system has already detected a capability, take necessary 3028 * action on this CPU. 3029 */ 3030 static void verify_local_cpu_caps(u16 scope_mask) 3031 { 3032 int i; 3033 bool cpu_has_cap, system_has_cap; 3034 const struct arm64_cpu_capabilities *caps; 3035 3036 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3037 3038 for (i = 0; i < ARM64_NCAPS; i++) { 3039 caps = cpu_hwcaps_ptrs[i]; 3040 if (!caps || !(caps->type & scope_mask)) 3041 continue; 3042 3043 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3044 system_has_cap = cpus_have_cap(caps->capability); 3045 3046 if (system_has_cap) { 3047 /* 3048 * Check if the new CPU misses an advertised feature, 3049 * which is not safe to miss. 3050 */ 3051 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3052 break; 3053 /* 3054 * We have to issue cpu_enable() irrespective of 3055 * whether the CPU has it or not, as it is enabeld 3056 * system wide. It is upto the call back to take 3057 * appropriate action on this CPU. 3058 */ 3059 if (caps->cpu_enable) 3060 caps->cpu_enable(caps); 3061 } else { 3062 /* 3063 * Check if the CPU has this capability if it isn't 3064 * safe to have when the system doesn't. 3065 */ 3066 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3067 break; 3068 } 3069 } 3070 3071 if (i < ARM64_NCAPS) { 3072 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3073 smp_processor_id(), caps->capability, 3074 caps->desc, system_has_cap, cpu_has_cap); 3075 3076 if (cpucap_panic_on_conflict(caps)) 3077 cpu_panic_kernel(); 3078 else 3079 cpu_die_early(); 3080 } 3081 } 3082 3083 /* 3084 * Check for CPU features that are used in early boot 3085 * based on the Boot CPU value. 3086 */ 3087 static void check_early_cpu_features(void) 3088 { 3089 verify_cpu_asid_bits(); 3090 3091 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3092 } 3093 3094 static void 3095 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3096 { 3097 3098 for (; caps->matches; caps++) 3099 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3100 pr_crit("CPU%d: missing HWCAP: %s\n", 3101 smp_processor_id(), caps->desc); 3102 cpu_die_early(); 3103 } 3104 } 3105 3106 static void verify_local_elf_hwcaps(void) 3107 { 3108 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3109 3110 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3111 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3112 } 3113 3114 static void verify_sve_features(void) 3115 { 3116 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 3117 u64 zcr = read_zcr_features(); 3118 3119 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 3120 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 3121 3122 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) { 3123 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3124 smp_processor_id()); 3125 cpu_die_early(); 3126 } 3127 3128 /* Add checks on other ZCR bits here if necessary */ 3129 } 3130 3131 static void verify_sme_features(void) 3132 { 3133 u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1); 3134 u64 smcr = read_smcr_features(); 3135 3136 unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK; 3137 unsigned int len = smcr & SMCR_ELx_LEN_MASK; 3138 3139 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) { 3140 pr_crit("CPU%d: SME: vector length support mismatch\n", 3141 smp_processor_id()); 3142 cpu_die_early(); 3143 } 3144 3145 /* Add checks on other SMCR bits here if necessary */ 3146 } 3147 3148 static void verify_hyp_capabilities(void) 3149 { 3150 u64 safe_mmfr1, mmfr0, mmfr1; 3151 int parange, ipa_max; 3152 unsigned int safe_vmid_bits, vmid_bits; 3153 3154 if (!IS_ENABLED(CONFIG_KVM)) 3155 return; 3156 3157 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3158 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3159 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3160 3161 /* Verify VMID bits */ 3162 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3163 vmid_bits = get_vmid_bits(mmfr1); 3164 if (vmid_bits < safe_vmid_bits) { 3165 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3166 cpu_die_early(); 3167 } 3168 3169 /* Verify IPA range */ 3170 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3171 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3172 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3173 if (ipa_max < get_kvm_ipa_limit()) { 3174 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3175 cpu_die_early(); 3176 } 3177 } 3178 3179 /* 3180 * Run through the enabled system capabilities and enable() it on this CPU. 3181 * The capabilities were decided based on the available CPUs at the boot time. 3182 * Any new CPU should match the system wide status of the capability. If the 3183 * new CPU doesn't have a capability which the system now has enabled, we 3184 * cannot do anything to fix it up and could cause unexpected failures. So 3185 * we park the CPU. 3186 */ 3187 static void verify_local_cpu_capabilities(void) 3188 { 3189 /* 3190 * The capabilities with SCOPE_BOOT_CPU are checked from 3191 * check_early_cpu_features(), as they need to be verified 3192 * on all secondary CPUs. 3193 */ 3194 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3195 verify_local_elf_hwcaps(); 3196 3197 if (system_supports_sve()) 3198 verify_sve_features(); 3199 3200 if (system_supports_sme()) 3201 verify_sme_features(); 3202 3203 if (is_hyp_mode_available()) 3204 verify_hyp_capabilities(); 3205 } 3206 3207 void check_local_cpu_capabilities(void) 3208 { 3209 /* 3210 * All secondary CPUs should conform to the early CPU features 3211 * in use by the kernel based on boot CPU. 3212 */ 3213 check_early_cpu_features(); 3214 3215 /* 3216 * If we haven't finalised the system capabilities, this CPU gets 3217 * a chance to update the errata work arounds and local features. 3218 * Otherwise, this CPU should verify that it has all the system 3219 * advertised capabilities. 3220 */ 3221 if (!system_capabilities_finalized()) 3222 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3223 else 3224 verify_local_cpu_capabilities(); 3225 } 3226 3227 static void __init setup_boot_cpu_capabilities(void) 3228 { 3229 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 3230 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3231 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 3232 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3233 } 3234 3235 bool this_cpu_has_cap(unsigned int n) 3236 { 3237 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3238 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 3239 3240 if (cap) 3241 return cap->matches(cap, SCOPE_LOCAL_CPU); 3242 } 3243 3244 return false; 3245 } 3246 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3247 3248 /* 3249 * This helper function is used in a narrow window when, 3250 * - The system wide safe registers are set with all the SMP CPUs and, 3251 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 3252 * In all other cases cpus_have_{const_}cap() should be used. 3253 */ 3254 static bool __maybe_unused __system_matches_cap(unsigned int n) 3255 { 3256 if (n < ARM64_NCAPS) { 3257 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 3258 3259 if (cap) 3260 return cap->matches(cap, SCOPE_SYSTEM); 3261 } 3262 return false; 3263 } 3264 3265 void cpu_set_feature(unsigned int num) 3266 { 3267 set_bit(num, elf_hwcap); 3268 } 3269 3270 bool cpu_have_feature(unsigned int num) 3271 { 3272 return test_bit(num, elf_hwcap); 3273 } 3274 EXPORT_SYMBOL_GPL(cpu_have_feature); 3275 3276 unsigned long cpu_get_elf_hwcap(void) 3277 { 3278 /* 3279 * We currently only populate the first 32 bits of AT_HWCAP. Please 3280 * note that for userspace compatibility we guarantee that bits 62 3281 * and 63 will always be returned as 0. 3282 */ 3283 return elf_hwcap[0]; 3284 } 3285 3286 unsigned long cpu_get_elf_hwcap2(void) 3287 { 3288 return elf_hwcap[1]; 3289 } 3290 3291 static void __init setup_system_capabilities(void) 3292 { 3293 /* 3294 * We have finalised the system-wide safe feature 3295 * registers, finalise the capabilities that depend 3296 * on it. Also enable all the available capabilities, 3297 * that are not enabled already. 3298 */ 3299 update_cpu_capabilities(SCOPE_SYSTEM); 3300 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3301 } 3302 3303 void __init setup_cpu_features(void) 3304 { 3305 u32 cwg; 3306 3307 setup_system_capabilities(); 3308 setup_elf_hwcaps(arm64_elf_hwcaps); 3309 3310 if (system_supports_32bit_el0()) { 3311 setup_elf_hwcaps(compat_elf_hwcaps); 3312 elf_hwcap_fixup(); 3313 } 3314 3315 if (system_uses_ttbr0_pan()) 3316 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3317 3318 sve_setup(); 3319 sme_setup(); 3320 minsigstksz_setup(); 3321 3322 /* 3323 * Check for sane CTR_EL0.CWG value. 3324 */ 3325 cwg = cache_type_cwg(); 3326 if (!cwg) 3327 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3328 ARCH_DMA_MINALIGN); 3329 } 3330 3331 static int enable_mismatched_32bit_el0(unsigned int cpu) 3332 { 3333 /* 3334 * The first 32-bit-capable CPU we detected and so can no longer 3335 * be offlined by userspace. -1 indicates we haven't yet onlined 3336 * a 32-bit-capable CPU. 3337 */ 3338 static int lucky_winner = -1; 3339 3340 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3341 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3342 3343 if (cpu_32bit) { 3344 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3345 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3346 } 3347 3348 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3349 return 0; 3350 3351 if (lucky_winner >= 0) 3352 return 0; 3353 3354 /* 3355 * We've detected a mismatch. We need to keep one of our CPUs with 3356 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3357 * every CPU in the system for a 32-bit task. 3358 */ 3359 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3360 cpu_active_mask); 3361 get_cpu_device(lucky_winner)->offline_disabled = true; 3362 setup_elf_hwcaps(compat_elf_hwcaps); 3363 elf_hwcap_fixup(); 3364 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3365 cpu, lucky_winner); 3366 return 0; 3367 } 3368 3369 static int __init init_32bit_el0_mask(void) 3370 { 3371 if (!allow_mismatched_32bit_el0) 3372 return 0; 3373 3374 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3375 return -ENOMEM; 3376 3377 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3378 "arm64/mismatched_32bit_el0:online", 3379 enable_mismatched_32bit_el0, NULL); 3380 } 3381 subsys_initcall_sync(init_32bit_el0_mask); 3382 3383 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3384 { 3385 cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir); 3386 } 3387 3388 /* 3389 * We emulate only the following system register space. 3390 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3391 * See Table C5-6 System instruction encodings for System register accesses, 3392 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3393 */ 3394 static inline bool __attribute_const__ is_emulated(u32 id) 3395 { 3396 return (sys_reg_Op0(id) == 0x3 && 3397 sys_reg_CRn(id) == 0x0 && 3398 sys_reg_Op1(id) == 0x0 && 3399 (sys_reg_CRm(id) == 0 || 3400 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3401 } 3402 3403 /* 3404 * With CRm == 0, reg should be one of : 3405 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3406 */ 3407 static inline int emulate_id_reg(u32 id, u64 *valp) 3408 { 3409 switch (id) { 3410 case SYS_MIDR_EL1: 3411 *valp = read_cpuid_id(); 3412 break; 3413 case SYS_MPIDR_EL1: 3414 *valp = SYS_MPIDR_SAFE_VAL; 3415 break; 3416 case SYS_REVIDR_EL1: 3417 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3418 *valp = 0; 3419 break; 3420 default: 3421 return -EINVAL; 3422 } 3423 3424 return 0; 3425 } 3426 3427 static int emulate_sys_reg(u32 id, u64 *valp) 3428 { 3429 struct arm64_ftr_reg *regp; 3430 3431 if (!is_emulated(id)) 3432 return -EINVAL; 3433 3434 if (sys_reg_CRm(id) == 0) 3435 return emulate_id_reg(id, valp); 3436 3437 regp = get_arm64_ftr_reg_nowarn(id); 3438 if (regp) 3439 *valp = arm64_ftr_reg_user_value(regp); 3440 else 3441 /* 3442 * The untracked registers are either IMPLEMENTATION DEFINED 3443 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3444 */ 3445 *valp = 0; 3446 return 0; 3447 } 3448 3449 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3450 { 3451 int rc; 3452 u64 val; 3453 3454 rc = emulate_sys_reg(sys_reg, &val); 3455 if (!rc) { 3456 pt_regs_write_reg(regs, rt, val); 3457 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3458 } 3459 return rc; 3460 } 3461 3462 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3463 { 3464 u32 sys_reg, rt; 3465 3466 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3467 return false; 3468 3469 /* 3470 * sys_reg values are defined as used in mrs/msr instruction. 3471 * shift the imm value to get the encoding. 3472 */ 3473 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3474 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3475 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3476 } 3477 3478 enum mitigation_state arm64_get_meltdown_state(void) 3479 { 3480 if (__meltdown_safe) 3481 return SPECTRE_UNAFFECTED; 3482 3483 if (arm64_kernel_unmapped_at_el0()) 3484 return SPECTRE_MITIGATED; 3485 3486 return SPECTRE_VULNERABLE; 3487 } 3488 3489 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3490 char *buf) 3491 { 3492 switch (arm64_get_meltdown_state()) { 3493 case SPECTRE_UNAFFECTED: 3494 return sprintf(buf, "Not affected\n"); 3495 3496 case SPECTRE_MITIGATED: 3497 return sprintf(buf, "Mitigation: PTI\n"); 3498 3499 default: 3500 return sprintf(buf, "Vulnerable\n"); 3501 } 3502 } 3503