1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/types.h> 71 #include <linux/mm.h> 72 #include <linux/cpu.h> 73 #include <linux/kasan.h> 74 #include <asm/cpu.h> 75 #include <asm/cpufeature.h> 76 #include <asm/cpu_ops.h> 77 #include <asm/fpsimd.h> 78 #include <asm/kvm_host.h> 79 #include <asm/mmu_context.h> 80 #include <asm/mte.h> 81 #include <asm/processor.h> 82 #include <asm/sysreg.h> 83 #include <asm/traps.h> 84 #include <asm/virt.h> 85 86 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 87 static unsigned long elf_hwcap __read_mostly; 88 89 #ifdef CONFIG_COMPAT 90 #define COMPAT_ELF_HWCAP_DEFAULT \ 91 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 92 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 93 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 94 COMPAT_HWCAP_LPAE) 95 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 96 unsigned int compat_elf_hwcap2 __read_mostly; 97 #endif 98 99 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 100 EXPORT_SYMBOL(cpu_hwcaps); 101 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 102 103 /* Need also bit for ARM64_CB_PATCH */ 104 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 105 106 bool arm64_use_ng_mappings = false; 107 EXPORT_SYMBOL(arm64_use_ng_mappings); 108 109 /* 110 * Flag to indicate if we have computed the system wide 111 * capabilities based on the boot time active CPUs. This 112 * will be used to determine if a new booting CPU should 113 * go through the verification process to make sure that it 114 * supports the system capabilities, without using a hotplug 115 * notifier. This is also used to decide if we could use 116 * the fast path for checking constant CPU caps. 117 */ 118 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 119 EXPORT_SYMBOL(arm64_const_caps_ready); 120 static inline void finalize_system_capabilities(void) 121 { 122 static_branch_enable(&arm64_const_caps_ready); 123 } 124 125 void dump_cpu_features(void) 126 { 127 /* file-wide pr_fmt adds "CPU features: " prefix */ 128 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 129 } 130 131 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 132 EXPORT_SYMBOL(cpu_hwcap_keys); 133 134 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 135 { \ 136 .sign = SIGNED, \ 137 .visible = VISIBLE, \ 138 .strict = STRICT, \ 139 .type = TYPE, \ 140 .shift = SHIFT, \ 141 .width = WIDTH, \ 142 .safe_val = SAFE_VAL, \ 143 } 144 145 /* Define a feature with unsigned values */ 146 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 147 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 148 149 /* Define a feature with a signed value */ 150 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 151 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 152 153 #define ARM64_FTR_END \ 154 { \ 155 .width = 0, \ 156 } 157 158 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 159 160 static bool __system_matches_cap(unsigned int n); 161 162 /* 163 * NOTE: Any changes to the visibility of features should be kept in 164 * sync with the documentation of the CPU feature register ABI. 165 */ 166 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 167 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), 168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0), 169 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 170 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 171 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 172 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 173 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 174 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 175 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 176 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 181 ARM64_FTR_END, 182 }; 183 184 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 192 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 194 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 199 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), 200 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 201 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 203 ARM64_FTR_END, 204 }; 205 206 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 208 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 214 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 217 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 218 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 219 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 223 ARM64_FTR_END, 224 }; 225 226 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 230 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 232 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 233 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 234 ARM64_FTR_END, 235 }; 236 237 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 238 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 239 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 241 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 243 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 245 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 247 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 249 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 256 ARM64_FTR_END, 257 }; 258 259 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), 263 /* 264 * Page size not being supported at Stage-2 is not fatal. You 265 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 266 * your favourite nesting hypervisor. 267 * 268 * There is a small corner case where the hypervisor explicitly 269 * advertises a given granule size at Stage-2 (value 2) on some 270 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 271 * vCPUs. Although this is not forbidden by the architecture, it 272 * indicates that the hypervisor is being silly (or buggy). 273 * 274 * We make no effort to cope with this and pretend that if these 275 * fields are inconsistent across vCPUs, then it isn't worth 276 * trying to bring KVM up. 277 */ 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 281 /* 282 * We already refuse to boot CPUs that don't support our configured 283 * page size, so we can only detect mismatches for a page size other 284 * than the one we're currently using. Unfortunately, SoCs like this 285 * exist in the wild so, even though we don't like it, we'll have to go 286 * along with it and treat them as non-strict. 287 */ 288 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 289 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 291 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 293 /* Linux shouldn't care about secure memory */ 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 297 /* 298 * Differing PARange is fine as long as all peripherals and memory are mapped 299 * within the minimum PARange of all CPUs 300 */ 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 302 ARM64_FTR_END, 303 }; 304 305 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), 310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 316 ARM64_FTR_END, 317 }; 318 319 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0), 329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 335 ARM64_FTR_END, 336 }; 337 338 static const struct arm64_ftr_bits ftr_ctr[] = { 339 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 340 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 341 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 342 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 345 /* 346 * Linux can handle differing I-cache policies. Userspace JITs will 347 * make use of *minLine. 348 * If we have differing I-cache policies, report it as the weakest - VIPT. 349 */ 350 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 351 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 352 ARM64_FTR_END, 353 }; 354 355 static struct arm64_ftr_override __ro_after_init no_override = { }; 356 357 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 358 .name = "SYS_CTR_EL0", 359 .ftr_bits = ftr_ctr, 360 .override = &no_override, 361 }; 362 363 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 364 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 369 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 372 ARM64_FTR_END, 373 }; 374 375 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 376 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 381 /* 382 * We can instantiate multiple PMU instances with different levels 383 * of support. 384 */ 385 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), 387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 388 ARM64_FTR_END, 389 }; 390 391 static const struct arm64_ftr_bits ftr_mvfr2[] = { 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 394 ARM64_FTR_END, 395 }; 396 397 static const struct arm64_ftr_bits ftr_dczid[] = { 398 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), 399 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), 400 ARM64_FTR_END, 401 }; 402 403 static const struct arm64_ftr_bits ftr_id_isar0[] = { 404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 410 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 411 ARM64_FTR_END, 412 }; 413 414 static const struct arm64_ftr_bits ftr_id_isar5[] = { 415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 417 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 419 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 421 ARM64_FTR_END, 422 }; 423 424 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 432 433 /* 434 * SpecSEI = 1 indicates that the PE might generate an SError on an 435 * external abort on speculative read. It is safe to assume that an 436 * SError might be generated than it will not be. Hence it has been 437 * classified as FTR_HIGHER_SAFE. 438 */ 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 440 ARM64_FTR_END, 441 }; 442 443 static const struct arm64_ftr_bits ftr_id_isar4[] = { 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 452 ARM64_FTR_END, 453 }; 454 455 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 457 ARM64_FTR_END, 458 }; 459 460 static const struct arm64_ftr_bits ftr_id_isar6[] = { 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 468 ARM64_FTR_END, 469 }; 470 471 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 478 ARM64_FTR_END, 479 }; 480 481 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 490 ARM64_FTR_END, 491 }; 492 493 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 496 ARM64_FTR_END, 497 }; 498 499 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 500 /* [31:28] TraceFilt */ 501 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 508 ARM64_FTR_END, 509 }; 510 511 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 512 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 513 ARM64_FTR_END, 514 }; 515 516 static const struct arm64_ftr_bits ftr_zcr[] = { 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 518 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 519 ARM64_FTR_END, 520 }; 521 522 /* 523 * Common ftr bits for a 32bit register with all hidden, strict 524 * attributes, with 4bit feature fields and a default safe value of 525 * 0. Covers the following 32bit registers: 526 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 527 */ 528 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 537 ARM64_FTR_END, 538 }; 539 540 /* Table for a single 32bit feature value */ 541 static const struct arm64_ftr_bits ftr_single32[] = { 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 543 ARM64_FTR_END, 544 }; 545 546 static const struct arm64_ftr_bits ftr_raz[] = { 547 ARM64_FTR_END, 548 }; 549 550 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) { \ 551 .sys_id = id, \ 552 .reg = &(struct arm64_ftr_reg){ \ 553 .name = #id, \ 554 .override = (ovr), \ 555 .ftr_bits = &((table)[0]), \ 556 }} 557 558 #define ARM64_FTR_REG(id, table) ARM64_FTR_REG_OVERRIDE(id, table, &no_override) 559 560 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 561 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 562 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 563 564 static const struct __ftr_reg_entry { 565 u32 sys_id; 566 struct arm64_ftr_reg *reg; 567 } arm64_ftr_regs[] = { 568 569 /* Op1 = 0, CRn = 0, CRm = 1 */ 570 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 571 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 572 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 573 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 574 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 575 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 576 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 577 578 /* Op1 = 0, CRn = 0, CRm = 2 */ 579 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 580 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 581 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 582 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 583 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 584 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 585 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 586 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 587 588 /* Op1 = 0, CRn = 0, CRm = 3 */ 589 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 590 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 591 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 592 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 593 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 594 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 595 596 /* Op1 = 0, CRn = 0, CRm = 4 */ 597 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 598 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 599 &id_aa64pfr1_override), 600 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 601 602 /* Op1 = 0, CRn = 0, CRm = 5 */ 603 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 604 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 605 606 /* Op1 = 0, CRn = 0, CRm = 6 */ 607 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 608 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 609 &id_aa64isar1_override), 610 611 /* Op1 = 0, CRn = 0, CRm = 7 */ 612 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 613 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 614 &id_aa64mmfr1_override), 615 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 616 617 /* Op1 = 0, CRn = 1, CRm = 2 */ 618 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 619 620 /* Op1 = 3, CRn = 0, CRm = 0 */ 621 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 622 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 623 624 /* Op1 = 3, CRn = 14, CRm = 0 */ 625 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 626 }; 627 628 static int search_cmp_ftr_reg(const void *id, const void *regp) 629 { 630 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 631 } 632 633 /* 634 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 635 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 636 * ascending order of sys_id, we use binary search to find a matching 637 * entry. 638 * 639 * returns - Upon success, matching ftr_reg entry for id. 640 * - NULL on failure. It is upto the caller to decide 641 * the impact of a failure. 642 */ 643 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 644 { 645 const struct __ftr_reg_entry *ret; 646 647 ret = bsearch((const void *)(unsigned long)sys_id, 648 arm64_ftr_regs, 649 ARRAY_SIZE(arm64_ftr_regs), 650 sizeof(arm64_ftr_regs[0]), 651 search_cmp_ftr_reg); 652 if (ret) 653 return ret->reg; 654 return NULL; 655 } 656 657 /* 658 * get_arm64_ftr_reg - Looks up a feature register entry using 659 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 660 * 661 * returns - Upon success, matching ftr_reg entry for id. 662 * - NULL on failure but with an WARN_ON(). 663 */ 664 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 665 { 666 struct arm64_ftr_reg *reg; 667 668 reg = get_arm64_ftr_reg_nowarn(sys_id); 669 670 /* 671 * Requesting a non-existent register search is an error. Warn 672 * and let the caller handle it. 673 */ 674 WARN_ON(!reg); 675 return reg; 676 } 677 678 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 679 s64 ftr_val) 680 { 681 u64 mask = arm64_ftr_mask(ftrp); 682 683 reg &= ~mask; 684 reg |= (ftr_val << ftrp->shift) & mask; 685 return reg; 686 } 687 688 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 689 s64 cur) 690 { 691 s64 ret = 0; 692 693 switch (ftrp->type) { 694 case FTR_EXACT: 695 ret = ftrp->safe_val; 696 break; 697 case FTR_LOWER_SAFE: 698 ret = new < cur ? new : cur; 699 break; 700 case FTR_HIGHER_OR_ZERO_SAFE: 701 if (!cur || !new) 702 break; 703 fallthrough; 704 case FTR_HIGHER_SAFE: 705 ret = new > cur ? new : cur; 706 break; 707 default: 708 BUG(); 709 } 710 711 return ret; 712 } 713 714 static void __init sort_ftr_regs(void) 715 { 716 unsigned int i; 717 718 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 719 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 720 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 721 unsigned int j = 0; 722 723 /* 724 * Features here must be sorted in descending order with respect 725 * to their shift values and should not overlap with each other. 726 */ 727 for (; ftr_bits->width != 0; ftr_bits++, j++) { 728 unsigned int width = ftr_reg->ftr_bits[j].width; 729 unsigned int shift = ftr_reg->ftr_bits[j].shift; 730 unsigned int prev_shift; 731 732 WARN((shift + width) > 64, 733 "%s has invalid feature at shift %d\n", 734 ftr_reg->name, shift); 735 736 /* 737 * Skip the first feature. There is nothing to 738 * compare against for now. 739 */ 740 if (j == 0) 741 continue; 742 743 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 744 WARN((shift + width) > prev_shift, 745 "%s has feature overlap at shift %d\n", 746 ftr_reg->name, shift); 747 } 748 749 /* 750 * Skip the first register. There is nothing to 751 * compare against for now. 752 */ 753 if (i == 0) 754 continue; 755 /* 756 * Registers here must be sorted in ascending order with respect 757 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 758 * to work correctly. 759 */ 760 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 761 } 762 } 763 764 /* 765 * Initialise the CPU feature register from Boot CPU values. 766 * Also initiliases the strict_mask for the register. 767 * Any bits that are not covered by an arm64_ftr_bits entry are considered 768 * RES0 for the system-wide value, and must strictly match. 769 */ 770 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 771 { 772 u64 val = 0; 773 u64 strict_mask = ~0x0ULL; 774 u64 user_mask = 0; 775 u64 valid_mask = 0; 776 777 const struct arm64_ftr_bits *ftrp; 778 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 779 780 if (!reg) 781 return; 782 783 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 784 u64 ftr_mask = arm64_ftr_mask(ftrp); 785 s64 ftr_new = arm64_ftr_value(ftrp, new); 786 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 787 788 if ((ftr_mask & reg->override->mask) == ftr_mask) { 789 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 790 char *str = NULL; 791 792 if (ftr_ovr != tmp) { 793 /* Unsafe, remove the override */ 794 reg->override->mask &= ~ftr_mask; 795 reg->override->val &= ~ftr_mask; 796 tmp = ftr_ovr; 797 str = "ignoring override"; 798 } else if (ftr_new != tmp) { 799 /* Override was valid */ 800 ftr_new = tmp; 801 str = "forced"; 802 } else if (ftr_ovr == tmp) { 803 /* Override was the safe value */ 804 str = "already set"; 805 } 806 807 if (str) 808 pr_warn("%s[%d:%d]: %s to %llx\n", 809 reg->name, 810 ftrp->shift + ftrp->width - 1, 811 ftrp->shift, str, tmp); 812 } 813 814 val = arm64_ftr_set_value(ftrp, val, ftr_new); 815 816 valid_mask |= ftr_mask; 817 if (!ftrp->strict) 818 strict_mask &= ~ftr_mask; 819 if (ftrp->visible) 820 user_mask |= ftr_mask; 821 else 822 reg->user_val = arm64_ftr_set_value(ftrp, 823 reg->user_val, 824 ftrp->safe_val); 825 } 826 827 val &= valid_mask; 828 829 reg->sys_val = val; 830 reg->strict_mask = strict_mask; 831 reg->user_mask = user_mask; 832 } 833 834 extern const struct arm64_cpu_capabilities arm64_errata[]; 835 static const struct arm64_cpu_capabilities arm64_features[]; 836 837 static void __init 838 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 839 { 840 for (; caps->matches; caps++) { 841 if (WARN(caps->capability >= ARM64_NCAPS, 842 "Invalid capability %d\n", caps->capability)) 843 continue; 844 if (WARN(cpu_hwcaps_ptrs[caps->capability], 845 "Duplicate entry for capability %d\n", 846 caps->capability)) 847 continue; 848 cpu_hwcaps_ptrs[caps->capability] = caps; 849 } 850 } 851 852 static void __init init_cpu_hwcaps_indirect_list(void) 853 { 854 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 855 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 856 } 857 858 static void __init setup_boot_cpu_capabilities(void); 859 860 void __init init_cpu_features(struct cpuinfo_arm64 *info) 861 { 862 /* Before we start using the tables, make sure it is sorted */ 863 sort_ftr_regs(); 864 865 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 866 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 867 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 868 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 869 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 870 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 871 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 872 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 873 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 874 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 875 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 876 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 877 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 878 879 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 880 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 881 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 882 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 883 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 884 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 885 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 886 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 887 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 888 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 889 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 890 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 891 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 892 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 893 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 894 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 895 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 896 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 897 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 898 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 899 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 900 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 901 } 902 903 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 904 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 905 sve_init_vq_map(); 906 } 907 908 /* 909 * Initialize the indirect array of CPU hwcaps capabilities pointers 910 * before we handle the boot CPU below. 911 */ 912 init_cpu_hwcaps_indirect_list(); 913 914 /* 915 * Detect and enable early CPU capabilities based on the boot CPU, 916 * after we have initialised the CPU feature infrastructure. 917 */ 918 setup_boot_cpu_capabilities(); 919 } 920 921 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 922 { 923 const struct arm64_ftr_bits *ftrp; 924 925 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 926 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 927 s64 ftr_new = arm64_ftr_value(ftrp, new); 928 929 if (ftr_cur == ftr_new) 930 continue; 931 /* Find a safe value */ 932 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 933 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 934 } 935 936 } 937 938 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 939 { 940 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 941 942 if (!regp) 943 return 0; 944 945 update_cpu_ftr_reg(regp, val); 946 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 947 return 0; 948 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 949 regp->name, boot, cpu, val); 950 return 1; 951 } 952 953 static void relax_cpu_ftr_reg(u32 sys_id, int field) 954 { 955 const struct arm64_ftr_bits *ftrp; 956 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 957 958 if (!regp) 959 return; 960 961 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 962 if (ftrp->shift == field) { 963 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 964 break; 965 } 966 } 967 968 /* Bogus field? */ 969 WARN_ON(!ftrp->width); 970 } 971 972 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info, 973 struct cpuinfo_arm64 *boot) 974 { 975 int taint = 0; 976 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 977 978 /* 979 * If we don't have AArch32 at all then skip the checks entirely 980 * as the register values may be UNKNOWN and we're not going to be 981 * using them for anything. 982 */ 983 if (!id_aa64pfr0_32bit_el0(pfr0)) 984 return taint; 985 986 /* 987 * If we don't have AArch32 at EL1, then relax the strictness of 988 * EL1-dependent register fields to avoid spurious sanity check fails. 989 */ 990 if (!id_aa64pfr0_32bit_el1(pfr0)) { 991 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 992 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 993 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 994 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 995 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 996 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 997 } 998 999 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1000 info->reg_id_dfr0, boot->reg_id_dfr0); 1001 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1002 info->reg_id_dfr1, boot->reg_id_dfr1); 1003 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1004 info->reg_id_isar0, boot->reg_id_isar0); 1005 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1006 info->reg_id_isar1, boot->reg_id_isar1); 1007 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1008 info->reg_id_isar2, boot->reg_id_isar2); 1009 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1010 info->reg_id_isar3, boot->reg_id_isar3); 1011 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1012 info->reg_id_isar4, boot->reg_id_isar4); 1013 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1014 info->reg_id_isar5, boot->reg_id_isar5); 1015 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1016 info->reg_id_isar6, boot->reg_id_isar6); 1017 1018 /* 1019 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1020 * ACTLR formats could differ across CPUs and therefore would have to 1021 * be trapped for virtualization anyway. 1022 */ 1023 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1024 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1025 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1026 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1027 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1028 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1029 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1030 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1031 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1032 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1033 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1034 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1035 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1036 info->reg_id_pfr0, boot->reg_id_pfr0); 1037 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1038 info->reg_id_pfr1, boot->reg_id_pfr1); 1039 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1040 info->reg_id_pfr2, boot->reg_id_pfr2); 1041 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1042 info->reg_mvfr0, boot->reg_mvfr0); 1043 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1044 info->reg_mvfr1, boot->reg_mvfr1); 1045 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1046 info->reg_mvfr2, boot->reg_mvfr2); 1047 1048 return taint; 1049 } 1050 1051 /* 1052 * Update system wide CPU feature registers with the values from a 1053 * non-boot CPU. Also performs SANITY checks to make sure that there 1054 * aren't any insane variations from that of the boot CPU. 1055 */ 1056 void update_cpu_features(int cpu, 1057 struct cpuinfo_arm64 *info, 1058 struct cpuinfo_arm64 *boot) 1059 { 1060 int taint = 0; 1061 1062 /* 1063 * The kernel can handle differing I-cache policies, but otherwise 1064 * caches should look identical. Userspace JITs will make use of 1065 * *minLine. 1066 */ 1067 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1068 info->reg_ctr, boot->reg_ctr); 1069 1070 /* 1071 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1072 * could result in too much or too little memory being zeroed if a 1073 * process is preempted and migrated between CPUs. 1074 */ 1075 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1076 info->reg_dczid, boot->reg_dczid); 1077 1078 /* If different, timekeeping will be broken (especially with KVM) */ 1079 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1080 info->reg_cntfrq, boot->reg_cntfrq); 1081 1082 /* 1083 * The kernel uses self-hosted debug features and expects CPUs to 1084 * support identical debug features. We presently need CTX_CMPs, WRPs, 1085 * and BRPs to be identical. 1086 * ID_AA64DFR1 is currently RES0. 1087 */ 1088 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1089 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1090 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1091 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1092 /* 1093 * Even in big.LITTLE, processors should be identical instruction-set 1094 * wise. 1095 */ 1096 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1097 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1098 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1099 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1100 1101 /* 1102 * Differing PARange support is fine as long as all peripherals and 1103 * memory are mapped within the minimum PARange of all CPUs. 1104 * Linux should not care about secure memory. 1105 */ 1106 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1107 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1108 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1109 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1110 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1111 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1112 1113 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1114 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1115 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1116 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1117 1118 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1119 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1120 1121 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 1122 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1123 info->reg_zcr, boot->reg_zcr); 1124 1125 /* Probe vector lengths, unless we already gave up on SVE */ 1126 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 1127 !system_capabilities_finalized()) 1128 sve_update_vq_map(); 1129 } 1130 1131 /* 1132 * This relies on a sanitised view of the AArch64 ID registers 1133 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1134 */ 1135 taint |= update_32bit_cpu_features(cpu, info, boot); 1136 1137 /* 1138 * Mismatched CPU features are a recipe for disaster. Don't even 1139 * pretend to support them. 1140 */ 1141 if (taint) { 1142 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1143 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1144 } 1145 } 1146 1147 u64 read_sanitised_ftr_reg(u32 id) 1148 { 1149 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1150 1151 if (!regp) 1152 return 0; 1153 return regp->sys_val; 1154 } 1155 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1156 1157 #define read_sysreg_case(r) \ 1158 case r: val = read_sysreg_s(r); break; 1159 1160 /* 1161 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1162 * Read the system register on the current CPU 1163 */ 1164 u64 __read_sysreg_by_encoding(u32 sys_id) 1165 { 1166 struct arm64_ftr_reg *regp; 1167 u64 val; 1168 1169 switch (sys_id) { 1170 read_sysreg_case(SYS_ID_PFR0_EL1); 1171 read_sysreg_case(SYS_ID_PFR1_EL1); 1172 read_sysreg_case(SYS_ID_PFR2_EL1); 1173 read_sysreg_case(SYS_ID_DFR0_EL1); 1174 read_sysreg_case(SYS_ID_DFR1_EL1); 1175 read_sysreg_case(SYS_ID_MMFR0_EL1); 1176 read_sysreg_case(SYS_ID_MMFR1_EL1); 1177 read_sysreg_case(SYS_ID_MMFR2_EL1); 1178 read_sysreg_case(SYS_ID_MMFR3_EL1); 1179 read_sysreg_case(SYS_ID_MMFR4_EL1); 1180 read_sysreg_case(SYS_ID_MMFR5_EL1); 1181 read_sysreg_case(SYS_ID_ISAR0_EL1); 1182 read_sysreg_case(SYS_ID_ISAR1_EL1); 1183 read_sysreg_case(SYS_ID_ISAR2_EL1); 1184 read_sysreg_case(SYS_ID_ISAR3_EL1); 1185 read_sysreg_case(SYS_ID_ISAR4_EL1); 1186 read_sysreg_case(SYS_ID_ISAR5_EL1); 1187 read_sysreg_case(SYS_ID_ISAR6_EL1); 1188 read_sysreg_case(SYS_MVFR0_EL1); 1189 read_sysreg_case(SYS_MVFR1_EL1); 1190 read_sysreg_case(SYS_MVFR2_EL1); 1191 1192 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1193 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1194 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1195 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1196 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1197 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1198 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1199 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1200 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1201 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1202 1203 read_sysreg_case(SYS_CNTFRQ_EL0); 1204 read_sysreg_case(SYS_CTR_EL0); 1205 read_sysreg_case(SYS_DCZID_EL0); 1206 1207 default: 1208 BUG(); 1209 return 0; 1210 } 1211 1212 regp = get_arm64_ftr_reg(sys_id); 1213 if (regp) { 1214 val &= ~regp->override->mask; 1215 val |= (regp->override->val & regp->override->mask); 1216 } 1217 1218 return val; 1219 } 1220 1221 #include <linux/irqchip/arm-gic-v3.h> 1222 1223 static bool 1224 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1225 { 1226 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 1227 1228 return val >= entry->min_field_value; 1229 } 1230 1231 static bool 1232 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1233 { 1234 u64 val; 1235 1236 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1237 if (scope == SCOPE_SYSTEM) 1238 val = read_sanitised_ftr_reg(entry->sys_reg); 1239 else 1240 val = __read_sysreg_by_encoding(entry->sys_reg); 1241 1242 return feature_matches(val, entry); 1243 } 1244 1245 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1246 { 1247 bool has_sre; 1248 1249 if (!has_cpuid_feature(entry, scope)) 1250 return false; 1251 1252 has_sre = gic_enable_sre(); 1253 if (!has_sre) 1254 pr_warn_once("%s present but disabled by higher exception level\n", 1255 entry->desc); 1256 1257 return has_sre; 1258 } 1259 1260 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1261 { 1262 u32 midr = read_cpuid_id(); 1263 1264 /* Cavium ThunderX pass 1.x and 2.x */ 1265 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1266 MIDR_CPU_VAR_REV(0, 0), 1267 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1268 } 1269 1270 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1271 { 1272 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1273 1274 return cpuid_feature_extract_signed_field(pfr0, 1275 ID_AA64PFR0_FP_SHIFT) < 0; 1276 } 1277 1278 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1279 int scope) 1280 { 1281 u64 ctr; 1282 1283 if (scope == SCOPE_SYSTEM) 1284 ctr = arm64_ftr_reg_ctrel0.sys_val; 1285 else 1286 ctr = read_cpuid_effective_cachetype(); 1287 1288 return ctr & BIT(CTR_IDC_SHIFT); 1289 } 1290 1291 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1292 { 1293 /* 1294 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1295 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1296 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1297 * value. 1298 */ 1299 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 1300 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1301 } 1302 1303 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1304 int scope) 1305 { 1306 u64 ctr; 1307 1308 if (scope == SCOPE_SYSTEM) 1309 ctr = arm64_ftr_reg_ctrel0.sys_val; 1310 else 1311 ctr = read_cpuid_cachetype(); 1312 1313 return ctr & BIT(CTR_DIC_SHIFT); 1314 } 1315 1316 static bool __maybe_unused 1317 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1318 { 1319 /* 1320 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1321 * may share TLB entries with a CPU stuck in the crashed 1322 * kernel. 1323 */ 1324 if (is_kdump_kernel()) 1325 return false; 1326 1327 return has_cpuid_feature(entry, scope); 1328 } 1329 1330 /* 1331 * This check is triggered during the early boot before the cpufeature 1332 * is initialised. Checking the status on the local CPU allows the boot 1333 * CPU to detect the need for non-global mappings and thus avoiding a 1334 * pagetable re-write after all the CPUs are booted. This check will be 1335 * anyway run on individual CPUs, allowing us to get the consistent 1336 * state once the SMP CPUs are up and thus make the switch to non-global 1337 * mappings if required. 1338 */ 1339 bool kaslr_requires_kpti(void) 1340 { 1341 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1342 return false; 1343 1344 /* 1345 * E0PD does a similar job to KPTI so can be used instead 1346 * where available. 1347 */ 1348 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1349 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1350 if (cpuid_feature_extract_unsigned_field(mmfr2, 1351 ID_AA64MMFR2_E0PD_SHIFT)) 1352 return false; 1353 } 1354 1355 /* 1356 * Systems affected by Cavium erratum 24756 are incompatible 1357 * with KPTI. 1358 */ 1359 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1360 extern const struct midr_range cavium_erratum_27456_cpus[]; 1361 1362 if (is_midr_in_range_list(read_cpuid_id(), 1363 cavium_erratum_27456_cpus)) 1364 return false; 1365 } 1366 1367 return kaslr_offset() > 0; 1368 } 1369 1370 static bool __meltdown_safe = true; 1371 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1372 1373 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1374 int scope) 1375 { 1376 /* List of CPUs that are not vulnerable and don't need KPTI */ 1377 static const struct midr_range kpti_safe_list[] = { 1378 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1379 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1380 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1381 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1382 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1383 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1384 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1385 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1386 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1387 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1388 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1389 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1390 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1391 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1392 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1393 { /* sentinel */ } 1394 }; 1395 char const *str = "kpti command line option"; 1396 bool meltdown_safe; 1397 1398 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1399 1400 /* Defer to CPU feature registers */ 1401 if (has_cpuid_feature(entry, scope)) 1402 meltdown_safe = true; 1403 1404 if (!meltdown_safe) 1405 __meltdown_safe = false; 1406 1407 /* 1408 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1409 * ThunderX leads to apparent I-cache corruption of kernel text, which 1410 * ends as well as you might imagine. Don't even try. 1411 */ 1412 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1413 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1414 __kpti_forced = -1; 1415 } 1416 1417 /* Useful for KASLR robustness */ 1418 if (kaslr_requires_kpti()) { 1419 if (!__kpti_forced) { 1420 str = "KASLR"; 1421 __kpti_forced = 1; 1422 } 1423 } 1424 1425 if (cpu_mitigations_off() && !__kpti_forced) { 1426 str = "mitigations=off"; 1427 __kpti_forced = -1; 1428 } 1429 1430 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1431 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1432 return false; 1433 } 1434 1435 /* Forced? */ 1436 if (__kpti_forced) { 1437 pr_info_once("kernel page table isolation forced %s by %s\n", 1438 __kpti_forced > 0 ? "ON" : "OFF", str); 1439 return __kpti_forced > 0; 1440 } 1441 1442 return !meltdown_safe; 1443 } 1444 1445 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1446 static void 1447 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1448 { 1449 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1450 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1451 kpti_remap_fn *remap_fn; 1452 1453 int cpu = smp_processor_id(); 1454 1455 /* 1456 * We don't need to rewrite the page-tables if either we've done 1457 * it already or we have KASLR enabled and therefore have not 1458 * created any global mappings at all. 1459 */ 1460 if (arm64_use_ng_mappings) 1461 return; 1462 1463 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1464 1465 cpu_install_idmap(); 1466 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1467 cpu_uninstall_idmap(); 1468 1469 if (!cpu) 1470 arm64_use_ng_mappings = true; 1471 1472 return; 1473 } 1474 #else 1475 static void 1476 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1477 { 1478 } 1479 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1480 1481 static int __init parse_kpti(char *str) 1482 { 1483 bool enabled; 1484 int ret = strtobool(str, &enabled); 1485 1486 if (ret) 1487 return ret; 1488 1489 __kpti_forced = enabled ? 1 : -1; 1490 return 0; 1491 } 1492 early_param("kpti", parse_kpti); 1493 1494 #ifdef CONFIG_ARM64_HW_AFDBM 1495 static inline void __cpu_enable_hw_dbm(void) 1496 { 1497 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1498 1499 write_sysreg(tcr, tcr_el1); 1500 isb(); 1501 local_flush_tlb_all(); 1502 } 1503 1504 static bool cpu_has_broken_dbm(void) 1505 { 1506 /* List of CPUs which have broken DBM support. */ 1507 static const struct midr_range cpus[] = { 1508 #ifdef CONFIG_ARM64_ERRATUM_1024718 1509 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1510 /* Kryo4xx Silver (rdpe => r1p0) */ 1511 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1512 #endif 1513 {}, 1514 }; 1515 1516 return is_midr_in_range_list(read_cpuid_id(), cpus); 1517 } 1518 1519 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1520 { 1521 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1522 !cpu_has_broken_dbm(); 1523 } 1524 1525 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1526 { 1527 if (cpu_can_use_dbm(cap)) 1528 __cpu_enable_hw_dbm(); 1529 } 1530 1531 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1532 int __unused) 1533 { 1534 static bool detected = false; 1535 /* 1536 * DBM is a non-conflicting feature. i.e, the kernel can safely 1537 * run a mix of CPUs with and without the feature. So, we 1538 * unconditionally enable the capability to allow any late CPU 1539 * to use the feature. We only enable the control bits on the 1540 * CPU, if it actually supports. 1541 * 1542 * We have to make sure we print the "feature" detection only 1543 * when at least one CPU actually uses it. So check if this CPU 1544 * can actually use it and print the message exactly once. 1545 * 1546 * This is safe as all CPUs (including secondary CPUs - due to the 1547 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1548 * goes through the "matches" check exactly once. Also if a CPU 1549 * matches the criteria, it is guaranteed that the CPU will turn 1550 * the DBM on, as the capability is unconditionally enabled. 1551 */ 1552 if (!detected && cpu_can_use_dbm(cap)) { 1553 detected = true; 1554 pr_info("detected: Hardware dirty bit management\n"); 1555 } 1556 1557 return true; 1558 } 1559 1560 #endif 1561 1562 #ifdef CONFIG_ARM64_AMU_EXTN 1563 1564 /* 1565 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1566 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1567 * information regarding all the events that it supports. When a CPU bit is 1568 * set in the cpumask, the user of this feature can only rely on the presence 1569 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1570 * counters are enabled or access to these counters is enabled by code 1571 * executed at higher exception levels (firmware). 1572 */ 1573 static struct cpumask amu_cpus __read_mostly; 1574 1575 bool cpu_has_amu_feat(int cpu) 1576 { 1577 return cpumask_test_cpu(cpu, &amu_cpus); 1578 } 1579 1580 int get_cpu_with_amu_feat(void) 1581 { 1582 return cpumask_any(&amu_cpus); 1583 } 1584 1585 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1586 { 1587 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1588 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1589 smp_processor_id()); 1590 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1591 update_freq_counters_refs(); 1592 } 1593 } 1594 1595 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1596 int __unused) 1597 { 1598 /* 1599 * The AMU extension is a non-conflicting feature: the kernel can 1600 * safely run a mix of CPUs with and without support for the 1601 * activity monitors extension. Therefore, unconditionally enable 1602 * the capability to allow any late CPU to use the feature. 1603 * 1604 * With this feature unconditionally enabled, the cpu_enable 1605 * function will be called for all CPUs that match the criteria, 1606 * including secondary and hotplugged, marking this feature as 1607 * present on that respective CPU. The enable function will also 1608 * print a detection message. 1609 */ 1610 1611 return true; 1612 } 1613 #else 1614 int get_cpu_with_amu_feat(void) 1615 { 1616 return nr_cpu_ids; 1617 } 1618 #endif 1619 1620 #ifdef CONFIG_ARM64_VHE 1621 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1622 { 1623 return is_kernel_in_hyp_mode(); 1624 } 1625 1626 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1627 { 1628 /* 1629 * Copy register values that aren't redirected by hardware. 1630 * 1631 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1632 * this value to tpidr_el2 before we patch the code. Once we've done 1633 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1634 * do anything here. 1635 */ 1636 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1637 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1638 } 1639 #endif 1640 1641 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1642 { 1643 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1644 1645 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1646 WARN_ON(val & (7 << 27 | 7 << 21)); 1647 } 1648 1649 #ifdef CONFIG_ARM64_PAN 1650 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1651 { 1652 /* 1653 * We modify PSTATE. This won't work from irq context as the PSTATE 1654 * is discarded once we return from the exception. 1655 */ 1656 WARN_ON_ONCE(in_interrupt()); 1657 1658 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1659 set_pstate_pan(1); 1660 } 1661 #endif /* CONFIG_ARM64_PAN */ 1662 1663 #ifdef CONFIG_ARM64_RAS_EXTN 1664 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1665 { 1666 /* Firmware may have left a deferred SError in this register. */ 1667 write_sysreg_s(0, SYS_DISR_EL1); 1668 } 1669 #endif /* CONFIG_ARM64_RAS_EXTN */ 1670 1671 #ifdef CONFIG_ARM64_PTR_AUTH 1672 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1673 { 1674 int boot_val, sec_val; 1675 1676 /* We don't expect to be called with SCOPE_SYSTEM */ 1677 WARN_ON(scope == SCOPE_SYSTEM); 1678 /* 1679 * The ptr-auth feature levels are not intercompatible with lower 1680 * levels. Hence we must match ptr-auth feature level of the secondary 1681 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1682 * from the sanitised register whereas direct register read is done for 1683 * the secondary CPUs. 1684 * The sanitised feature state is guaranteed to match that of the 1685 * boot CPU as a mismatched secondary CPU is parked before it gets 1686 * a chance to update the state, with the capability. 1687 */ 1688 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1689 entry->field_pos, entry->sign); 1690 if (scope & SCOPE_BOOT_CPU) 1691 return boot_val >= entry->min_field_value; 1692 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 1693 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 1694 entry->field_pos, entry->sign); 1695 return sec_val == boot_val; 1696 } 1697 1698 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 1699 int scope) 1700 { 1701 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) || 1702 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 1703 } 1704 1705 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1706 int __unused) 1707 { 1708 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) || 1709 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1710 } 1711 #endif /* CONFIG_ARM64_PTR_AUTH */ 1712 1713 #ifdef CONFIG_ARM64_E0PD 1714 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1715 { 1716 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1717 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1718 } 1719 #endif /* CONFIG_ARM64_E0PD */ 1720 1721 #ifdef CONFIG_ARM64_PSEUDO_NMI 1722 static bool enable_pseudo_nmi; 1723 1724 static int __init early_enable_pseudo_nmi(char *p) 1725 { 1726 return strtobool(p, &enable_pseudo_nmi); 1727 } 1728 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1729 1730 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1731 int scope) 1732 { 1733 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1734 } 1735 #endif 1736 1737 #ifdef CONFIG_ARM64_BTI 1738 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 1739 { 1740 /* 1741 * Use of X16/X17 for tail-calls and trampolines that jump to 1742 * function entry points using BR is a requirement for 1743 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 1744 * So, be strict and forbid other BRs using other registers to 1745 * jump onto a PACIxSP instruction: 1746 */ 1747 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 1748 isb(); 1749 } 1750 #endif /* CONFIG_ARM64_BTI */ 1751 1752 #ifdef CONFIG_ARM64_MTE 1753 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 1754 { 1755 /* 1756 * Clear the tags in the zero page. This needs to be done via the 1757 * linear map which has the Tagged attribute. 1758 */ 1759 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) 1760 mte_clear_page_tags(lm_alias(empty_zero_page)); 1761 1762 kasan_init_hw_tags_cpu(); 1763 } 1764 #endif /* CONFIG_ARM64_MTE */ 1765 1766 #ifdef CONFIG_KVM 1767 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 1768 { 1769 if (kvm_get_mode() != KVM_MODE_PROTECTED) 1770 return false; 1771 1772 if (is_kernel_in_hyp_mode()) { 1773 pr_warn("Protected KVM not available with VHE\n"); 1774 return false; 1775 } 1776 1777 return true; 1778 } 1779 #endif /* CONFIG_KVM */ 1780 1781 /* Internal helper functions to match cpu capability type */ 1782 static bool 1783 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1784 { 1785 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1786 } 1787 1788 static bool 1789 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1790 { 1791 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1792 } 1793 1794 static bool 1795 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 1796 { 1797 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 1798 } 1799 1800 static const struct arm64_cpu_capabilities arm64_features[] = { 1801 { 1802 .desc = "GIC system register CPU interface", 1803 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1804 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1805 .matches = has_useable_gicv3_cpuif, 1806 .sys_reg = SYS_ID_AA64PFR0_EL1, 1807 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1808 .sign = FTR_UNSIGNED, 1809 .min_field_value = 1, 1810 }, 1811 #ifdef CONFIG_ARM64_PAN 1812 { 1813 .desc = "Privileged Access Never", 1814 .capability = ARM64_HAS_PAN, 1815 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1816 .matches = has_cpuid_feature, 1817 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1818 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1819 .sign = FTR_UNSIGNED, 1820 .min_field_value = 1, 1821 .cpu_enable = cpu_enable_pan, 1822 }, 1823 #endif /* CONFIG_ARM64_PAN */ 1824 #ifdef CONFIG_ARM64_LSE_ATOMICS 1825 { 1826 .desc = "LSE atomic instructions", 1827 .capability = ARM64_HAS_LSE_ATOMICS, 1828 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1829 .matches = has_cpuid_feature, 1830 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1831 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1832 .sign = FTR_UNSIGNED, 1833 .min_field_value = 2, 1834 }, 1835 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 1836 { 1837 .desc = "Software prefetching using PRFM", 1838 .capability = ARM64_HAS_NO_HW_PREFETCH, 1839 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1840 .matches = has_no_hw_prefetch, 1841 }, 1842 #ifdef CONFIG_ARM64_VHE 1843 { 1844 .desc = "Virtualization Host Extensions", 1845 .capability = ARM64_HAS_VIRT_HOST_EXTN, 1846 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1847 .matches = runs_at_el2, 1848 .cpu_enable = cpu_copy_el2regs, 1849 }, 1850 #endif /* CONFIG_ARM64_VHE */ 1851 { 1852 .desc = "32-bit EL0 Support", 1853 .capability = ARM64_HAS_32BIT_EL0, 1854 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1855 .matches = has_cpuid_feature, 1856 .sys_reg = SYS_ID_AA64PFR0_EL1, 1857 .sign = FTR_UNSIGNED, 1858 .field_pos = ID_AA64PFR0_EL0_SHIFT, 1859 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 1860 }, 1861 #ifdef CONFIG_KVM 1862 { 1863 .desc = "32-bit EL1 Support", 1864 .capability = ARM64_HAS_32BIT_EL1, 1865 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1866 .matches = has_cpuid_feature, 1867 .sys_reg = SYS_ID_AA64PFR0_EL1, 1868 .sign = FTR_UNSIGNED, 1869 .field_pos = ID_AA64PFR0_EL1_SHIFT, 1870 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT, 1871 }, 1872 { 1873 .desc = "Protected KVM", 1874 .capability = ARM64_KVM_PROTECTED_MODE, 1875 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1876 .matches = is_kvm_protected_mode, 1877 }, 1878 #endif 1879 { 1880 .desc = "Kernel page table isolation (KPTI)", 1881 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 1882 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1883 /* 1884 * The ID feature fields below are used to indicate that 1885 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 1886 * more details. 1887 */ 1888 .sys_reg = SYS_ID_AA64PFR0_EL1, 1889 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 1890 .min_field_value = 1, 1891 .matches = unmap_kernel_at_el0, 1892 .cpu_enable = kpti_install_ng_mappings, 1893 }, 1894 { 1895 /* FP/SIMD is not implemented */ 1896 .capability = ARM64_HAS_NO_FPSIMD, 1897 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1898 .min_field_value = 0, 1899 .matches = has_no_fpsimd, 1900 }, 1901 #ifdef CONFIG_ARM64_PMEM 1902 { 1903 .desc = "Data cache clean to Point of Persistence", 1904 .capability = ARM64_HAS_DCPOP, 1905 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1906 .matches = has_cpuid_feature, 1907 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1908 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1909 .min_field_value = 1, 1910 }, 1911 { 1912 .desc = "Data cache clean to Point of Deep Persistence", 1913 .capability = ARM64_HAS_DCPODP, 1914 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1915 .matches = has_cpuid_feature, 1916 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1917 .sign = FTR_UNSIGNED, 1918 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1919 .min_field_value = 2, 1920 }, 1921 #endif 1922 #ifdef CONFIG_ARM64_SVE 1923 { 1924 .desc = "Scalable Vector Extension", 1925 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1926 .capability = ARM64_SVE, 1927 .sys_reg = SYS_ID_AA64PFR0_EL1, 1928 .sign = FTR_UNSIGNED, 1929 .field_pos = ID_AA64PFR0_SVE_SHIFT, 1930 .min_field_value = ID_AA64PFR0_SVE, 1931 .matches = has_cpuid_feature, 1932 .cpu_enable = sve_kernel_enable, 1933 }, 1934 #endif /* CONFIG_ARM64_SVE */ 1935 #ifdef CONFIG_ARM64_RAS_EXTN 1936 { 1937 .desc = "RAS Extension Support", 1938 .capability = ARM64_HAS_RAS_EXTN, 1939 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1940 .matches = has_cpuid_feature, 1941 .sys_reg = SYS_ID_AA64PFR0_EL1, 1942 .sign = FTR_UNSIGNED, 1943 .field_pos = ID_AA64PFR0_RAS_SHIFT, 1944 .min_field_value = ID_AA64PFR0_RAS_V1, 1945 .cpu_enable = cpu_clear_disr, 1946 }, 1947 #endif /* CONFIG_ARM64_RAS_EXTN */ 1948 #ifdef CONFIG_ARM64_AMU_EXTN 1949 { 1950 /* 1951 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 1952 * Therefore, don't provide .desc as we don't want the detection 1953 * message to be shown until at least one CPU is detected to 1954 * support the feature. 1955 */ 1956 .capability = ARM64_HAS_AMU_EXTN, 1957 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1958 .matches = has_amu, 1959 .sys_reg = SYS_ID_AA64PFR0_EL1, 1960 .sign = FTR_UNSIGNED, 1961 .field_pos = ID_AA64PFR0_AMU_SHIFT, 1962 .min_field_value = ID_AA64PFR0_AMU, 1963 .cpu_enable = cpu_amu_enable, 1964 }, 1965 #endif /* CONFIG_ARM64_AMU_EXTN */ 1966 { 1967 .desc = "Data cache clean to the PoU not required for I/D coherence", 1968 .capability = ARM64_HAS_CACHE_IDC, 1969 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1970 .matches = has_cache_idc, 1971 .cpu_enable = cpu_emulate_effective_ctr, 1972 }, 1973 { 1974 .desc = "Instruction cache invalidation not required for I/D coherence", 1975 .capability = ARM64_HAS_CACHE_DIC, 1976 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1977 .matches = has_cache_dic, 1978 }, 1979 { 1980 .desc = "Stage-2 Force Write-Back", 1981 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1982 .capability = ARM64_HAS_STAGE2_FWB, 1983 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1984 .sign = FTR_UNSIGNED, 1985 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 1986 .min_field_value = 1, 1987 .matches = has_cpuid_feature, 1988 .cpu_enable = cpu_has_fwb, 1989 }, 1990 { 1991 .desc = "ARMv8.4 Translation Table Level", 1992 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1993 .capability = ARM64_HAS_ARMv8_4_TTL, 1994 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1995 .sign = FTR_UNSIGNED, 1996 .field_pos = ID_AA64MMFR2_TTL_SHIFT, 1997 .min_field_value = 1, 1998 .matches = has_cpuid_feature, 1999 }, 2000 { 2001 .desc = "TLB range maintenance instructions", 2002 .capability = ARM64_HAS_TLB_RANGE, 2003 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2004 .matches = has_cpuid_feature, 2005 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2006 .field_pos = ID_AA64ISAR0_TLB_SHIFT, 2007 .sign = FTR_UNSIGNED, 2008 .min_field_value = ID_AA64ISAR0_TLB_RANGE, 2009 }, 2010 #ifdef CONFIG_ARM64_HW_AFDBM 2011 { 2012 /* 2013 * Since we turn this on always, we don't want the user to 2014 * think that the feature is available when it may not be. 2015 * So hide the description. 2016 * 2017 * .desc = "Hardware pagetable Dirty Bit Management", 2018 * 2019 */ 2020 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2021 .capability = ARM64_HW_DBM, 2022 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2023 .sign = FTR_UNSIGNED, 2024 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 2025 .min_field_value = 2, 2026 .matches = has_hw_dbm, 2027 .cpu_enable = cpu_enable_hw_dbm, 2028 }, 2029 #endif 2030 { 2031 .desc = "CRC32 instructions", 2032 .capability = ARM64_HAS_CRC32, 2033 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2034 .matches = has_cpuid_feature, 2035 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2036 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 2037 .min_field_value = 1, 2038 }, 2039 { 2040 .desc = "Speculative Store Bypassing Safe (SSBS)", 2041 .capability = ARM64_SSBS, 2042 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2043 .matches = has_cpuid_feature, 2044 .sys_reg = SYS_ID_AA64PFR1_EL1, 2045 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 2046 .sign = FTR_UNSIGNED, 2047 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 2048 }, 2049 #ifdef CONFIG_ARM64_CNP 2050 { 2051 .desc = "Common not Private translations", 2052 .capability = ARM64_HAS_CNP, 2053 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2054 .matches = has_useable_cnp, 2055 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2056 .sign = FTR_UNSIGNED, 2057 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 2058 .min_field_value = 1, 2059 .cpu_enable = cpu_enable_cnp, 2060 }, 2061 #endif 2062 { 2063 .desc = "Speculation barrier (SB)", 2064 .capability = ARM64_HAS_SB, 2065 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2066 .matches = has_cpuid_feature, 2067 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2068 .field_pos = ID_AA64ISAR1_SB_SHIFT, 2069 .sign = FTR_UNSIGNED, 2070 .min_field_value = 1, 2071 }, 2072 #ifdef CONFIG_ARM64_PTR_AUTH 2073 { 2074 .desc = "Address authentication (architected algorithm)", 2075 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 2076 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2077 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2078 .sign = FTR_UNSIGNED, 2079 .field_pos = ID_AA64ISAR1_APA_SHIFT, 2080 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 2081 .matches = has_address_auth_cpucap, 2082 }, 2083 { 2084 .desc = "Address authentication (IMP DEF algorithm)", 2085 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2086 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2087 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2088 .sign = FTR_UNSIGNED, 2089 .field_pos = ID_AA64ISAR1_API_SHIFT, 2090 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 2091 .matches = has_address_auth_cpucap, 2092 }, 2093 { 2094 .capability = ARM64_HAS_ADDRESS_AUTH, 2095 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2096 .matches = has_address_auth_metacap, 2097 }, 2098 { 2099 .desc = "Generic authentication (architected algorithm)", 2100 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 2101 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2102 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2103 .sign = FTR_UNSIGNED, 2104 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 2105 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 2106 .matches = has_cpuid_feature, 2107 }, 2108 { 2109 .desc = "Generic authentication (IMP DEF algorithm)", 2110 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2111 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2112 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2113 .sign = FTR_UNSIGNED, 2114 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 2115 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 2116 .matches = has_cpuid_feature, 2117 }, 2118 { 2119 .capability = ARM64_HAS_GENERIC_AUTH, 2120 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2121 .matches = has_generic_auth, 2122 }, 2123 #endif /* CONFIG_ARM64_PTR_AUTH */ 2124 #ifdef CONFIG_ARM64_PSEUDO_NMI 2125 { 2126 /* 2127 * Depends on having GICv3 2128 */ 2129 .desc = "IRQ priority masking", 2130 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2131 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2132 .matches = can_use_gic_priorities, 2133 .sys_reg = SYS_ID_AA64PFR0_EL1, 2134 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2135 .sign = FTR_UNSIGNED, 2136 .min_field_value = 1, 2137 }, 2138 #endif 2139 #ifdef CONFIG_ARM64_E0PD 2140 { 2141 .desc = "E0PD", 2142 .capability = ARM64_HAS_E0PD, 2143 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2144 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2145 .sign = FTR_UNSIGNED, 2146 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2147 .matches = has_cpuid_feature, 2148 .min_field_value = 1, 2149 .cpu_enable = cpu_enable_e0pd, 2150 }, 2151 #endif 2152 #ifdef CONFIG_ARCH_RANDOM 2153 { 2154 .desc = "Random Number Generator", 2155 .capability = ARM64_HAS_RNG, 2156 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2157 .matches = has_cpuid_feature, 2158 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2159 .field_pos = ID_AA64ISAR0_RNDR_SHIFT, 2160 .sign = FTR_UNSIGNED, 2161 .min_field_value = 1, 2162 }, 2163 #endif 2164 #ifdef CONFIG_ARM64_BTI 2165 { 2166 .desc = "Branch Target Identification", 2167 .capability = ARM64_BTI, 2168 #ifdef CONFIG_ARM64_BTI_KERNEL 2169 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2170 #else 2171 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2172 #endif 2173 .matches = has_cpuid_feature, 2174 .cpu_enable = bti_enable, 2175 .sys_reg = SYS_ID_AA64PFR1_EL1, 2176 .field_pos = ID_AA64PFR1_BT_SHIFT, 2177 .min_field_value = ID_AA64PFR1_BT_BTI, 2178 .sign = FTR_UNSIGNED, 2179 }, 2180 #endif 2181 #ifdef CONFIG_ARM64_MTE 2182 { 2183 .desc = "Memory Tagging Extension", 2184 .capability = ARM64_MTE, 2185 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2186 .matches = has_cpuid_feature, 2187 .sys_reg = SYS_ID_AA64PFR1_EL1, 2188 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2189 .min_field_value = ID_AA64PFR1_MTE, 2190 .sign = FTR_UNSIGNED, 2191 .cpu_enable = cpu_enable_mte, 2192 }, 2193 #endif /* CONFIG_ARM64_MTE */ 2194 { 2195 .desc = "RCpc load-acquire (LDAPR)", 2196 .capability = ARM64_HAS_LDAPR, 2197 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2198 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2199 .sign = FTR_UNSIGNED, 2200 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, 2201 .matches = has_cpuid_feature, 2202 .min_field_value = 1, 2203 }, 2204 {}, 2205 }; 2206 2207 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2208 .matches = has_cpuid_feature, \ 2209 .sys_reg = reg, \ 2210 .field_pos = field, \ 2211 .sign = s, \ 2212 .min_field_value = min_value, 2213 2214 #define __HWCAP_CAP(name, cap_type, cap) \ 2215 .desc = name, \ 2216 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2217 .hwcap_type = cap_type, \ 2218 .hwcap = cap, \ 2219 2220 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 2221 { \ 2222 __HWCAP_CAP(#cap, cap_type, cap) \ 2223 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2224 } 2225 2226 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2227 { \ 2228 __HWCAP_CAP(#cap, cap_type, cap) \ 2229 .matches = cpucap_multi_entry_cap_matches, \ 2230 .match_list = list, \ 2231 } 2232 2233 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2234 { \ 2235 __HWCAP_CAP(#cap, cap_type, cap) \ 2236 .matches = match, \ 2237 } 2238 2239 #ifdef CONFIG_ARM64_PTR_AUTH 2240 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2241 { 2242 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 2243 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 2244 }, 2245 { 2246 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 2247 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 2248 }, 2249 {}, 2250 }; 2251 2252 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2253 { 2254 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 2255 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 2256 }, 2257 { 2258 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 2259 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 2260 }, 2261 {}, 2262 }; 2263 #endif 2264 2265 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2266 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2267 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2268 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2269 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2270 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2271 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2272 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2273 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2274 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2275 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2276 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2277 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2278 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2279 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2280 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2281 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2282 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2283 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2284 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2285 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2286 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2287 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2288 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2289 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2290 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2291 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2292 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2293 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2294 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2295 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2296 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2297 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2298 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2299 #ifdef CONFIG_ARM64_SVE 2300 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2301 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2302 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2303 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2304 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2305 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2306 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2307 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2308 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2309 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2310 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2311 #endif 2312 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2313 #ifdef CONFIG_ARM64_BTI 2314 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2315 #endif 2316 #ifdef CONFIG_ARM64_PTR_AUTH 2317 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2318 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2319 #endif 2320 #ifdef CONFIG_ARM64_MTE 2321 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), 2322 #endif /* CONFIG_ARM64_MTE */ 2323 {}, 2324 }; 2325 2326 #ifdef CONFIG_COMPAT 2327 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2328 { 2329 /* 2330 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2331 * in line with that of arm32 as in vfp_init(). We make sure that the 2332 * check is future proof, by making sure value is non-zero. 2333 */ 2334 u32 mvfr1; 2335 2336 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2337 if (scope == SCOPE_SYSTEM) 2338 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2339 else 2340 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2341 2342 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2343 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2344 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2345 } 2346 #endif 2347 2348 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2349 #ifdef CONFIG_COMPAT 2350 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2351 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2352 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2353 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2354 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2355 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2356 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2357 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2358 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2359 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2360 #endif 2361 {}, 2362 }; 2363 2364 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2365 { 2366 switch (cap->hwcap_type) { 2367 case CAP_HWCAP: 2368 cpu_set_feature(cap->hwcap); 2369 break; 2370 #ifdef CONFIG_COMPAT 2371 case CAP_COMPAT_HWCAP: 2372 compat_elf_hwcap |= (u32)cap->hwcap; 2373 break; 2374 case CAP_COMPAT_HWCAP2: 2375 compat_elf_hwcap2 |= (u32)cap->hwcap; 2376 break; 2377 #endif 2378 default: 2379 WARN_ON(1); 2380 break; 2381 } 2382 } 2383 2384 /* Check if we have a particular HWCAP enabled */ 2385 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2386 { 2387 bool rc; 2388 2389 switch (cap->hwcap_type) { 2390 case CAP_HWCAP: 2391 rc = cpu_have_feature(cap->hwcap); 2392 break; 2393 #ifdef CONFIG_COMPAT 2394 case CAP_COMPAT_HWCAP: 2395 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2396 break; 2397 case CAP_COMPAT_HWCAP2: 2398 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2399 break; 2400 #endif 2401 default: 2402 WARN_ON(1); 2403 rc = false; 2404 } 2405 2406 return rc; 2407 } 2408 2409 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2410 { 2411 /* We support emulation of accesses to CPU ID feature registers */ 2412 cpu_set_named_feature(CPUID); 2413 for (; hwcaps->matches; hwcaps++) 2414 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2415 cap_set_elf_hwcap(hwcaps); 2416 } 2417 2418 static void update_cpu_capabilities(u16 scope_mask) 2419 { 2420 int i; 2421 const struct arm64_cpu_capabilities *caps; 2422 2423 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2424 for (i = 0; i < ARM64_NCAPS; i++) { 2425 caps = cpu_hwcaps_ptrs[i]; 2426 if (!caps || !(caps->type & scope_mask) || 2427 cpus_have_cap(caps->capability) || 2428 !caps->matches(caps, cpucap_default_scope(caps))) 2429 continue; 2430 2431 if (caps->desc) 2432 pr_info("detected: %s\n", caps->desc); 2433 cpus_set_cap(caps->capability); 2434 2435 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2436 set_bit(caps->capability, boot_capabilities); 2437 } 2438 } 2439 2440 /* 2441 * Enable all the available capabilities on this CPU. The capabilities 2442 * with BOOT_CPU scope are handled separately and hence skipped here. 2443 */ 2444 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2445 { 2446 int i; 2447 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2448 2449 for_each_available_cap(i) { 2450 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2451 2452 if (WARN_ON(!cap)) 2453 continue; 2454 2455 if (!(cap->type & non_boot_scope)) 2456 continue; 2457 2458 if (cap->cpu_enable) 2459 cap->cpu_enable(cap); 2460 } 2461 return 0; 2462 } 2463 2464 /* 2465 * Run through the enabled capabilities and enable() it on all active 2466 * CPUs 2467 */ 2468 static void __init enable_cpu_capabilities(u16 scope_mask) 2469 { 2470 int i; 2471 const struct arm64_cpu_capabilities *caps; 2472 bool boot_scope; 2473 2474 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2475 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2476 2477 for (i = 0; i < ARM64_NCAPS; i++) { 2478 unsigned int num; 2479 2480 caps = cpu_hwcaps_ptrs[i]; 2481 if (!caps || !(caps->type & scope_mask)) 2482 continue; 2483 num = caps->capability; 2484 if (!cpus_have_cap(num)) 2485 continue; 2486 2487 /* Ensure cpus_have_const_cap(num) works */ 2488 static_branch_enable(&cpu_hwcap_keys[num]); 2489 2490 if (boot_scope && caps->cpu_enable) 2491 /* 2492 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2493 * before any secondary CPU boots. Thus, each secondary 2494 * will enable the capability as appropriate via 2495 * check_local_cpu_capabilities(). The only exception is 2496 * the boot CPU, for which the capability must be 2497 * enabled here. This approach avoids costly 2498 * stop_machine() calls for this case. 2499 */ 2500 caps->cpu_enable(caps); 2501 } 2502 2503 /* 2504 * For all non-boot scope capabilities, use stop_machine() 2505 * as it schedules the work allowing us to modify PSTATE, 2506 * instead of on_each_cpu() which uses an IPI, giving us a 2507 * PSTATE that disappears when we return. 2508 */ 2509 if (!boot_scope) 2510 stop_machine(cpu_enable_non_boot_scope_capabilities, 2511 NULL, cpu_online_mask); 2512 } 2513 2514 /* 2515 * Run through the list of capabilities to check for conflicts. 2516 * If the system has already detected a capability, take necessary 2517 * action on this CPU. 2518 */ 2519 static void verify_local_cpu_caps(u16 scope_mask) 2520 { 2521 int i; 2522 bool cpu_has_cap, system_has_cap; 2523 const struct arm64_cpu_capabilities *caps; 2524 2525 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2526 2527 for (i = 0; i < ARM64_NCAPS; i++) { 2528 caps = cpu_hwcaps_ptrs[i]; 2529 if (!caps || !(caps->type & scope_mask)) 2530 continue; 2531 2532 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2533 system_has_cap = cpus_have_cap(caps->capability); 2534 2535 if (system_has_cap) { 2536 /* 2537 * Check if the new CPU misses an advertised feature, 2538 * which is not safe to miss. 2539 */ 2540 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2541 break; 2542 /* 2543 * We have to issue cpu_enable() irrespective of 2544 * whether the CPU has it or not, as it is enabeld 2545 * system wide. It is upto the call back to take 2546 * appropriate action on this CPU. 2547 */ 2548 if (caps->cpu_enable) 2549 caps->cpu_enable(caps); 2550 } else { 2551 /* 2552 * Check if the CPU has this capability if it isn't 2553 * safe to have when the system doesn't. 2554 */ 2555 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2556 break; 2557 } 2558 } 2559 2560 if (i < ARM64_NCAPS) { 2561 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2562 smp_processor_id(), caps->capability, 2563 caps->desc, system_has_cap, cpu_has_cap); 2564 2565 if (cpucap_panic_on_conflict(caps)) 2566 cpu_panic_kernel(); 2567 else 2568 cpu_die_early(); 2569 } 2570 } 2571 2572 /* 2573 * Check for CPU features that are used in early boot 2574 * based on the Boot CPU value. 2575 */ 2576 static void check_early_cpu_features(void) 2577 { 2578 verify_cpu_asid_bits(); 2579 2580 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2581 } 2582 2583 static void 2584 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2585 { 2586 2587 for (; caps->matches; caps++) 2588 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2589 pr_crit("CPU%d: missing HWCAP: %s\n", 2590 smp_processor_id(), caps->desc); 2591 cpu_die_early(); 2592 } 2593 } 2594 2595 static void verify_sve_features(void) 2596 { 2597 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2598 u64 zcr = read_zcr_features(); 2599 2600 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2601 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2602 2603 if (len < safe_len || sve_verify_vq_map()) { 2604 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2605 smp_processor_id()); 2606 cpu_die_early(); 2607 } 2608 2609 /* Add checks on other ZCR bits here if necessary */ 2610 } 2611 2612 static void verify_hyp_capabilities(void) 2613 { 2614 u64 safe_mmfr1, mmfr0, mmfr1; 2615 int parange, ipa_max; 2616 unsigned int safe_vmid_bits, vmid_bits; 2617 2618 if (!IS_ENABLED(CONFIG_KVM)) 2619 return; 2620 2621 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 2622 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 2623 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 2624 2625 /* Verify VMID bits */ 2626 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 2627 vmid_bits = get_vmid_bits(mmfr1); 2628 if (vmid_bits < safe_vmid_bits) { 2629 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 2630 cpu_die_early(); 2631 } 2632 2633 /* Verify IPA range */ 2634 parange = cpuid_feature_extract_unsigned_field(mmfr0, 2635 ID_AA64MMFR0_PARANGE_SHIFT); 2636 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 2637 if (ipa_max < get_kvm_ipa_limit()) { 2638 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 2639 cpu_die_early(); 2640 } 2641 } 2642 2643 /* 2644 * Run through the enabled system capabilities and enable() it on this CPU. 2645 * The capabilities were decided based on the available CPUs at the boot time. 2646 * Any new CPU should match the system wide status of the capability. If the 2647 * new CPU doesn't have a capability which the system now has enabled, we 2648 * cannot do anything to fix it up and could cause unexpected failures. So 2649 * we park the CPU. 2650 */ 2651 static void verify_local_cpu_capabilities(void) 2652 { 2653 /* 2654 * The capabilities with SCOPE_BOOT_CPU are checked from 2655 * check_early_cpu_features(), as they need to be verified 2656 * on all secondary CPUs. 2657 */ 2658 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2659 2660 verify_local_elf_hwcaps(arm64_elf_hwcaps); 2661 2662 if (system_supports_32bit_el0()) 2663 verify_local_elf_hwcaps(compat_elf_hwcaps); 2664 2665 if (system_supports_sve()) 2666 verify_sve_features(); 2667 2668 if (is_hyp_mode_available()) 2669 verify_hyp_capabilities(); 2670 } 2671 2672 void check_local_cpu_capabilities(void) 2673 { 2674 /* 2675 * All secondary CPUs should conform to the early CPU features 2676 * in use by the kernel based on boot CPU. 2677 */ 2678 check_early_cpu_features(); 2679 2680 /* 2681 * If we haven't finalised the system capabilities, this CPU gets 2682 * a chance to update the errata work arounds and local features. 2683 * Otherwise, this CPU should verify that it has all the system 2684 * advertised capabilities. 2685 */ 2686 if (!system_capabilities_finalized()) 2687 update_cpu_capabilities(SCOPE_LOCAL_CPU); 2688 else 2689 verify_local_cpu_capabilities(); 2690 } 2691 2692 static void __init setup_boot_cpu_capabilities(void) 2693 { 2694 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 2695 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 2696 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 2697 enable_cpu_capabilities(SCOPE_BOOT_CPU); 2698 } 2699 2700 bool this_cpu_has_cap(unsigned int n) 2701 { 2702 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 2703 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2704 2705 if (cap) 2706 return cap->matches(cap, SCOPE_LOCAL_CPU); 2707 } 2708 2709 return false; 2710 } 2711 2712 /* 2713 * This helper function is used in a narrow window when, 2714 * - The system wide safe registers are set with all the SMP CPUs and, 2715 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 2716 * In all other cases cpus_have_{const_}cap() should be used. 2717 */ 2718 static bool __maybe_unused __system_matches_cap(unsigned int n) 2719 { 2720 if (n < ARM64_NCAPS) { 2721 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2722 2723 if (cap) 2724 return cap->matches(cap, SCOPE_SYSTEM); 2725 } 2726 return false; 2727 } 2728 2729 void cpu_set_feature(unsigned int num) 2730 { 2731 WARN_ON(num >= MAX_CPU_FEATURES); 2732 elf_hwcap |= BIT(num); 2733 } 2734 EXPORT_SYMBOL_GPL(cpu_set_feature); 2735 2736 bool cpu_have_feature(unsigned int num) 2737 { 2738 WARN_ON(num >= MAX_CPU_FEATURES); 2739 return elf_hwcap & BIT(num); 2740 } 2741 EXPORT_SYMBOL_GPL(cpu_have_feature); 2742 2743 unsigned long cpu_get_elf_hwcap(void) 2744 { 2745 /* 2746 * We currently only populate the first 32 bits of AT_HWCAP. Please 2747 * note that for userspace compatibility we guarantee that bits 62 2748 * and 63 will always be returned as 0. 2749 */ 2750 return lower_32_bits(elf_hwcap); 2751 } 2752 2753 unsigned long cpu_get_elf_hwcap2(void) 2754 { 2755 return upper_32_bits(elf_hwcap); 2756 } 2757 2758 static void __init setup_system_capabilities(void) 2759 { 2760 /* 2761 * We have finalised the system-wide safe feature 2762 * registers, finalise the capabilities that depend 2763 * on it. Also enable all the available capabilities, 2764 * that are not enabled already. 2765 */ 2766 update_cpu_capabilities(SCOPE_SYSTEM); 2767 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2768 } 2769 2770 void __init setup_cpu_features(void) 2771 { 2772 u32 cwg; 2773 2774 setup_system_capabilities(); 2775 setup_elf_hwcaps(arm64_elf_hwcaps); 2776 2777 if (system_supports_32bit_el0()) 2778 setup_elf_hwcaps(compat_elf_hwcaps); 2779 2780 if (system_uses_ttbr0_pan()) 2781 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2782 2783 sve_setup(); 2784 minsigstksz_setup(); 2785 2786 /* Advertise that we have computed the system capabilities */ 2787 finalize_system_capabilities(); 2788 2789 /* 2790 * Check for sane CTR_EL0.CWG value. 2791 */ 2792 cwg = cache_type_cwg(); 2793 if (!cwg) 2794 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2795 ARCH_DMA_MINALIGN); 2796 } 2797 2798 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 2799 { 2800 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 2801 } 2802 2803 /* 2804 * We emulate only the following system register space. 2805 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 2806 * See Table C5-6 System instruction encodings for System register accesses, 2807 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 2808 */ 2809 static inline bool __attribute_const__ is_emulated(u32 id) 2810 { 2811 return (sys_reg_Op0(id) == 0x3 && 2812 sys_reg_CRn(id) == 0x0 && 2813 sys_reg_Op1(id) == 0x0 && 2814 (sys_reg_CRm(id) == 0 || 2815 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 2816 } 2817 2818 /* 2819 * With CRm == 0, reg should be one of : 2820 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 2821 */ 2822 static inline int emulate_id_reg(u32 id, u64 *valp) 2823 { 2824 switch (id) { 2825 case SYS_MIDR_EL1: 2826 *valp = read_cpuid_id(); 2827 break; 2828 case SYS_MPIDR_EL1: 2829 *valp = SYS_MPIDR_SAFE_VAL; 2830 break; 2831 case SYS_REVIDR_EL1: 2832 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 2833 *valp = 0; 2834 break; 2835 default: 2836 return -EINVAL; 2837 } 2838 2839 return 0; 2840 } 2841 2842 static int emulate_sys_reg(u32 id, u64 *valp) 2843 { 2844 struct arm64_ftr_reg *regp; 2845 2846 if (!is_emulated(id)) 2847 return -EINVAL; 2848 2849 if (sys_reg_CRm(id) == 0) 2850 return emulate_id_reg(id, valp); 2851 2852 regp = get_arm64_ftr_reg_nowarn(id); 2853 if (regp) 2854 *valp = arm64_ftr_reg_user_value(regp); 2855 else 2856 /* 2857 * The untracked registers are either IMPLEMENTATION DEFINED 2858 * (e.g, ID_AFR0_EL1) or reserved RAZ. 2859 */ 2860 *valp = 0; 2861 return 0; 2862 } 2863 2864 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 2865 { 2866 int rc; 2867 u64 val; 2868 2869 rc = emulate_sys_reg(sys_reg, &val); 2870 if (!rc) { 2871 pt_regs_write_reg(regs, rt, val); 2872 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 2873 } 2874 return rc; 2875 } 2876 2877 static int emulate_mrs(struct pt_regs *regs, u32 insn) 2878 { 2879 u32 sys_reg, rt; 2880 2881 /* 2882 * sys_reg values are defined as used in mrs/msr instruction. 2883 * shift the imm value to get the encoding. 2884 */ 2885 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 2886 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 2887 return do_emulate_mrs(regs, sys_reg, rt); 2888 } 2889 2890 static struct undef_hook mrs_hook = { 2891 .instr_mask = 0xfff00000, 2892 .instr_val = 0xd5300000, 2893 .pstate_mask = PSR_AA32_MODE_MASK, 2894 .pstate_val = PSR_MODE_EL0t, 2895 .fn = emulate_mrs, 2896 }; 2897 2898 static int __init enable_mrs_emulation(void) 2899 { 2900 register_undef_hook(&mrs_hook); 2901 return 0; 2902 } 2903 2904 core_initcall(enable_mrs_emulation); 2905 2906 enum mitigation_state arm64_get_meltdown_state(void) 2907 { 2908 if (__meltdown_safe) 2909 return SPECTRE_UNAFFECTED; 2910 2911 if (arm64_kernel_unmapped_at_el0()) 2912 return SPECTRE_MITIGATED; 2913 2914 return SPECTRE_VULNERABLE; 2915 } 2916 2917 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 2918 char *buf) 2919 { 2920 switch (arm64_get_meltdown_state()) { 2921 case SPECTRE_UNAFFECTED: 2922 return sprintf(buf, "Not affected\n"); 2923 2924 case SPECTRE_MITIGATED: 2925 return sprintf(buf, "Mitigation: PTI\n"); 2926 2927 default: 2928 return sprintf(buf, "Vulnerable\n"); 2929 } 2930 } 2931