1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/types.h> 71 #include <linux/minmax.h> 72 #include <linux/mm.h> 73 #include <linux/cpu.h> 74 #include <linux/kasan.h> 75 #include <asm/cpu.h> 76 #include <asm/cpufeature.h> 77 #include <asm/cpu_ops.h> 78 #include <asm/fpsimd.h> 79 #include <asm/kvm_host.h> 80 #include <asm/mmu_context.h> 81 #include <asm/mte.h> 82 #include <asm/processor.h> 83 #include <asm/sysreg.h> 84 #include <asm/traps.h> 85 #include <asm/virt.h> 86 87 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 88 static unsigned long elf_hwcap __read_mostly; 89 90 #ifdef CONFIG_COMPAT 91 #define COMPAT_ELF_HWCAP_DEFAULT \ 92 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 93 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 94 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 95 COMPAT_HWCAP_LPAE) 96 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 97 unsigned int compat_elf_hwcap2 __read_mostly; 98 #endif 99 100 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 101 EXPORT_SYMBOL(cpu_hwcaps); 102 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 103 104 /* Need also bit for ARM64_CB_PATCH */ 105 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 106 107 bool arm64_use_ng_mappings = false; 108 EXPORT_SYMBOL(arm64_use_ng_mappings); 109 110 /* 111 * Flag to indicate if we have computed the system wide 112 * capabilities based on the boot time active CPUs. This 113 * will be used to determine if a new booting CPU should 114 * go through the verification process to make sure that it 115 * supports the system capabilities, without using a hotplug 116 * notifier. This is also used to decide if we could use 117 * the fast path for checking constant CPU caps. 118 */ 119 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 120 EXPORT_SYMBOL(arm64_const_caps_ready); 121 static inline void finalize_system_capabilities(void) 122 { 123 static_branch_enable(&arm64_const_caps_ready); 124 } 125 126 void dump_cpu_features(void) 127 { 128 /* file-wide pr_fmt adds "CPU features: " prefix */ 129 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 130 } 131 132 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 133 EXPORT_SYMBOL(cpu_hwcap_keys); 134 135 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 136 { \ 137 .sign = SIGNED, \ 138 .visible = VISIBLE, \ 139 .strict = STRICT, \ 140 .type = TYPE, \ 141 .shift = SHIFT, \ 142 .width = WIDTH, \ 143 .safe_val = SAFE_VAL, \ 144 } 145 146 /* Define a feature with unsigned values */ 147 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 148 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 149 150 /* Define a feature with a signed value */ 151 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 152 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 153 154 #define ARM64_FTR_END \ 155 { \ 156 .width = 0, \ 157 } 158 159 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 160 161 static bool __system_matches_cap(unsigned int n); 162 163 /* 164 * NOTE: Any changes to the visibility of features should be kept in 165 * sync with the documentation of the CPU feature register ABI. 166 */ 167 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 168 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), 169 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0), 170 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 171 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 172 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 173 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 174 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 175 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 176 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 182 ARM64_FTR_END, 183 }; 184 185 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 192 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 193 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 195 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 199 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 200 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 202 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 204 ARM64_FTR_END, 205 }; 206 207 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 208 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 215 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 218 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 219 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 224 ARM64_FTR_END, 225 }; 226 227 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 231 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 233 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 234 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 235 ARM64_FTR_END, 236 }; 237 238 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 239 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 240 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 242 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 244 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 246 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 248 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 250 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 252 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 254 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 256 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 257 ARM64_FTR_END, 258 }; 259 260 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), 263 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), 264 /* 265 * Page size not being supported at Stage-2 is not fatal. You 266 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 267 * your favourite nesting hypervisor. 268 * 269 * There is a small corner case where the hypervisor explicitly 270 * advertises a given granule size at Stage-2 (value 2) on some 271 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 272 * vCPUs. Although this is not forbidden by the architecture, it 273 * indicates that the hypervisor is being silly (or buggy). 274 * 275 * We make no effort to cope with this and pretend that if these 276 * fields are inconsistent across vCPUs, then it isn't worth 277 * trying to bring KVM up. 278 */ 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 282 /* 283 * We already refuse to boot CPUs that don't support our configured 284 * page size, so we can only detect mismatches for a page size other 285 * than the one we're currently using. Unfortunately, SoCs like this 286 * exist in the wild so, even though we don't like it, we'll have to go 287 * along with it and treat them as non-strict. 288 */ 289 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 290 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 292 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 294 /* Linux shouldn't care about secure memory */ 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 298 /* 299 * Differing PARange is fine as long as all peripherals and memory are mapped 300 * within the minimum PARange of all CPUs 301 */ 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 303 ARM64_FTR_END, 304 }; 305 306 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), 310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 317 ARM64_FTR_END, 318 }; 319 320 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0), 325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0), 327 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0), 329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 336 ARM64_FTR_END, 337 }; 338 339 static const struct arm64_ftr_bits ftr_ctr[] = { 340 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 341 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 342 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 343 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 345 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 346 /* 347 * Linux can handle differing I-cache policies. Userspace JITs will 348 * make use of *minLine. 349 * If we have differing I-cache policies, report it as the weakest - VIPT. 350 */ 351 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 352 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 353 ARM64_FTR_END, 354 }; 355 356 static struct arm64_ftr_override __ro_after_init no_override = { }; 357 358 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 359 .name = "SYS_CTR_EL0", 360 .ftr_bits = ftr_ctr, 361 .override = &no_override, 362 }; 363 364 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 365 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 370 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 373 ARM64_FTR_END, 374 }; 375 376 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 377 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0), 378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 382 /* 383 * We can instantiate multiple PMU instances with different levels 384 * of support. 385 */ 386 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 388 ARM64_FTR_END, 389 }; 390 391 static const struct arm64_ftr_bits ftr_mvfr2[] = { 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 394 ARM64_FTR_END, 395 }; 396 397 static const struct arm64_ftr_bits ftr_dczid[] = { 398 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), 399 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), 400 ARM64_FTR_END, 401 }; 402 403 static const struct arm64_ftr_bits ftr_id_isar0[] = { 404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 410 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 411 ARM64_FTR_END, 412 }; 413 414 static const struct arm64_ftr_bits ftr_id_isar5[] = { 415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 417 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 419 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 421 ARM64_FTR_END, 422 }; 423 424 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 432 433 /* 434 * SpecSEI = 1 indicates that the PE might generate an SError on an 435 * external abort on speculative read. It is safe to assume that an 436 * SError might be generated than it will not be. Hence it has been 437 * classified as FTR_HIGHER_SAFE. 438 */ 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 440 ARM64_FTR_END, 441 }; 442 443 static const struct arm64_ftr_bits ftr_id_isar4[] = { 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 452 ARM64_FTR_END, 453 }; 454 455 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 457 ARM64_FTR_END, 458 }; 459 460 static const struct arm64_ftr_bits ftr_id_isar6[] = { 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 468 ARM64_FTR_END, 469 }; 470 471 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 478 ARM64_FTR_END, 479 }; 480 481 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 490 ARM64_FTR_END, 491 }; 492 493 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 496 ARM64_FTR_END, 497 }; 498 499 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 500 /* [31:28] TraceFilt */ 501 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 508 ARM64_FTR_END, 509 }; 510 511 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 512 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 513 ARM64_FTR_END, 514 }; 515 516 static const struct arm64_ftr_bits ftr_zcr[] = { 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 518 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 519 ARM64_FTR_END, 520 }; 521 522 /* 523 * Common ftr bits for a 32bit register with all hidden, strict 524 * attributes, with 4bit feature fields and a default safe value of 525 * 0. Covers the following 32bit registers: 526 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 527 */ 528 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 537 ARM64_FTR_END, 538 }; 539 540 /* Table for a single 32bit feature value */ 541 static const struct arm64_ftr_bits ftr_single32[] = { 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 543 ARM64_FTR_END, 544 }; 545 546 static const struct arm64_ftr_bits ftr_raz[] = { 547 ARM64_FTR_END, 548 }; 549 550 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) { \ 551 .sys_id = id, \ 552 .reg = &(struct arm64_ftr_reg){ \ 553 .name = #id, \ 554 .override = (ovr), \ 555 .ftr_bits = &((table)[0]), \ 556 }} 557 558 #define ARM64_FTR_REG(id, table) ARM64_FTR_REG_OVERRIDE(id, table, &no_override) 559 560 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 561 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 562 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 563 564 static const struct __ftr_reg_entry { 565 u32 sys_id; 566 struct arm64_ftr_reg *reg; 567 } arm64_ftr_regs[] = { 568 569 /* Op1 = 0, CRn = 0, CRm = 1 */ 570 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 571 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 572 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 573 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 574 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 575 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 576 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 577 578 /* Op1 = 0, CRn = 0, CRm = 2 */ 579 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 580 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 581 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 582 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 583 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 584 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 585 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 586 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 587 588 /* Op1 = 0, CRn = 0, CRm = 3 */ 589 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 590 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 591 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 592 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 593 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 594 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 595 596 /* Op1 = 0, CRn = 0, CRm = 4 */ 597 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 598 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 599 &id_aa64pfr1_override), 600 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 601 602 /* Op1 = 0, CRn = 0, CRm = 5 */ 603 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 604 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 605 606 /* Op1 = 0, CRn = 0, CRm = 6 */ 607 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 608 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 609 &id_aa64isar1_override), 610 611 /* Op1 = 0, CRn = 0, CRm = 7 */ 612 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 613 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 614 &id_aa64mmfr1_override), 615 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 616 617 /* Op1 = 0, CRn = 1, CRm = 2 */ 618 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 619 620 /* Op1 = 3, CRn = 0, CRm = 0 */ 621 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 622 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 623 624 /* Op1 = 3, CRn = 14, CRm = 0 */ 625 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 626 }; 627 628 static int search_cmp_ftr_reg(const void *id, const void *regp) 629 { 630 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 631 } 632 633 /* 634 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 635 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 636 * ascending order of sys_id, we use binary search to find a matching 637 * entry. 638 * 639 * returns - Upon success, matching ftr_reg entry for id. 640 * - NULL on failure. It is upto the caller to decide 641 * the impact of a failure. 642 */ 643 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 644 { 645 const struct __ftr_reg_entry *ret; 646 647 ret = bsearch((const void *)(unsigned long)sys_id, 648 arm64_ftr_regs, 649 ARRAY_SIZE(arm64_ftr_regs), 650 sizeof(arm64_ftr_regs[0]), 651 search_cmp_ftr_reg); 652 if (ret) 653 return ret->reg; 654 return NULL; 655 } 656 657 /* 658 * get_arm64_ftr_reg - Looks up a feature register entry using 659 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 660 * 661 * returns - Upon success, matching ftr_reg entry for id. 662 * - NULL on failure but with an WARN_ON(). 663 */ 664 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 665 { 666 struct arm64_ftr_reg *reg; 667 668 reg = get_arm64_ftr_reg_nowarn(sys_id); 669 670 /* 671 * Requesting a non-existent register search is an error. Warn 672 * and let the caller handle it. 673 */ 674 WARN_ON(!reg); 675 return reg; 676 } 677 678 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 679 s64 ftr_val) 680 { 681 u64 mask = arm64_ftr_mask(ftrp); 682 683 reg &= ~mask; 684 reg |= (ftr_val << ftrp->shift) & mask; 685 return reg; 686 } 687 688 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 689 s64 cur) 690 { 691 s64 ret = 0; 692 693 switch (ftrp->type) { 694 case FTR_EXACT: 695 ret = ftrp->safe_val; 696 break; 697 case FTR_LOWER_SAFE: 698 ret = min(new, cur); 699 break; 700 case FTR_HIGHER_OR_ZERO_SAFE: 701 if (!cur || !new) 702 break; 703 fallthrough; 704 case FTR_HIGHER_SAFE: 705 ret = max(new, cur); 706 break; 707 default: 708 BUG(); 709 } 710 711 return ret; 712 } 713 714 static void __init sort_ftr_regs(void) 715 { 716 unsigned int i; 717 718 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 719 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 720 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 721 unsigned int j = 0; 722 723 /* 724 * Features here must be sorted in descending order with respect 725 * to their shift values and should not overlap with each other. 726 */ 727 for (; ftr_bits->width != 0; ftr_bits++, j++) { 728 unsigned int width = ftr_reg->ftr_bits[j].width; 729 unsigned int shift = ftr_reg->ftr_bits[j].shift; 730 unsigned int prev_shift; 731 732 WARN((shift + width) > 64, 733 "%s has invalid feature at shift %d\n", 734 ftr_reg->name, shift); 735 736 /* 737 * Skip the first feature. There is nothing to 738 * compare against for now. 739 */ 740 if (j == 0) 741 continue; 742 743 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 744 WARN((shift + width) > prev_shift, 745 "%s has feature overlap at shift %d\n", 746 ftr_reg->name, shift); 747 } 748 749 /* 750 * Skip the first register. There is nothing to 751 * compare against for now. 752 */ 753 if (i == 0) 754 continue; 755 /* 756 * Registers here must be sorted in ascending order with respect 757 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 758 * to work correctly. 759 */ 760 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 761 } 762 } 763 764 /* 765 * Initialise the CPU feature register from Boot CPU values. 766 * Also initiliases the strict_mask for the register. 767 * Any bits that are not covered by an arm64_ftr_bits entry are considered 768 * RES0 for the system-wide value, and must strictly match. 769 */ 770 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 771 { 772 u64 val = 0; 773 u64 strict_mask = ~0x0ULL; 774 u64 user_mask = 0; 775 u64 valid_mask = 0; 776 777 const struct arm64_ftr_bits *ftrp; 778 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 779 780 if (!reg) 781 return; 782 783 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 784 u64 ftr_mask = arm64_ftr_mask(ftrp); 785 s64 ftr_new = arm64_ftr_value(ftrp, new); 786 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 787 788 if ((ftr_mask & reg->override->mask) == ftr_mask) { 789 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 790 char *str = NULL; 791 792 if (ftr_ovr != tmp) { 793 /* Unsafe, remove the override */ 794 reg->override->mask &= ~ftr_mask; 795 reg->override->val &= ~ftr_mask; 796 tmp = ftr_ovr; 797 str = "ignoring override"; 798 } else if (ftr_new != tmp) { 799 /* Override was valid */ 800 ftr_new = tmp; 801 str = "forced"; 802 } else if (ftr_ovr == tmp) { 803 /* Override was the safe value */ 804 str = "already set"; 805 } 806 807 if (str) 808 pr_warn("%s[%d:%d]: %s to %llx\n", 809 reg->name, 810 ftrp->shift + ftrp->width - 1, 811 ftrp->shift, str, tmp); 812 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 813 reg->override->val &= ~ftr_mask; 814 pr_warn("%s[%d:%d]: impossible override, ignored\n", 815 reg->name, 816 ftrp->shift + ftrp->width - 1, 817 ftrp->shift); 818 } 819 820 val = arm64_ftr_set_value(ftrp, val, ftr_new); 821 822 valid_mask |= ftr_mask; 823 if (!ftrp->strict) 824 strict_mask &= ~ftr_mask; 825 if (ftrp->visible) 826 user_mask |= ftr_mask; 827 else 828 reg->user_val = arm64_ftr_set_value(ftrp, 829 reg->user_val, 830 ftrp->safe_val); 831 } 832 833 val &= valid_mask; 834 835 reg->sys_val = val; 836 reg->strict_mask = strict_mask; 837 reg->user_mask = user_mask; 838 } 839 840 extern const struct arm64_cpu_capabilities arm64_errata[]; 841 static const struct arm64_cpu_capabilities arm64_features[]; 842 843 static void __init 844 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 845 { 846 for (; caps->matches; caps++) { 847 if (WARN(caps->capability >= ARM64_NCAPS, 848 "Invalid capability %d\n", caps->capability)) 849 continue; 850 if (WARN(cpu_hwcaps_ptrs[caps->capability], 851 "Duplicate entry for capability %d\n", 852 caps->capability)) 853 continue; 854 cpu_hwcaps_ptrs[caps->capability] = caps; 855 } 856 } 857 858 static void __init init_cpu_hwcaps_indirect_list(void) 859 { 860 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 861 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 862 } 863 864 static void __init setup_boot_cpu_capabilities(void); 865 866 void __init init_cpu_features(struct cpuinfo_arm64 *info) 867 { 868 /* Before we start using the tables, make sure it is sorted */ 869 sort_ftr_regs(); 870 871 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 872 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 873 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 874 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 875 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 876 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 877 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 878 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 879 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 880 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 881 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 882 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 883 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 884 885 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 886 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 887 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 888 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 889 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 890 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 891 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 892 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 893 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 894 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 895 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 896 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 897 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 898 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 899 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 900 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 901 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 902 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 903 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 904 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 905 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 906 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 907 } 908 909 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 910 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 911 sve_init_vq_map(); 912 } 913 914 /* 915 * Initialize the indirect array of CPU hwcaps capabilities pointers 916 * before we handle the boot CPU below. 917 */ 918 init_cpu_hwcaps_indirect_list(); 919 920 /* 921 * Detect and enable early CPU capabilities based on the boot CPU, 922 * after we have initialised the CPU feature infrastructure. 923 */ 924 setup_boot_cpu_capabilities(); 925 } 926 927 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 928 { 929 const struct arm64_ftr_bits *ftrp; 930 931 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 932 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 933 s64 ftr_new = arm64_ftr_value(ftrp, new); 934 935 if (ftr_cur == ftr_new) 936 continue; 937 /* Find a safe value */ 938 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 939 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 940 } 941 942 } 943 944 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 945 { 946 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 947 948 if (!regp) 949 return 0; 950 951 update_cpu_ftr_reg(regp, val); 952 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 953 return 0; 954 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 955 regp->name, boot, cpu, val); 956 return 1; 957 } 958 959 static void relax_cpu_ftr_reg(u32 sys_id, int field) 960 { 961 const struct arm64_ftr_bits *ftrp; 962 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 963 964 if (!regp) 965 return; 966 967 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 968 if (ftrp->shift == field) { 969 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 970 break; 971 } 972 } 973 974 /* Bogus field? */ 975 WARN_ON(!ftrp->width); 976 } 977 978 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info, 979 struct cpuinfo_arm64 *boot) 980 { 981 int taint = 0; 982 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 983 984 /* 985 * If we don't have AArch32 at all then skip the checks entirely 986 * as the register values may be UNKNOWN and we're not going to be 987 * using them for anything. 988 */ 989 if (!id_aa64pfr0_32bit_el0(pfr0)) 990 return taint; 991 992 /* 993 * If we don't have AArch32 at EL1, then relax the strictness of 994 * EL1-dependent register fields to avoid spurious sanity check fails. 995 */ 996 if (!id_aa64pfr0_32bit_el1(pfr0)) { 997 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 998 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 999 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 1000 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 1001 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 1002 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 1003 } 1004 1005 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1006 info->reg_id_dfr0, boot->reg_id_dfr0); 1007 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1008 info->reg_id_dfr1, boot->reg_id_dfr1); 1009 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1010 info->reg_id_isar0, boot->reg_id_isar0); 1011 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1012 info->reg_id_isar1, boot->reg_id_isar1); 1013 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1014 info->reg_id_isar2, boot->reg_id_isar2); 1015 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1016 info->reg_id_isar3, boot->reg_id_isar3); 1017 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1018 info->reg_id_isar4, boot->reg_id_isar4); 1019 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1020 info->reg_id_isar5, boot->reg_id_isar5); 1021 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1022 info->reg_id_isar6, boot->reg_id_isar6); 1023 1024 /* 1025 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1026 * ACTLR formats could differ across CPUs and therefore would have to 1027 * be trapped for virtualization anyway. 1028 */ 1029 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1030 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1031 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1032 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1033 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1034 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1035 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1036 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1037 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1038 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1039 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1040 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1041 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1042 info->reg_id_pfr0, boot->reg_id_pfr0); 1043 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1044 info->reg_id_pfr1, boot->reg_id_pfr1); 1045 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1046 info->reg_id_pfr2, boot->reg_id_pfr2); 1047 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1048 info->reg_mvfr0, boot->reg_mvfr0); 1049 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1050 info->reg_mvfr1, boot->reg_mvfr1); 1051 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1052 info->reg_mvfr2, boot->reg_mvfr2); 1053 1054 return taint; 1055 } 1056 1057 /* 1058 * Update system wide CPU feature registers with the values from a 1059 * non-boot CPU. Also performs SANITY checks to make sure that there 1060 * aren't any insane variations from that of the boot CPU. 1061 */ 1062 void update_cpu_features(int cpu, 1063 struct cpuinfo_arm64 *info, 1064 struct cpuinfo_arm64 *boot) 1065 { 1066 int taint = 0; 1067 1068 /* 1069 * The kernel can handle differing I-cache policies, but otherwise 1070 * caches should look identical. Userspace JITs will make use of 1071 * *minLine. 1072 */ 1073 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1074 info->reg_ctr, boot->reg_ctr); 1075 1076 /* 1077 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1078 * could result in too much or too little memory being zeroed if a 1079 * process is preempted and migrated between CPUs. 1080 */ 1081 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1082 info->reg_dczid, boot->reg_dczid); 1083 1084 /* If different, timekeeping will be broken (especially with KVM) */ 1085 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1086 info->reg_cntfrq, boot->reg_cntfrq); 1087 1088 /* 1089 * The kernel uses self-hosted debug features and expects CPUs to 1090 * support identical debug features. We presently need CTX_CMPs, WRPs, 1091 * and BRPs to be identical. 1092 * ID_AA64DFR1 is currently RES0. 1093 */ 1094 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1095 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1096 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1097 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1098 /* 1099 * Even in big.LITTLE, processors should be identical instruction-set 1100 * wise. 1101 */ 1102 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1103 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1104 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1105 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1106 1107 /* 1108 * Differing PARange support is fine as long as all peripherals and 1109 * memory are mapped within the minimum PARange of all CPUs. 1110 * Linux should not care about secure memory. 1111 */ 1112 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1113 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1114 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1115 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1116 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1117 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1118 1119 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1120 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1121 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1122 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1123 1124 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1125 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1126 1127 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 1128 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1129 info->reg_zcr, boot->reg_zcr); 1130 1131 /* Probe vector lengths, unless we already gave up on SVE */ 1132 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 1133 !system_capabilities_finalized()) 1134 sve_update_vq_map(); 1135 } 1136 1137 /* 1138 * This relies on a sanitised view of the AArch64 ID registers 1139 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1140 */ 1141 taint |= update_32bit_cpu_features(cpu, info, boot); 1142 1143 /* 1144 * Mismatched CPU features are a recipe for disaster. Don't even 1145 * pretend to support them. 1146 */ 1147 if (taint) { 1148 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1149 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1150 } 1151 } 1152 1153 u64 read_sanitised_ftr_reg(u32 id) 1154 { 1155 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1156 1157 if (!regp) 1158 return 0; 1159 return regp->sys_val; 1160 } 1161 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1162 1163 #define read_sysreg_case(r) \ 1164 case r: val = read_sysreg_s(r); break; 1165 1166 /* 1167 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1168 * Read the system register on the current CPU 1169 */ 1170 u64 __read_sysreg_by_encoding(u32 sys_id) 1171 { 1172 struct arm64_ftr_reg *regp; 1173 u64 val; 1174 1175 switch (sys_id) { 1176 read_sysreg_case(SYS_ID_PFR0_EL1); 1177 read_sysreg_case(SYS_ID_PFR1_EL1); 1178 read_sysreg_case(SYS_ID_PFR2_EL1); 1179 read_sysreg_case(SYS_ID_DFR0_EL1); 1180 read_sysreg_case(SYS_ID_DFR1_EL1); 1181 read_sysreg_case(SYS_ID_MMFR0_EL1); 1182 read_sysreg_case(SYS_ID_MMFR1_EL1); 1183 read_sysreg_case(SYS_ID_MMFR2_EL1); 1184 read_sysreg_case(SYS_ID_MMFR3_EL1); 1185 read_sysreg_case(SYS_ID_MMFR4_EL1); 1186 read_sysreg_case(SYS_ID_MMFR5_EL1); 1187 read_sysreg_case(SYS_ID_ISAR0_EL1); 1188 read_sysreg_case(SYS_ID_ISAR1_EL1); 1189 read_sysreg_case(SYS_ID_ISAR2_EL1); 1190 read_sysreg_case(SYS_ID_ISAR3_EL1); 1191 read_sysreg_case(SYS_ID_ISAR4_EL1); 1192 read_sysreg_case(SYS_ID_ISAR5_EL1); 1193 read_sysreg_case(SYS_ID_ISAR6_EL1); 1194 read_sysreg_case(SYS_MVFR0_EL1); 1195 read_sysreg_case(SYS_MVFR1_EL1); 1196 read_sysreg_case(SYS_MVFR2_EL1); 1197 1198 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1199 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1200 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1201 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1202 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1203 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1204 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1205 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1206 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1207 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1208 1209 read_sysreg_case(SYS_CNTFRQ_EL0); 1210 read_sysreg_case(SYS_CTR_EL0); 1211 read_sysreg_case(SYS_DCZID_EL0); 1212 1213 default: 1214 BUG(); 1215 return 0; 1216 } 1217 1218 regp = get_arm64_ftr_reg(sys_id); 1219 if (regp) { 1220 val &= ~regp->override->mask; 1221 val |= (regp->override->val & regp->override->mask); 1222 } 1223 1224 return val; 1225 } 1226 1227 #include <linux/irqchip/arm-gic-v3.h> 1228 1229 static bool 1230 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1231 { 1232 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 1233 1234 return val >= entry->min_field_value; 1235 } 1236 1237 static bool 1238 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1239 { 1240 u64 val; 1241 1242 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1243 if (scope == SCOPE_SYSTEM) 1244 val = read_sanitised_ftr_reg(entry->sys_reg); 1245 else 1246 val = __read_sysreg_by_encoding(entry->sys_reg); 1247 1248 return feature_matches(val, entry); 1249 } 1250 1251 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1252 { 1253 bool has_sre; 1254 1255 if (!has_cpuid_feature(entry, scope)) 1256 return false; 1257 1258 has_sre = gic_enable_sre(); 1259 if (!has_sre) 1260 pr_warn_once("%s present but disabled by higher exception level\n", 1261 entry->desc); 1262 1263 return has_sre; 1264 } 1265 1266 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1267 { 1268 u32 midr = read_cpuid_id(); 1269 1270 /* Cavium ThunderX pass 1.x and 2.x */ 1271 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1272 MIDR_CPU_VAR_REV(0, 0), 1273 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1274 } 1275 1276 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1277 { 1278 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1279 1280 return cpuid_feature_extract_signed_field(pfr0, 1281 ID_AA64PFR0_FP_SHIFT) < 0; 1282 } 1283 1284 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1285 int scope) 1286 { 1287 u64 ctr; 1288 1289 if (scope == SCOPE_SYSTEM) 1290 ctr = arm64_ftr_reg_ctrel0.sys_val; 1291 else 1292 ctr = read_cpuid_effective_cachetype(); 1293 1294 return ctr & BIT(CTR_IDC_SHIFT); 1295 } 1296 1297 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1298 { 1299 /* 1300 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1301 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1302 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1303 * value. 1304 */ 1305 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 1306 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1307 } 1308 1309 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1310 int scope) 1311 { 1312 u64 ctr; 1313 1314 if (scope == SCOPE_SYSTEM) 1315 ctr = arm64_ftr_reg_ctrel0.sys_val; 1316 else 1317 ctr = read_cpuid_cachetype(); 1318 1319 return ctr & BIT(CTR_DIC_SHIFT); 1320 } 1321 1322 static bool __maybe_unused 1323 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1324 { 1325 /* 1326 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1327 * may share TLB entries with a CPU stuck in the crashed 1328 * kernel. 1329 */ 1330 if (is_kdump_kernel()) 1331 return false; 1332 1333 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1334 return false; 1335 1336 return has_cpuid_feature(entry, scope); 1337 } 1338 1339 /* 1340 * This check is triggered during the early boot before the cpufeature 1341 * is initialised. Checking the status on the local CPU allows the boot 1342 * CPU to detect the need for non-global mappings and thus avoiding a 1343 * pagetable re-write after all the CPUs are booted. This check will be 1344 * anyway run on individual CPUs, allowing us to get the consistent 1345 * state once the SMP CPUs are up and thus make the switch to non-global 1346 * mappings if required. 1347 */ 1348 bool kaslr_requires_kpti(void) 1349 { 1350 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1351 return false; 1352 1353 /* 1354 * E0PD does a similar job to KPTI so can be used instead 1355 * where available. 1356 */ 1357 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1358 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1359 if (cpuid_feature_extract_unsigned_field(mmfr2, 1360 ID_AA64MMFR2_E0PD_SHIFT)) 1361 return false; 1362 } 1363 1364 /* 1365 * Systems affected by Cavium erratum 24756 are incompatible 1366 * with KPTI. 1367 */ 1368 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1369 extern const struct midr_range cavium_erratum_27456_cpus[]; 1370 1371 if (is_midr_in_range_list(read_cpuid_id(), 1372 cavium_erratum_27456_cpus)) 1373 return false; 1374 } 1375 1376 return kaslr_offset() > 0; 1377 } 1378 1379 static bool __meltdown_safe = true; 1380 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1381 1382 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1383 int scope) 1384 { 1385 /* List of CPUs that are not vulnerable and don't need KPTI */ 1386 static const struct midr_range kpti_safe_list[] = { 1387 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1388 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1389 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1390 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1391 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1392 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1393 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1394 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1395 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1396 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1397 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1398 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1399 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1400 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1401 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1402 { /* sentinel */ } 1403 }; 1404 char const *str = "kpti command line option"; 1405 bool meltdown_safe; 1406 1407 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1408 1409 /* Defer to CPU feature registers */ 1410 if (has_cpuid_feature(entry, scope)) 1411 meltdown_safe = true; 1412 1413 if (!meltdown_safe) 1414 __meltdown_safe = false; 1415 1416 /* 1417 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1418 * ThunderX leads to apparent I-cache corruption of kernel text, which 1419 * ends as well as you might imagine. Don't even try. 1420 */ 1421 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1422 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1423 __kpti_forced = -1; 1424 } 1425 1426 /* Useful for KASLR robustness */ 1427 if (kaslr_requires_kpti()) { 1428 if (!__kpti_forced) { 1429 str = "KASLR"; 1430 __kpti_forced = 1; 1431 } 1432 } 1433 1434 if (cpu_mitigations_off() && !__kpti_forced) { 1435 str = "mitigations=off"; 1436 __kpti_forced = -1; 1437 } 1438 1439 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1440 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1441 return false; 1442 } 1443 1444 /* Forced? */ 1445 if (__kpti_forced) { 1446 pr_info_once("kernel page table isolation forced %s by %s\n", 1447 __kpti_forced > 0 ? "ON" : "OFF", str); 1448 return __kpti_forced > 0; 1449 } 1450 1451 return !meltdown_safe; 1452 } 1453 1454 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1455 static void __nocfi 1456 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1457 { 1458 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1459 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1460 kpti_remap_fn *remap_fn; 1461 1462 int cpu = smp_processor_id(); 1463 1464 /* 1465 * We don't need to rewrite the page-tables if either we've done 1466 * it already or we have KASLR enabled and therefore have not 1467 * created any global mappings at all. 1468 */ 1469 if (arm64_use_ng_mappings) 1470 return; 1471 1472 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings)); 1473 1474 cpu_install_idmap(); 1475 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1476 cpu_uninstall_idmap(); 1477 1478 if (!cpu) 1479 arm64_use_ng_mappings = true; 1480 1481 return; 1482 } 1483 #else 1484 static void 1485 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1486 { 1487 } 1488 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1489 1490 static int __init parse_kpti(char *str) 1491 { 1492 bool enabled; 1493 int ret = strtobool(str, &enabled); 1494 1495 if (ret) 1496 return ret; 1497 1498 __kpti_forced = enabled ? 1 : -1; 1499 return 0; 1500 } 1501 early_param("kpti", parse_kpti); 1502 1503 #ifdef CONFIG_ARM64_HW_AFDBM 1504 static inline void __cpu_enable_hw_dbm(void) 1505 { 1506 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1507 1508 write_sysreg(tcr, tcr_el1); 1509 isb(); 1510 local_flush_tlb_all(); 1511 } 1512 1513 static bool cpu_has_broken_dbm(void) 1514 { 1515 /* List of CPUs which have broken DBM support. */ 1516 static const struct midr_range cpus[] = { 1517 #ifdef CONFIG_ARM64_ERRATUM_1024718 1518 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1519 /* Kryo4xx Silver (rdpe => r1p0) */ 1520 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1521 #endif 1522 {}, 1523 }; 1524 1525 return is_midr_in_range_list(read_cpuid_id(), cpus); 1526 } 1527 1528 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1529 { 1530 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1531 !cpu_has_broken_dbm(); 1532 } 1533 1534 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1535 { 1536 if (cpu_can_use_dbm(cap)) 1537 __cpu_enable_hw_dbm(); 1538 } 1539 1540 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1541 int __unused) 1542 { 1543 static bool detected = false; 1544 /* 1545 * DBM is a non-conflicting feature. i.e, the kernel can safely 1546 * run a mix of CPUs with and without the feature. So, we 1547 * unconditionally enable the capability to allow any late CPU 1548 * to use the feature. We only enable the control bits on the 1549 * CPU, if it actually supports. 1550 * 1551 * We have to make sure we print the "feature" detection only 1552 * when at least one CPU actually uses it. So check if this CPU 1553 * can actually use it and print the message exactly once. 1554 * 1555 * This is safe as all CPUs (including secondary CPUs - due to the 1556 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1557 * goes through the "matches" check exactly once. Also if a CPU 1558 * matches the criteria, it is guaranteed that the CPU will turn 1559 * the DBM on, as the capability is unconditionally enabled. 1560 */ 1561 if (!detected && cpu_can_use_dbm(cap)) { 1562 detected = true; 1563 pr_info("detected: Hardware dirty bit management\n"); 1564 } 1565 1566 return true; 1567 } 1568 1569 #endif 1570 1571 #ifdef CONFIG_ARM64_AMU_EXTN 1572 1573 /* 1574 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1575 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1576 * information regarding all the events that it supports. When a CPU bit is 1577 * set in the cpumask, the user of this feature can only rely on the presence 1578 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1579 * counters are enabled or access to these counters is enabled by code 1580 * executed at higher exception levels (firmware). 1581 */ 1582 static struct cpumask amu_cpus __read_mostly; 1583 1584 bool cpu_has_amu_feat(int cpu) 1585 { 1586 return cpumask_test_cpu(cpu, &amu_cpus); 1587 } 1588 1589 int get_cpu_with_amu_feat(void) 1590 { 1591 return cpumask_any(&amu_cpus); 1592 } 1593 1594 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1595 { 1596 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1597 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1598 smp_processor_id()); 1599 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1600 update_freq_counters_refs(); 1601 } 1602 } 1603 1604 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1605 int __unused) 1606 { 1607 /* 1608 * The AMU extension is a non-conflicting feature: the kernel can 1609 * safely run a mix of CPUs with and without support for the 1610 * activity monitors extension. Therefore, unconditionally enable 1611 * the capability to allow any late CPU to use the feature. 1612 * 1613 * With this feature unconditionally enabled, the cpu_enable 1614 * function will be called for all CPUs that match the criteria, 1615 * including secondary and hotplugged, marking this feature as 1616 * present on that respective CPU. The enable function will also 1617 * print a detection message. 1618 */ 1619 1620 return true; 1621 } 1622 #else 1623 int get_cpu_with_amu_feat(void) 1624 { 1625 return nr_cpu_ids; 1626 } 1627 #endif 1628 1629 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1630 { 1631 return is_kernel_in_hyp_mode(); 1632 } 1633 1634 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1635 { 1636 /* 1637 * Copy register values that aren't redirected by hardware. 1638 * 1639 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1640 * this value to tpidr_el2 before we patch the code. Once we've done 1641 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1642 * do anything here. 1643 */ 1644 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1645 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1646 } 1647 1648 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1649 { 1650 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1651 1652 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1653 WARN_ON(val & (7 << 27 | 7 << 21)); 1654 } 1655 1656 #ifdef CONFIG_ARM64_PAN 1657 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1658 { 1659 /* 1660 * We modify PSTATE. This won't work from irq context as the PSTATE 1661 * is discarded once we return from the exception. 1662 */ 1663 WARN_ON_ONCE(in_interrupt()); 1664 1665 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1666 set_pstate_pan(1); 1667 } 1668 #endif /* CONFIG_ARM64_PAN */ 1669 1670 #ifdef CONFIG_ARM64_RAS_EXTN 1671 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1672 { 1673 /* Firmware may have left a deferred SError in this register. */ 1674 write_sysreg_s(0, SYS_DISR_EL1); 1675 } 1676 #endif /* CONFIG_ARM64_RAS_EXTN */ 1677 1678 #ifdef CONFIG_ARM64_PTR_AUTH 1679 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1680 { 1681 int boot_val, sec_val; 1682 1683 /* We don't expect to be called with SCOPE_SYSTEM */ 1684 WARN_ON(scope == SCOPE_SYSTEM); 1685 /* 1686 * The ptr-auth feature levels are not intercompatible with lower 1687 * levels. Hence we must match ptr-auth feature level of the secondary 1688 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1689 * from the sanitised register whereas direct register read is done for 1690 * the secondary CPUs. 1691 * The sanitised feature state is guaranteed to match that of the 1692 * boot CPU as a mismatched secondary CPU is parked before it gets 1693 * a chance to update the state, with the capability. 1694 */ 1695 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1696 entry->field_pos, entry->sign); 1697 if (scope & SCOPE_BOOT_CPU) 1698 return boot_val >= entry->min_field_value; 1699 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 1700 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 1701 entry->field_pos, entry->sign); 1702 return sec_val == boot_val; 1703 } 1704 1705 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 1706 int scope) 1707 { 1708 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) || 1709 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 1710 } 1711 1712 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1713 int __unused) 1714 { 1715 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) || 1716 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1717 } 1718 #endif /* CONFIG_ARM64_PTR_AUTH */ 1719 1720 #ifdef CONFIG_ARM64_E0PD 1721 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1722 { 1723 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1724 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1725 } 1726 #endif /* CONFIG_ARM64_E0PD */ 1727 1728 #ifdef CONFIG_ARM64_PSEUDO_NMI 1729 static bool enable_pseudo_nmi; 1730 1731 static int __init early_enable_pseudo_nmi(char *p) 1732 { 1733 return strtobool(p, &enable_pseudo_nmi); 1734 } 1735 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1736 1737 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1738 int scope) 1739 { 1740 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1741 } 1742 #endif 1743 1744 #ifdef CONFIG_ARM64_BTI 1745 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 1746 { 1747 /* 1748 * Use of X16/X17 for tail-calls and trampolines that jump to 1749 * function entry points using BR is a requirement for 1750 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 1751 * So, be strict and forbid other BRs using other registers to 1752 * jump onto a PACIxSP instruction: 1753 */ 1754 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 1755 isb(); 1756 } 1757 #endif /* CONFIG_ARM64_BTI */ 1758 1759 #ifdef CONFIG_ARM64_MTE 1760 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 1761 { 1762 /* 1763 * Clear the tags in the zero page. This needs to be done via the 1764 * linear map which has the Tagged attribute. 1765 */ 1766 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) 1767 mte_clear_page_tags(lm_alias(empty_zero_page)); 1768 1769 kasan_init_hw_tags_cpu(); 1770 } 1771 #endif /* CONFIG_ARM64_MTE */ 1772 1773 #ifdef CONFIG_KVM 1774 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 1775 { 1776 if (kvm_get_mode() != KVM_MODE_PROTECTED) 1777 return false; 1778 1779 if (is_kernel_in_hyp_mode()) { 1780 pr_warn("Protected KVM not available with VHE\n"); 1781 return false; 1782 } 1783 1784 return true; 1785 } 1786 #endif /* CONFIG_KVM */ 1787 1788 /* Internal helper functions to match cpu capability type */ 1789 static bool 1790 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1791 { 1792 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1793 } 1794 1795 static bool 1796 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1797 { 1798 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1799 } 1800 1801 static bool 1802 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 1803 { 1804 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 1805 } 1806 1807 static const struct arm64_cpu_capabilities arm64_features[] = { 1808 { 1809 .desc = "GIC system register CPU interface", 1810 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1811 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1812 .matches = has_useable_gicv3_cpuif, 1813 .sys_reg = SYS_ID_AA64PFR0_EL1, 1814 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1815 .sign = FTR_UNSIGNED, 1816 .min_field_value = 1, 1817 }, 1818 #ifdef CONFIG_ARM64_PAN 1819 { 1820 .desc = "Privileged Access Never", 1821 .capability = ARM64_HAS_PAN, 1822 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1823 .matches = has_cpuid_feature, 1824 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1825 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1826 .sign = FTR_UNSIGNED, 1827 .min_field_value = 1, 1828 .cpu_enable = cpu_enable_pan, 1829 }, 1830 #endif /* CONFIG_ARM64_PAN */ 1831 #ifdef CONFIG_ARM64_EPAN 1832 { 1833 .desc = "Enhanced Privileged Access Never", 1834 .capability = ARM64_HAS_EPAN, 1835 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1836 .matches = has_cpuid_feature, 1837 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1838 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1839 .sign = FTR_UNSIGNED, 1840 .min_field_value = 3, 1841 }, 1842 #endif /* CONFIG_ARM64_EPAN */ 1843 #ifdef CONFIG_ARM64_LSE_ATOMICS 1844 { 1845 .desc = "LSE atomic instructions", 1846 .capability = ARM64_HAS_LSE_ATOMICS, 1847 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1848 .matches = has_cpuid_feature, 1849 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1850 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1851 .sign = FTR_UNSIGNED, 1852 .min_field_value = 2, 1853 }, 1854 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 1855 { 1856 .desc = "Software prefetching using PRFM", 1857 .capability = ARM64_HAS_NO_HW_PREFETCH, 1858 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1859 .matches = has_no_hw_prefetch, 1860 }, 1861 { 1862 .desc = "Virtualization Host Extensions", 1863 .capability = ARM64_HAS_VIRT_HOST_EXTN, 1864 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1865 .matches = runs_at_el2, 1866 .cpu_enable = cpu_copy_el2regs, 1867 }, 1868 { 1869 .desc = "32-bit EL0 Support", 1870 .capability = ARM64_HAS_32BIT_EL0, 1871 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1872 .matches = has_cpuid_feature, 1873 .sys_reg = SYS_ID_AA64PFR0_EL1, 1874 .sign = FTR_UNSIGNED, 1875 .field_pos = ID_AA64PFR0_EL0_SHIFT, 1876 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 1877 }, 1878 #ifdef CONFIG_KVM 1879 { 1880 .desc = "32-bit EL1 Support", 1881 .capability = ARM64_HAS_32BIT_EL1, 1882 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1883 .matches = has_cpuid_feature, 1884 .sys_reg = SYS_ID_AA64PFR0_EL1, 1885 .sign = FTR_UNSIGNED, 1886 .field_pos = ID_AA64PFR0_EL1_SHIFT, 1887 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT, 1888 }, 1889 { 1890 .desc = "Protected KVM", 1891 .capability = ARM64_KVM_PROTECTED_MODE, 1892 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1893 .matches = is_kvm_protected_mode, 1894 }, 1895 #endif 1896 { 1897 .desc = "Kernel page table isolation (KPTI)", 1898 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 1899 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1900 /* 1901 * The ID feature fields below are used to indicate that 1902 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 1903 * more details. 1904 */ 1905 .sys_reg = SYS_ID_AA64PFR0_EL1, 1906 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 1907 .min_field_value = 1, 1908 .matches = unmap_kernel_at_el0, 1909 .cpu_enable = kpti_install_ng_mappings, 1910 }, 1911 { 1912 /* FP/SIMD is not implemented */ 1913 .capability = ARM64_HAS_NO_FPSIMD, 1914 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1915 .min_field_value = 0, 1916 .matches = has_no_fpsimd, 1917 }, 1918 #ifdef CONFIG_ARM64_PMEM 1919 { 1920 .desc = "Data cache clean to Point of Persistence", 1921 .capability = ARM64_HAS_DCPOP, 1922 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1923 .matches = has_cpuid_feature, 1924 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1925 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1926 .min_field_value = 1, 1927 }, 1928 { 1929 .desc = "Data cache clean to Point of Deep Persistence", 1930 .capability = ARM64_HAS_DCPODP, 1931 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1932 .matches = has_cpuid_feature, 1933 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1934 .sign = FTR_UNSIGNED, 1935 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1936 .min_field_value = 2, 1937 }, 1938 #endif 1939 #ifdef CONFIG_ARM64_SVE 1940 { 1941 .desc = "Scalable Vector Extension", 1942 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1943 .capability = ARM64_SVE, 1944 .sys_reg = SYS_ID_AA64PFR0_EL1, 1945 .sign = FTR_UNSIGNED, 1946 .field_pos = ID_AA64PFR0_SVE_SHIFT, 1947 .min_field_value = ID_AA64PFR0_SVE, 1948 .matches = has_cpuid_feature, 1949 .cpu_enable = sve_kernel_enable, 1950 }, 1951 #endif /* CONFIG_ARM64_SVE */ 1952 #ifdef CONFIG_ARM64_RAS_EXTN 1953 { 1954 .desc = "RAS Extension Support", 1955 .capability = ARM64_HAS_RAS_EXTN, 1956 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1957 .matches = has_cpuid_feature, 1958 .sys_reg = SYS_ID_AA64PFR0_EL1, 1959 .sign = FTR_UNSIGNED, 1960 .field_pos = ID_AA64PFR0_RAS_SHIFT, 1961 .min_field_value = ID_AA64PFR0_RAS_V1, 1962 .cpu_enable = cpu_clear_disr, 1963 }, 1964 #endif /* CONFIG_ARM64_RAS_EXTN */ 1965 #ifdef CONFIG_ARM64_AMU_EXTN 1966 { 1967 /* 1968 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 1969 * Therefore, don't provide .desc as we don't want the detection 1970 * message to be shown until at least one CPU is detected to 1971 * support the feature. 1972 */ 1973 .capability = ARM64_HAS_AMU_EXTN, 1974 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1975 .matches = has_amu, 1976 .sys_reg = SYS_ID_AA64PFR0_EL1, 1977 .sign = FTR_UNSIGNED, 1978 .field_pos = ID_AA64PFR0_AMU_SHIFT, 1979 .min_field_value = ID_AA64PFR0_AMU, 1980 .cpu_enable = cpu_amu_enable, 1981 }, 1982 #endif /* CONFIG_ARM64_AMU_EXTN */ 1983 { 1984 .desc = "Data cache clean to the PoU not required for I/D coherence", 1985 .capability = ARM64_HAS_CACHE_IDC, 1986 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1987 .matches = has_cache_idc, 1988 .cpu_enable = cpu_emulate_effective_ctr, 1989 }, 1990 { 1991 .desc = "Instruction cache invalidation not required for I/D coherence", 1992 .capability = ARM64_HAS_CACHE_DIC, 1993 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1994 .matches = has_cache_dic, 1995 }, 1996 { 1997 .desc = "Stage-2 Force Write-Back", 1998 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1999 .capability = ARM64_HAS_STAGE2_FWB, 2000 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2001 .sign = FTR_UNSIGNED, 2002 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 2003 .min_field_value = 1, 2004 .matches = has_cpuid_feature, 2005 .cpu_enable = cpu_has_fwb, 2006 }, 2007 { 2008 .desc = "ARMv8.4 Translation Table Level", 2009 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2010 .capability = ARM64_HAS_ARMv8_4_TTL, 2011 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2012 .sign = FTR_UNSIGNED, 2013 .field_pos = ID_AA64MMFR2_TTL_SHIFT, 2014 .min_field_value = 1, 2015 .matches = has_cpuid_feature, 2016 }, 2017 { 2018 .desc = "TLB range maintenance instructions", 2019 .capability = ARM64_HAS_TLB_RANGE, 2020 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2021 .matches = has_cpuid_feature, 2022 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2023 .field_pos = ID_AA64ISAR0_TLB_SHIFT, 2024 .sign = FTR_UNSIGNED, 2025 .min_field_value = ID_AA64ISAR0_TLB_RANGE, 2026 }, 2027 #ifdef CONFIG_ARM64_HW_AFDBM 2028 { 2029 /* 2030 * Since we turn this on always, we don't want the user to 2031 * think that the feature is available when it may not be. 2032 * So hide the description. 2033 * 2034 * .desc = "Hardware pagetable Dirty Bit Management", 2035 * 2036 */ 2037 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2038 .capability = ARM64_HW_DBM, 2039 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2040 .sign = FTR_UNSIGNED, 2041 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 2042 .min_field_value = 2, 2043 .matches = has_hw_dbm, 2044 .cpu_enable = cpu_enable_hw_dbm, 2045 }, 2046 #endif 2047 { 2048 .desc = "CRC32 instructions", 2049 .capability = ARM64_HAS_CRC32, 2050 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2051 .matches = has_cpuid_feature, 2052 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2053 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 2054 .min_field_value = 1, 2055 }, 2056 { 2057 .desc = "Speculative Store Bypassing Safe (SSBS)", 2058 .capability = ARM64_SSBS, 2059 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2060 .matches = has_cpuid_feature, 2061 .sys_reg = SYS_ID_AA64PFR1_EL1, 2062 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 2063 .sign = FTR_UNSIGNED, 2064 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 2065 }, 2066 #ifdef CONFIG_ARM64_CNP 2067 { 2068 .desc = "Common not Private translations", 2069 .capability = ARM64_HAS_CNP, 2070 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2071 .matches = has_useable_cnp, 2072 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2073 .sign = FTR_UNSIGNED, 2074 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 2075 .min_field_value = 1, 2076 .cpu_enable = cpu_enable_cnp, 2077 }, 2078 #endif 2079 { 2080 .desc = "Speculation barrier (SB)", 2081 .capability = ARM64_HAS_SB, 2082 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2083 .matches = has_cpuid_feature, 2084 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2085 .field_pos = ID_AA64ISAR1_SB_SHIFT, 2086 .sign = FTR_UNSIGNED, 2087 .min_field_value = 1, 2088 }, 2089 #ifdef CONFIG_ARM64_PTR_AUTH 2090 { 2091 .desc = "Address authentication (architected algorithm)", 2092 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 2093 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2094 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2095 .sign = FTR_UNSIGNED, 2096 .field_pos = ID_AA64ISAR1_APA_SHIFT, 2097 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 2098 .matches = has_address_auth_cpucap, 2099 }, 2100 { 2101 .desc = "Address authentication (IMP DEF algorithm)", 2102 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2103 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2104 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2105 .sign = FTR_UNSIGNED, 2106 .field_pos = ID_AA64ISAR1_API_SHIFT, 2107 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 2108 .matches = has_address_auth_cpucap, 2109 }, 2110 { 2111 .capability = ARM64_HAS_ADDRESS_AUTH, 2112 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2113 .matches = has_address_auth_metacap, 2114 }, 2115 { 2116 .desc = "Generic authentication (architected algorithm)", 2117 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 2118 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2119 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2120 .sign = FTR_UNSIGNED, 2121 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 2122 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 2123 .matches = has_cpuid_feature, 2124 }, 2125 { 2126 .desc = "Generic authentication (IMP DEF algorithm)", 2127 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2128 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2129 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2130 .sign = FTR_UNSIGNED, 2131 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 2132 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 2133 .matches = has_cpuid_feature, 2134 }, 2135 { 2136 .capability = ARM64_HAS_GENERIC_AUTH, 2137 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2138 .matches = has_generic_auth, 2139 }, 2140 #endif /* CONFIG_ARM64_PTR_AUTH */ 2141 #ifdef CONFIG_ARM64_PSEUDO_NMI 2142 { 2143 /* 2144 * Depends on having GICv3 2145 */ 2146 .desc = "IRQ priority masking", 2147 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2148 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2149 .matches = can_use_gic_priorities, 2150 .sys_reg = SYS_ID_AA64PFR0_EL1, 2151 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2152 .sign = FTR_UNSIGNED, 2153 .min_field_value = 1, 2154 }, 2155 #endif 2156 #ifdef CONFIG_ARM64_E0PD 2157 { 2158 .desc = "E0PD", 2159 .capability = ARM64_HAS_E0PD, 2160 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2161 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2162 .sign = FTR_UNSIGNED, 2163 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2164 .matches = has_cpuid_feature, 2165 .min_field_value = 1, 2166 .cpu_enable = cpu_enable_e0pd, 2167 }, 2168 #endif 2169 #ifdef CONFIG_ARCH_RANDOM 2170 { 2171 .desc = "Random Number Generator", 2172 .capability = ARM64_HAS_RNG, 2173 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2174 .matches = has_cpuid_feature, 2175 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2176 .field_pos = ID_AA64ISAR0_RNDR_SHIFT, 2177 .sign = FTR_UNSIGNED, 2178 .min_field_value = 1, 2179 }, 2180 #endif 2181 #ifdef CONFIG_ARM64_BTI 2182 { 2183 .desc = "Branch Target Identification", 2184 .capability = ARM64_BTI, 2185 #ifdef CONFIG_ARM64_BTI_KERNEL 2186 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2187 #else 2188 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2189 #endif 2190 .matches = has_cpuid_feature, 2191 .cpu_enable = bti_enable, 2192 .sys_reg = SYS_ID_AA64PFR1_EL1, 2193 .field_pos = ID_AA64PFR1_BT_SHIFT, 2194 .min_field_value = ID_AA64PFR1_BT_BTI, 2195 .sign = FTR_UNSIGNED, 2196 }, 2197 #endif 2198 #ifdef CONFIG_ARM64_MTE 2199 { 2200 .desc = "Memory Tagging Extension", 2201 .capability = ARM64_MTE, 2202 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2203 .matches = has_cpuid_feature, 2204 .sys_reg = SYS_ID_AA64PFR1_EL1, 2205 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2206 .min_field_value = ID_AA64PFR1_MTE, 2207 .sign = FTR_UNSIGNED, 2208 .cpu_enable = cpu_enable_mte, 2209 }, 2210 #endif /* CONFIG_ARM64_MTE */ 2211 { 2212 .desc = "RCpc load-acquire (LDAPR)", 2213 .capability = ARM64_HAS_LDAPR, 2214 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2215 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2216 .sign = FTR_UNSIGNED, 2217 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, 2218 .matches = has_cpuid_feature, 2219 .min_field_value = 1, 2220 }, 2221 {}, 2222 }; 2223 2224 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2225 .matches = has_cpuid_feature, \ 2226 .sys_reg = reg, \ 2227 .field_pos = field, \ 2228 .sign = s, \ 2229 .min_field_value = min_value, 2230 2231 #define __HWCAP_CAP(name, cap_type, cap) \ 2232 .desc = name, \ 2233 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2234 .hwcap_type = cap_type, \ 2235 .hwcap = cap, \ 2236 2237 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 2238 { \ 2239 __HWCAP_CAP(#cap, cap_type, cap) \ 2240 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2241 } 2242 2243 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2244 { \ 2245 __HWCAP_CAP(#cap, cap_type, cap) \ 2246 .matches = cpucap_multi_entry_cap_matches, \ 2247 .match_list = list, \ 2248 } 2249 2250 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2251 { \ 2252 __HWCAP_CAP(#cap, cap_type, cap) \ 2253 .matches = match, \ 2254 } 2255 2256 #ifdef CONFIG_ARM64_PTR_AUTH 2257 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2258 { 2259 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 2260 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 2261 }, 2262 { 2263 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 2264 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 2265 }, 2266 {}, 2267 }; 2268 2269 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2270 { 2271 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 2272 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 2273 }, 2274 { 2275 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 2276 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 2277 }, 2278 {}, 2279 }; 2280 #endif 2281 2282 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2283 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2284 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2285 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2286 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2287 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2288 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2289 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2290 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2291 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2292 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2293 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2294 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2295 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2296 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2297 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2298 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2299 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2300 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2301 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2302 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2303 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2304 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2305 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2306 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2307 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2308 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2309 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2310 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2311 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2312 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2313 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2314 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2315 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2316 #ifdef CONFIG_ARM64_SVE 2317 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2318 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2319 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2320 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2321 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2322 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2323 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2324 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2325 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2326 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2327 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2328 #endif 2329 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2330 #ifdef CONFIG_ARM64_BTI 2331 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2332 #endif 2333 #ifdef CONFIG_ARM64_PTR_AUTH 2334 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2335 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2336 #endif 2337 #ifdef CONFIG_ARM64_MTE 2338 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), 2339 #endif /* CONFIG_ARM64_MTE */ 2340 {}, 2341 }; 2342 2343 #ifdef CONFIG_COMPAT 2344 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2345 { 2346 /* 2347 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2348 * in line with that of arm32 as in vfp_init(). We make sure that the 2349 * check is future proof, by making sure value is non-zero. 2350 */ 2351 u32 mvfr1; 2352 2353 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2354 if (scope == SCOPE_SYSTEM) 2355 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2356 else 2357 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2358 2359 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2360 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2361 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2362 } 2363 #endif 2364 2365 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2366 #ifdef CONFIG_COMPAT 2367 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2368 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2369 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2370 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2371 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2372 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2373 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2374 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2375 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2376 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2377 #endif 2378 {}, 2379 }; 2380 2381 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2382 { 2383 switch (cap->hwcap_type) { 2384 case CAP_HWCAP: 2385 cpu_set_feature(cap->hwcap); 2386 break; 2387 #ifdef CONFIG_COMPAT 2388 case CAP_COMPAT_HWCAP: 2389 compat_elf_hwcap |= (u32)cap->hwcap; 2390 break; 2391 case CAP_COMPAT_HWCAP2: 2392 compat_elf_hwcap2 |= (u32)cap->hwcap; 2393 break; 2394 #endif 2395 default: 2396 WARN_ON(1); 2397 break; 2398 } 2399 } 2400 2401 /* Check if we have a particular HWCAP enabled */ 2402 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2403 { 2404 bool rc; 2405 2406 switch (cap->hwcap_type) { 2407 case CAP_HWCAP: 2408 rc = cpu_have_feature(cap->hwcap); 2409 break; 2410 #ifdef CONFIG_COMPAT 2411 case CAP_COMPAT_HWCAP: 2412 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2413 break; 2414 case CAP_COMPAT_HWCAP2: 2415 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2416 break; 2417 #endif 2418 default: 2419 WARN_ON(1); 2420 rc = false; 2421 } 2422 2423 return rc; 2424 } 2425 2426 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2427 { 2428 /* We support emulation of accesses to CPU ID feature registers */ 2429 cpu_set_named_feature(CPUID); 2430 for (; hwcaps->matches; hwcaps++) 2431 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2432 cap_set_elf_hwcap(hwcaps); 2433 } 2434 2435 static void update_cpu_capabilities(u16 scope_mask) 2436 { 2437 int i; 2438 const struct arm64_cpu_capabilities *caps; 2439 2440 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2441 for (i = 0; i < ARM64_NCAPS; i++) { 2442 caps = cpu_hwcaps_ptrs[i]; 2443 if (!caps || !(caps->type & scope_mask) || 2444 cpus_have_cap(caps->capability) || 2445 !caps->matches(caps, cpucap_default_scope(caps))) 2446 continue; 2447 2448 if (caps->desc) 2449 pr_info("detected: %s\n", caps->desc); 2450 cpus_set_cap(caps->capability); 2451 2452 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2453 set_bit(caps->capability, boot_capabilities); 2454 } 2455 } 2456 2457 /* 2458 * Enable all the available capabilities on this CPU. The capabilities 2459 * with BOOT_CPU scope are handled separately and hence skipped here. 2460 */ 2461 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2462 { 2463 int i; 2464 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2465 2466 for_each_available_cap(i) { 2467 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2468 2469 if (WARN_ON(!cap)) 2470 continue; 2471 2472 if (!(cap->type & non_boot_scope)) 2473 continue; 2474 2475 if (cap->cpu_enable) 2476 cap->cpu_enable(cap); 2477 } 2478 return 0; 2479 } 2480 2481 /* 2482 * Run through the enabled capabilities and enable() it on all active 2483 * CPUs 2484 */ 2485 static void __init enable_cpu_capabilities(u16 scope_mask) 2486 { 2487 int i; 2488 const struct arm64_cpu_capabilities *caps; 2489 bool boot_scope; 2490 2491 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2492 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2493 2494 for (i = 0; i < ARM64_NCAPS; i++) { 2495 unsigned int num; 2496 2497 caps = cpu_hwcaps_ptrs[i]; 2498 if (!caps || !(caps->type & scope_mask)) 2499 continue; 2500 num = caps->capability; 2501 if (!cpus_have_cap(num)) 2502 continue; 2503 2504 /* Ensure cpus_have_const_cap(num) works */ 2505 static_branch_enable(&cpu_hwcap_keys[num]); 2506 2507 if (boot_scope && caps->cpu_enable) 2508 /* 2509 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2510 * before any secondary CPU boots. Thus, each secondary 2511 * will enable the capability as appropriate via 2512 * check_local_cpu_capabilities(). The only exception is 2513 * the boot CPU, for which the capability must be 2514 * enabled here. This approach avoids costly 2515 * stop_machine() calls for this case. 2516 */ 2517 caps->cpu_enable(caps); 2518 } 2519 2520 /* 2521 * For all non-boot scope capabilities, use stop_machine() 2522 * as it schedules the work allowing us to modify PSTATE, 2523 * instead of on_each_cpu() which uses an IPI, giving us a 2524 * PSTATE that disappears when we return. 2525 */ 2526 if (!boot_scope) 2527 stop_machine(cpu_enable_non_boot_scope_capabilities, 2528 NULL, cpu_online_mask); 2529 } 2530 2531 /* 2532 * Run through the list of capabilities to check for conflicts. 2533 * If the system has already detected a capability, take necessary 2534 * action on this CPU. 2535 */ 2536 static void verify_local_cpu_caps(u16 scope_mask) 2537 { 2538 int i; 2539 bool cpu_has_cap, system_has_cap; 2540 const struct arm64_cpu_capabilities *caps; 2541 2542 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2543 2544 for (i = 0; i < ARM64_NCAPS; i++) { 2545 caps = cpu_hwcaps_ptrs[i]; 2546 if (!caps || !(caps->type & scope_mask)) 2547 continue; 2548 2549 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2550 system_has_cap = cpus_have_cap(caps->capability); 2551 2552 if (system_has_cap) { 2553 /* 2554 * Check if the new CPU misses an advertised feature, 2555 * which is not safe to miss. 2556 */ 2557 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2558 break; 2559 /* 2560 * We have to issue cpu_enable() irrespective of 2561 * whether the CPU has it or not, as it is enabeld 2562 * system wide. It is upto the call back to take 2563 * appropriate action on this CPU. 2564 */ 2565 if (caps->cpu_enable) 2566 caps->cpu_enable(caps); 2567 } else { 2568 /* 2569 * Check if the CPU has this capability if it isn't 2570 * safe to have when the system doesn't. 2571 */ 2572 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2573 break; 2574 } 2575 } 2576 2577 if (i < ARM64_NCAPS) { 2578 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2579 smp_processor_id(), caps->capability, 2580 caps->desc, system_has_cap, cpu_has_cap); 2581 2582 if (cpucap_panic_on_conflict(caps)) 2583 cpu_panic_kernel(); 2584 else 2585 cpu_die_early(); 2586 } 2587 } 2588 2589 /* 2590 * Check for CPU features that are used in early boot 2591 * based on the Boot CPU value. 2592 */ 2593 static void check_early_cpu_features(void) 2594 { 2595 verify_cpu_asid_bits(); 2596 2597 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2598 } 2599 2600 static void 2601 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2602 { 2603 2604 for (; caps->matches; caps++) 2605 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2606 pr_crit("CPU%d: missing HWCAP: %s\n", 2607 smp_processor_id(), caps->desc); 2608 cpu_die_early(); 2609 } 2610 } 2611 2612 static void verify_sve_features(void) 2613 { 2614 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2615 u64 zcr = read_zcr_features(); 2616 2617 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2618 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2619 2620 if (len < safe_len || sve_verify_vq_map()) { 2621 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2622 smp_processor_id()); 2623 cpu_die_early(); 2624 } 2625 2626 /* Add checks on other ZCR bits here if necessary */ 2627 } 2628 2629 static void verify_hyp_capabilities(void) 2630 { 2631 u64 safe_mmfr1, mmfr0, mmfr1; 2632 int parange, ipa_max; 2633 unsigned int safe_vmid_bits, vmid_bits; 2634 2635 if (!IS_ENABLED(CONFIG_KVM)) 2636 return; 2637 2638 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 2639 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 2640 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 2641 2642 /* Verify VMID bits */ 2643 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 2644 vmid_bits = get_vmid_bits(mmfr1); 2645 if (vmid_bits < safe_vmid_bits) { 2646 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 2647 cpu_die_early(); 2648 } 2649 2650 /* Verify IPA range */ 2651 parange = cpuid_feature_extract_unsigned_field(mmfr0, 2652 ID_AA64MMFR0_PARANGE_SHIFT); 2653 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 2654 if (ipa_max < get_kvm_ipa_limit()) { 2655 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 2656 cpu_die_early(); 2657 } 2658 } 2659 2660 /* 2661 * Run through the enabled system capabilities and enable() it on this CPU. 2662 * The capabilities were decided based on the available CPUs at the boot time. 2663 * Any new CPU should match the system wide status of the capability. If the 2664 * new CPU doesn't have a capability which the system now has enabled, we 2665 * cannot do anything to fix it up and could cause unexpected failures. So 2666 * we park the CPU. 2667 */ 2668 static void verify_local_cpu_capabilities(void) 2669 { 2670 /* 2671 * The capabilities with SCOPE_BOOT_CPU are checked from 2672 * check_early_cpu_features(), as they need to be verified 2673 * on all secondary CPUs. 2674 */ 2675 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2676 2677 verify_local_elf_hwcaps(arm64_elf_hwcaps); 2678 2679 if (system_supports_32bit_el0()) 2680 verify_local_elf_hwcaps(compat_elf_hwcaps); 2681 2682 if (system_supports_sve()) 2683 verify_sve_features(); 2684 2685 if (is_hyp_mode_available()) 2686 verify_hyp_capabilities(); 2687 } 2688 2689 void check_local_cpu_capabilities(void) 2690 { 2691 /* 2692 * All secondary CPUs should conform to the early CPU features 2693 * in use by the kernel based on boot CPU. 2694 */ 2695 check_early_cpu_features(); 2696 2697 /* 2698 * If we haven't finalised the system capabilities, this CPU gets 2699 * a chance to update the errata work arounds and local features. 2700 * Otherwise, this CPU should verify that it has all the system 2701 * advertised capabilities. 2702 */ 2703 if (!system_capabilities_finalized()) 2704 update_cpu_capabilities(SCOPE_LOCAL_CPU); 2705 else 2706 verify_local_cpu_capabilities(); 2707 } 2708 2709 static void __init setup_boot_cpu_capabilities(void) 2710 { 2711 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 2712 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 2713 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 2714 enable_cpu_capabilities(SCOPE_BOOT_CPU); 2715 } 2716 2717 bool this_cpu_has_cap(unsigned int n) 2718 { 2719 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 2720 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2721 2722 if (cap) 2723 return cap->matches(cap, SCOPE_LOCAL_CPU); 2724 } 2725 2726 return false; 2727 } 2728 2729 /* 2730 * This helper function is used in a narrow window when, 2731 * - The system wide safe registers are set with all the SMP CPUs and, 2732 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 2733 * In all other cases cpus_have_{const_}cap() should be used. 2734 */ 2735 static bool __maybe_unused __system_matches_cap(unsigned int n) 2736 { 2737 if (n < ARM64_NCAPS) { 2738 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2739 2740 if (cap) 2741 return cap->matches(cap, SCOPE_SYSTEM); 2742 } 2743 return false; 2744 } 2745 2746 void cpu_set_feature(unsigned int num) 2747 { 2748 WARN_ON(num >= MAX_CPU_FEATURES); 2749 elf_hwcap |= BIT(num); 2750 } 2751 EXPORT_SYMBOL_GPL(cpu_set_feature); 2752 2753 bool cpu_have_feature(unsigned int num) 2754 { 2755 WARN_ON(num >= MAX_CPU_FEATURES); 2756 return elf_hwcap & BIT(num); 2757 } 2758 EXPORT_SYMBOL_GPL(cpu_have_feature); 2759 2760 unsigned long cpu_get_elf_hwcap(void) 2761 { 2762 /* 2763 * We currently only populate the first 32 bits of AT_HWCAP. Please 2764 * note that for userspace compatibility we guarantee that bits 62 2765 * and 63 will always be returned as 0. 2766 */ 2767 return lower_32_bits(elf_hwcap); 2768 } 2769 2770 unsigned long cpu_get_elf_hwcap2(void) 2771 { 2772 return upper_32_bits(elf_hwcap); 2773 } 2774 2775 static void __init setup_system_capabilities(void) 2776 { 2777 /* 2778 * We have finalised the system-wide safe feature 2779 * registers, finalise the capabilities that depend 2780 * on it. Also enable all the available capabilities, 2781 * that are not enabled already. 2782 */ 2783 update_cpu_capabilities(SCOPE_SYSTEM); 2784 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2785 } 2786 2787 void __init setup_cpu_features(void) 2788 { 2789 u32 cwg; 2790 2791 setup_system_capabilities(); 2792 setup_elf_hwcaps(arm64_elf_hwcaps); 2793 2794 if (system_supports_32bit_el0()) 2795 setup_elf_hwcaps(compat_elf_hwcaps); 2796 2797 if (system_uses_ttbr0_pan()) 2798 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2799 2800 sve_setup(); 2801 minsigstksz_setup(); 2802 2803 /* Advertise that we have computed the system capabilities */ 2804 finalize_system_capabilities(); 2805 2806 /* 2807 * Check for sane CTR_EL0.CWG value. 2808 */ 2809 cwg = cache_type_cwg(); 2810 if (!cwg) 2811 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2812 ARCH_DMA_MINALIGN); 2813 } 2814 2815 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 2816 { 2817 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 2818 } 2819 2820 /* 2821 * We emulate only the following system register space. 2822 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 2823 * See Table C5-6 System instruction encodings for System register accesses, 2824 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 2825 */ 2826 static inline bool __attribute_const__ is_emulated(u32 id) 2827 { 2828 return (sys_reg_Op0(id) == 0x3 && 2829 sys_reg_CRn(id) == 0x0 && 2830 sys_reg_Op1(id) == 0x0 && 2831 (sys_reg_CRm(id) == 0 || 2832 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 2833 } 2834 2835 /* 2836 * With CRm == 0, reg should be one of : 2837 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 2838 */ 2839 static inline int emulate_id_reg(u32 id, u64 *valp) 2840 { 2841 switch (id) { 2842 case SYS_MIDR_EL1: 2843 *valp = read_cpuid_id(); 2844 break; 2845 case SYS_MPIDR_EL1: 2846 *valp = SYS_MPIDR_SAFE_VAL; 2847 break; 2848 case SYS_REVIDR_EL1: 2849 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 2850 *valp = 0; 2851 break; 2852 default: 2853 return -EINVAL; 2854 } 2855 2856 return 0; 2857 } 2858 2859 static int emulate_sys_reg(u32 id, u64 *valp) 2860 { 2861 struct arm64_ftr_reg *regp; 2862 2863 if (!is_emulated(id)) 2864 return -EINVAL; 2865 2866 if (sys_reg_CRm(id) == 0) 2867 return emulate_id_reg(id, valp); 2868 2869 regp = get_arm64_ftr_reg_nowarn(id); 2870 if (regp) 2871 *valp = arm64_ftr_reg_user_value(regp); 2872 else 2873 /* 2874 * The untracked registers are either IMPLEMENTATION DEFINED 2875 * (e.g, ID_AFR0_EL1) or reserved RAZ. 2876 */ 2877 *valp = 0; 2878 return 0; 2879 } 2880 2881 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 2882 { 2883 int rc; 2884 u64 val; 2885 2886 rc = emulate_sys_reg(sys_reg, &val); 2887 if (!rc) { 2888 pt_regs_write_reg(regs, rt, val); 2889 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 2890 } 2891 return rc; 2892 } 2893 2894 static int emulate_mrs(struct pt_regs *regs, u32 insn) 2895 { 2896 u32 sys_reg, rt; 2897 2898 /* 2899 * sys_reg values are defined as used in mrs/msr instruction. 2900 * shift the imm value to get the encoding. 2901 */ 2902 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 2903 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 2904 return do_emulate_mrs(regs, sys_reg, rt); 2905 } 2906 2907 static struct undef_hook mrs_hook = { 2908 .instr_mask = 0xfff00000, 2909 .instr_val = 0xd5300000, 2910 .pstate_mask = PSR_AA32_MODE_MASK, 2911 .pstate_val = PSR_MODE_EL0t, 2912 .fn = emulate_mrs, 2913 }; 2914 2915 static int __init enable_mrs_emulation(void) 2916 { 2917 register_undef_hook(&mrs_hook); 2918 return 0; 2919 } 2920 2921 core_initcall(enable_mrs_emulation); 2922 2923 enum mitigation_state arm64_get_meltdown_state(void) 2924 { 2925 if (__meltdown_safe) 2926 return SPECTRE_UNAFFECTED; 2927 2928 if (arm64_kernel_unmapped_at_el0()) 2929 return SPECTRE_MITIGATED; 2930 2931 return SPECTRE_VULNERABLE; 2932 } 2933 2934 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 2935 char *buf) 2936 { 2937 switch (arm64_get_meltdown_state()) { 2938 case SPECTRE_UNAFFECTED: 2939 return sprintf(buf, "Not affected\n"); 2940 2941 case SPECTRE_MITIGATED: 2942 return sprintf(buf, "Mitigation: PTI\n"); 2943 2944 default: 2945 return sprintf(buf, "Vulnerable\n"); 2946 } 2947 } 2948