1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/types.h> 71 #include <linux/mm.h> 72 #include <linux/cpu.h> 73 #include <linux/kasan.h> 74 #include <asm/cpu.h> 75 #include <asm/cpufeature.h> 76 #include <asm/cpu_ops.h> 77 #include <asm/fpsimd.h> 78 #include <asm/kvm_host.h> 79 #include <asm/mmu_context.h> 80 #include <asm/mte.h> 81 #include <asm/processor.h> 82 #include <asm/sysreg.h> 83 #include <asm/traps.h> 84 #include <asm/virt.h> 85 86 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 87 static unsigned long elf_hwcap __read_mostly; 88 89 #ifdef CONFIG_COMPAT 90 #define COMPAT_ELF_HWCAP_DEFAULT \ 91 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 92 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 93 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 94 COMPAT_HWCAP_LPAE) 95 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 96 unsigned int compat_elf_hwcap2 __read_mostly; 97 #endif 98 99 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 100 EXPORT_SYMBOL(cpu_hwcaps); 101 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 102 103 /* Need also bit for ARM64_CB_PATCH */ 104 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 105 106 bool arm64_use_ng_mappings = false; 107 EXPORT_SYMBOL(arm64_use_ng_mappings); 108 109 /* 110 * Flag to indicate if we have computed the system wide 111 * capabilities based on the boot time active CPUs. This 112 * will be used to determine if a new booting CPU should 113 * go through the verification process to make sure that it 114 * supports the system capabilities, without using a hotplug 115 * notifier. This is also used to decide if we could use 116 * the fast path for checking constant CPU caps. 117 */ 118 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 119 EXPORT_SYMBOL(arm64_const_caps_ready); 120 static inline void finalize_system_capabilities(void) 121 { 122 static_branch_enable(&arm64_const_caps_ready); 123 } 124 125 void dump_cpu_features(void) 126 { 127 /* file-wide pr_fmt adds "CPU features: " prefix */ 128 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 129 } 130 131 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 132 EXPORT_SYMBOL(cpu_hwcap_keys); 133 134 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 135 { \ 136 .sign = SIGNED, \ 137 .visible = VISIBLE, \ 138 .strict = STRICT, \ 139 .type = TYPE, \ 140 .shift = SHIFT, \ 141 .width = WIDTH, \ 142 .safe_val = SAFE_VAL, \ 143 } 144 145 /* Define a feature with unsigned values */ 146 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 147 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 148 149 /* Define a feature with a signed value */ 150 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 151 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 152 153 #define ARM64_FTR_END \ 154 { \ 155 .width = 0, \ 156 } 157 158 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 159 160 static bool __system_matches_cap(unsigned int n); 161 162 /* 163 * NOTE: Any changes to the visibility of features should be kept in 164 * sync with the documentation of the CPU feature register ABI. 165 */ 166 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 167 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), 168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0), 169 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 170 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 171 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 172 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 173 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 174 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 175 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 176 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 181 ARM64_FTR_END, 182 }; 183 184 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 192 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 194 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 199 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), 200 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 201 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 203 ARM64_FTR_END, 204 }; 205 206 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 208 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 214 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 217 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 218 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 219 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 223 ARM64_FTR_END, 224 }; 225 226 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 230 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 232 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 233 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 234 ARM64_FTR_END, 235 }; 236 237 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 238 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 239 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 241 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 243 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 245 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 247 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 249 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 256 ARM64_FTR_END, 257 }; 258 259 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), 263 /* 264 * Page size not being supported at Stage-2 is not fatal. You 265 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 266 * your favourite nesting hypervisor. 267 * 268 * There is a small corner case where the hypervisor explicitly 269 * advertises a given granule size at Stage-2 (value 2) on some 270 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 271 * vCPUs. Although this is not forbidden by the architecture, it 272 * indicates that the hypervisor is being silly (or buggy). 273 * 274 * We make no effort to cope with this and pretend that if these 275 * fields are inconsistent across vCPUs, then it isn't worth 276 * trying to bring KVM up. 277 */ 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 281 /* 282 * We already refuse to boot CPUs that don't support our configured 283 * page size, so we can only detect mismatches for a page size other 284 * than the one we're currently using. Unfortunately, SoCs like this 285 * exist in the wild so, even though we don't like it, we'll have to go 286 * along with it and treat them as non-strict. 287 */ 288 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 289 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 291 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 293 /* Linux shouldn't care about secure memory */ 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 297 /* 298 * Differing PARange is fine as long as all peripherals and memory are mapped 299 * within the minimum PARange of all CPUs 300 */ 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 302 ARM64_FTR_END, 303 }; 304 305 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), 310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 316 ARM64_FTR_END, 317 }; 318 319 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0), 329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 335 ARM64_FTR_END, 336 }; 337 338 static const struct arm64_ftr_bits ftr_ctr[] = { 339 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 340 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 341 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 342 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 345 /* 346 * Linux can handle differing I-cache policies. Userspace JITs will 347 * make use of *minLine. 348 * If we have differing I-cache policies, report it as the weakest - VIPT. 349 */ 350 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 351 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 352 ARM64_FTR_END, 353 }; 354 355 static struct arm64_ftr_override __ro_after_init no_override = { }; 356 357 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 358 .name = "SYS_CTR_EL0", 359 .ftr_bits = ftr_ctr, 360 .override = &no_override, 361 }; 362 363 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 364 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 369 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 372 ARM64_FTR_END, 373 }; 374 375 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 376 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 381 /* 382 * We can instantiate multiple PMU instances with different levels 383 * of support. 384 */ 385 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 387 ARM64_FTR_END, 388 }; 389 390 static const struct arm64_ftr_bits ftr_mvfr2[] = { 391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 393 ARM64_FTR_END, 394 }; 395 396 static const struct arm64_ftr_bits ftr_dczid[] = { 397 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), 398 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), 399 ARM64_FTR_END, 400 }; 401 402 static const struct arm64_ftr_bits ftr_id_isar0[] = { 403 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 410 ARM64_FTR_END, 411 }; 412 413 static const struct arm64_ftr_bits ftr_id_isar5[] = { 414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 417 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 419 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 420 ARM64_FTR_END, 421 }; 422 423 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 431 432 /* 433 * SpecSEI = 1 indicates that the PE might generate an SError on an 434 * external abort on speculative read. It is safe to assume that an 435 * SError might be generated than it will not be. Hence it has been 436 * classified as FTR_HIGHER_SAFE. 437 */ 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 439 ARM64_FTR_END, 440 }; 441 442 static const struct arm64_ftr_bits ftr_id_isar4[] = { 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 451 ARM64_FTR_END, 452 }; 453 454 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 456 ARM64_FTR_END, 457 }; 458 459 static const struct arm64_ftr_bits ftr_id_isar6[] = { 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 467 ARM64_FTR_END, 468 }; 469 470 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 477 ARM64_FTR_END, 478 }; 479 480 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 489 ARM64_FTR_END, 490 }; 491 492 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 495 ARM64_FTR_END, 496 }; 497 498 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 499 /* [31:28] TraceFilt */ 500 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 507 ARM64_FTR_END, 508 }; 509 510 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 511 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 512 ARM64_FTR_END, 513 }; 514 515 static const struct arm64_ftr_bits ftr_zcr[] = { 516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 517 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 518 ARM64_FTR_END, 519 }; 520 521 /* 522 * Common ftr bits for a 32bit register with all hidden, strict 523 * attributes, with 4bit feature fields and a default safe value of 524 * 0. Covers the following 32bit registers: 525 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 526 */ 527 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 536 ARM64_FTR_END, 537 }; 538 539 /* Table for a single 32bit feature value */ 540 static const struct arm64_ftr_bits ftr_single32[] = { 541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 542 ARM64_FTR_END, 543 }; 544 545 static const struct arm64_ftr_bits ftr_raz[] = { 546 ARM64_FTR_END, 547 }; 548 549 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) { \ 550 .sys_id = id, \ 551 .reg = &(struct arm64_ftr_reg){ \ 552 .name = #id, \ 553 .override = (ovr), \ 554 .ftr_bits = &((table)[0]), \ 555 }} 556 557 #define ARM64_FTR_REG(id, table) ARM64_FTR_REG_OVERRIDE(id, table, &no_override) 558 559 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 560 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 561 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 562 563 static const struct __ftr_reg_entry { 564 u32 sys_id; 565 struct arm64_ftr_reg *reg; 566 } arm64_ftr_regs[] = { 567 568 /* Op1 = 0, CRn = 0, CRm = 1 */ 569 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 570 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 571 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 572 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 573 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 574 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 575 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 576 577 /* Op1 = 0, CRn = 0, CRm = 2 */ 578 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 579 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 580 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 581 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 582 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 583 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 584 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 585 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 586 587 /* Op1 = 0, CRn = 0, CRm = 3 */ 588 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 589 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 590 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 591 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 592 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 593 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 594 595 /* Op1 = 0, CRn = 0, CRm = 4 */ 596 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 597 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 598 &id_aa64pfr1_override), 599 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 600 601 /* Op1 = 0, CRn = 0, CRm = 5 */ 602 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 603 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 604 605 /* Op1 = 0, CRn = 0, CRm = 6 */ 606 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 607 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 608 &id_aa64isar1_override), 609 610 /* Op1 = 0, CRn = 0, CRm = 7 */ 611 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 612 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 613 &id_aa64mmfr1_override), 614 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 615 616 /* Op1 = 0, CRn = 1, CRm = 2 */ 617 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 618 619 /* Op1 = 3, CRn = 0, CRm = 0 */ 620 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 621 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 622 623 /* Op1 = 3, CRn = 14, CRm = 0 */ 624 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 625 }; 626 627 static int search_cmp_ftr_reg(const void *id, const void *regp) 628 { 629 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 630 } 631 632 /* 633 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 634 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 635 * ascending order of sys_id, we use binary search to find a matching 636 * entry. 637 * 638 * returns - Upon success, matching ftr_reg entry for id. 639 * - NULL on failure. It is upto the caller to decide 640 * the impact of a failure. 641 */ 642 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 643 { 644 const struct __ftr_reg_entry *ret; 645 646 ret = bsearch((const void *)(unsigned long)sys_id, 647 arm64_ftr_regs, 648 ARRAY_SIZE(arm64_ftr_regs), 649 sizeof(arm64_ftr_regs[0]), 650 search_cmp_ftr_reg); 651 if (ret) 652 return ret->reg; 653 return NULL; 654 } 655 656 /* 657 * get_arm64_ftr_reg - Looks up a feature register entry using 658 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 659 * 660 * returns - Upon success, matching ftr_reg entry for id. 661 * - NULL on failure but with an WARN_ON(). 662 */ 663 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 664 { 665 struct arm64_ftr_reg *reg; 666 667 reg = get_arm64_ftr_reg_nowarn(sys_id); 668 669 /* 670 * Requesting a non-existent register search is an error. Warn 671 * and let the caller handle it. 672 */ 673 WARN_ON(!reg); 674 return reg; 675 } 676 677 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 678 s64 ftr_val) 679 { 680 u64 mask = arm64_ftr_mask(ftrp); 681 682 reg &= ~mask; 683 reg |= (ftr_val << ftrp->shift) & mask; 684 return reg; 685 } 686 687 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 688 s64 cur) 689 { 690 s64 ret = 0; 691 692 switch (ftrp->type) { 693 case FTR_EXACT: 694 ret = ftrp->safe_val; 695 break; 696 case FTR_LOWER_SAFE: 697 ret = new < cur ? new : cur; 698 break; 699 case FTR_HIGHER_OR_ZERO_SAFE: 700 if (!cur || !new) 701 break; 702 fallthrough; 703 case FTR_HIGHER_SAFE: 704 ret = new > cur ? new : cur; 705 break; 706 default: 707 BUG(); 708 } 709 710 return ret; 711 } 712 713 static void __init sort_ftr_regs(void) 714 { 715 unsigned int i; 716 717 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 718 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 719 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 720 unsigned int j = 0; 721 722 /* 723 * Features here must be sorted in descending order with respect 724 * to their shift values and should not overlap with each other. 725 */ 726 for (; ftr_bits->width != 0; ftr_bits++, j++) { 727 unsigned int width = ftr_reg->ftr_bits[j].width; 728 unsigned int shift = ftr_reg->ftr_bits[j].shift; 729 unsigned int prev_shift; 730 731 WARN((shift + width) > 64, 732 "%s has invalid feature at shift %d\n", 733 ftr_reg->name, shift); 734 735 /* 736 * Skip the first feature. There is nothing to 737 * compare against for now. 738 */ 739 if (j == 0) 740 continue; 741 742 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 743 WARN((shift + width) > prev_shift, 744 "%s has feature overlap at shift %d\n", 745 ftr_reg->name, shift); 746 } 747 748 /* 749 * Skip the first register. There is nothing to 750 * compare against for now. 751 */ 752 if (i == 0) 753 continue; 754 /* 755 * Registers here must be sorted in ascending order with respect 756 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 757 * to work correctly. 758 */ 759 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 760 } 761 } 762 763 /* 764 * Initialise the CPU feature register from Boot CPU values. 765 * Also initiliases the strict_mask for the register. 766 * Any bits that are not covered by an arm64_ftr_bits entry are considered 767 * RES0 for the system-wide value, and must strictly match. 768 */ 769 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 770 { 771 u64 val = 0; 772 u64 strict_mask = ~0x0ULL; 773 u64 user_mask = 0; 774 u64 valid_mask = 0; 775 776 const struct arm64_ftr_bits *ftrp; 777 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 778 779 if (!reg) 780 return; 781 782 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 783 u64 ftr_mask = arm64_ftr_mask(ftrp); 784 s64 ftr_new = arm64_ftr_value(ftrp, new); 785 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 786 787 if ((ftr_mask & reg->override->mask) == ftr_mask) { 788 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 789 char *str = NULL; 790 791 if (ftr_ovr != tmp) { 792 /* Unsafe, remove the override */ 793 reg->override->mask &= ~ftr_mask; 794 reg->override->val &= ~ftr_mask; 795 tmp = ftr_ovr; 796 str = "ignoring override"; 797 } else if (ftr_new != tmp) { 798 /* Override was valid */ 799 ftr_new = tmp; 800 str = "forced"; 801 } else if (ftr_ovr == tmp) { 802 /* Override was the safe value */ 803 str = "already set"; 804 } 805 806 if (str) 807 pr_warn("%s[%d:%d]: %s to %llx\n", 808 reg->name, 809 ftrp->shift + ftrp->width - 1, 810 ftrp->shift, str, tmp); 811 } 812 813 val = arm64_ftr_set_value(ftrp, val, ftr_new); 814 815 valid_mask |= ftr_mask; 816 if (!ftrp->strict) 817 strict_mask &= ~ftr_mask; 818 if (ftrp->visible) 819 user_mask |= ftr_mask; 820 else 821 reg->user_val = arm64_ftr_set_value(ftrp, 822 reg->user_val, 823 ftrp->safe_val); 824 } 825 826 val &= valid_mask; 827 828 reg->sys_val = val; 829 reg->strict_mask = strict_mask; 830 reg->user_mask = user_mask; 831 } 832 833 extern const struct arm64_cpu_capabilities arm64_errata[]; 834 static const struct arm64_cpu_capabilities arm64_features[]; 835 836 static void __init 837 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 838 { 839 for (; caps->matches; caps++) { 840 if (WARN(caps->capability >= ARM64_NCAPS, 841 "Invalid capability %d\n", caps->capability)) 842 continue; 843 if (WARN(cpu_hwcaps_ptrs[caps->capability], 844 "Duplicate entry for capability %d\n", 845 caps->capability)) 846 continue; 847 cpu_hwcaps_ptrs[caps->capability] = caps; 848 } 849 } 850 851 static void __init init_cpu_hwcaps_indirect_list(void) 852 { 853 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 854 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 855 } 856 857 static void __init setup_boot_cpu_capabilities(void); 858 859 void __init init_cpu_features(struct cpuinfo_arm64 *info) 860 { 861 /* Before we start using the tables, make sure it is sorted */ 862 sort_ftr_regs(); 863 864 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 865 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 866 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 867 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 868 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 869 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 870 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 871 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 872 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 873 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 874 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 875 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 876 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 877 878 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 879 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 880 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 881 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 882 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 883 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 884 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 885 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 886 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 887 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 888 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 889 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 890 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 891 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 892 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 893 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 894 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 895 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 896 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 897 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 898 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 899 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 900 } 901 902 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 903 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 904 sve_init_vq_map(); 905 } 906 907 /* 908 * Initialize the indirect array of CPU hwcaps capabilities pointers 909 * before we handle the boot CPU below. 910 */ 911 init_cpu_hwcaps_indirect_list(); 912 913 /* 914 * Detect and enable early CPU capabilities based on the boot CPU, 915 * after we have initialised the CPU feature infrastructure. 916 */ 917 setup_boot_cpu_capabilities(); 918 } 919 920 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 921 { 922 const struct arm64_ftr_bits *ftrp; 923 924 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 925 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 926 s64 ftr_new = arm64_ftr_value(ftrp, new); 927 928 if (ftr_cur == ftr_new) 929 continue; 930 /* Find a safe value */ 931 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 932 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 933 } 934 935 } 936 937 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 938 { 939 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 940 941 if (!regp) 942 return 0; 943 944 update_cpu_ftr_reg(regp, val); 945 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 946 return 0; 947 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 948 regp->name, boot, cpu, val); 949 return 1; 950 } 951 952 static void relax_cpu_ftr_reg(u32 sys_id, int field) 953 { 954 const struct arm64_ftr_bits *ftrp; 955 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 956 957 if (!regp) 958 return; 959 960 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 961 if (ftrp->shift == field) { 962 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 963 break; 964 } 965 } 966 967 /* Bogus field? */ 968 WARN_ON(!ftrp->width); 969 } 970 971 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info, 972 struct cpuinfo_arm64 *boot) 973 { 974 int taint = 0; 975 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 976 977 /* 978 * If we don't have AArch32 at all then skip the checks entirely 979 * as the register values may be UNKNOWN and we're not going to be 980 * using them for anything. 981 */ 982 if (!id_aa64pfr0_32bit_el0(pfr0)) 983 return taint; 984 985 /* 986 * If we don't have AArch32 at EL1, then relax the strictness of 987 * EL1-dependent register fields to avoid spurious sanity check fails. 988 */ 989 if (!id_aa64pfr0_32bit_el1(pfr0)) { 990 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 991 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 992 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 993 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 994 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 995 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 996 } 997 998 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 999 info->reg_id_dfr0, boot->reg_id_dfr0); 1000 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1001 info->reg_id_dfr1, boot->reg_id_dfr1); 1002 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1003 info->reg_id_isar0, boot->reg_id_isar0); 1004 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1005 info->reg_id_isar1, boot->reg_id_isar1); 1006 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1007 info->reg_id_isar2, boot->reg_id_isar2); 1008 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1009 info->reg_id_isar3, boot->reg_id_isar3); 1010 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1011 info->reg_id_isar4, boot->reg_id_isar4); 1012 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1013 info->reg_id_isar5, boot->reg_id_isar5); 1014 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1015 info->reg_id_isar6, boot->reg_id_isar6); 1016 1017 /* 1018 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1019 * ACTLR formats could differ across CPUs and therefore would have to 1020 * be trapped for virtualization anyway. 1021 */ 1022 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1023 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1024 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1025 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1026 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1027 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1028 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1029 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1030 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1031 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1032 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1033 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1034 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1035 info->reg_id_pfr0, boot->reg_id_pfr0); 1036 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1037 info->reg_id_pfr1, boot->reg_id_pfr1); 1038 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1039 info->reg_id_pfr2, boot->reg_id_pfr2); 1040 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1041 info->reg_mvfr0, boot->reg_mvfr0); 1042 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1043 info->reg_mvfr1, boot->reg_mvfr1); 1044 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1045 info->reg_mvfr2, boot->reg_mvfr2); 1046 1047 return taint; 1048 } 1049 1050 /* 1051 * Update system wide CPU feature registers with the values from a 1052 * non-boot CPU. Also performs SANITY checks to make sure that there 1053 * aren't any insane variations from that of the boot CPU. 1054 */ 1055 void update_cpu_features(int cpu, 1056 struct cpuinfo_arm64 *info, 1057 struct cpuinfo_arm64 *boot) 1058 { 1059 int taint = 0; 1060 1061 /* 1062 * The kernel can handle differing I-cache policies, but otherwise 1063 * caches should look identical. Userspace JITs will make use of 1064 * *minLine. 1065 */ 1066 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1067 info->reg_ctr, boot->reg_ctr); 1068 1069 /* 1070 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1071 * could result in too much or too little memory being zeroed if a 1072 * process is preempted and migrated between CPUs. 1073 */ 1074 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1075 info->reg_dczid, boot->reg_dczid); 1076 1077 /* If different, timekeeping will be broken (especially with KVM) */ 1078 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1079 info->reg_cntfrq, boot->reg_cntfrq); 1080 1081 /* 1082 * The kernel uses self-hosted debug features and expects CPUs to 1083 * support identical debug features. We presently need CTX_CMPs, WRPs, 1084 * and BRPs to be identical. 1085 * ID_AA64DFR1 is currently RES0. 1086 */ 1087 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1088 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1089 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1090 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1091 /* 1092 * Even in big.LITTLE, processors should be identical instruction-set 1093 * wise. 1094 */ 1095 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1096 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1097 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1098 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1099 1100 /* 1101 * Differing PARange support is fine as long as all peripherals and 1102 * memory are mapped within the minimum PARange of all CPUs. 1103 * Linux should not care about secure memory. 1104 */ 1105 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1106 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1107 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1108 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1109 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1110 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1111 1112 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1113 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1114 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1115 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1116 1117 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1118 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1119 1120 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 1121 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1122 info->reg_zcr, boot->reg_zcr); 1123 1124 /* Probe vector lengths, unless we already gave up on SVE */ 1125 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 1126 !system_capabilities_finalized()) 1127 sve_update_vq_map(); 1128 } 1129 1130 /* 1131 * This relies on a sanitised view of the AArch64 ID registers 1132 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1133 */ 1134 taint |= update_32bit_cpu_features(cpu, info, boot); 1135 1136 /* 1137 * Mismatched CPU features are a recipe for disaster. Don't even 1138 * pretend to support them. 1139 */ 1140 if (taint) { 1141 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1142 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1143 } 1144 } 1145 1146 u64 read_sanitised_ftr_reg(u32 id) 1147 { 1148 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1149 1150 if (!regp) 1151 return 0; 1152 return regp->sys_val; 1153 } 1154 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1155 1156 #define read_sysreg_case(r) \ 1157 case r: val = read_sysreg_s(r); break; 1158 1159 /* 1160 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1161 * Read the system register on the current CPU 1162 */ 1163 u64 __read_sysreg_by_encoding(u32 sys_id) 1164 { 1165 struct arm64_ftr_reg *regp; 1166 u64 val; 1167 1168 switch (sys_id) { 1169 read_sysreg_case(SYS_ID_PFR0_EL1); 1170 read_sysreg_case(SYS_ID_PFR1_EL1); 1171 read_sysreg_case(SYS_ID_PFR2_EL1); 1172 read_sysreg_case(SYS_ID_DFR0_EL1); 1173 read_sysreg_case(SYS_ID_DFR1_EL1); 1174 read_sysreg_case(SYS_ID_MMFR0_EL1); 1175 read_sysreg_case(SYS_ID_MMFR1_EL1); 1176 read_sysreg_case(SYS_ID_MMFR2_EL1); 1177 read_sysreg_case(SYS_ID_MMFR3_EL1); 1178 read_sysreg_case(SYS_ID_MMFR4_EL1); 1179 read_sysreg_case(SYS_ID_MMFR5_EL1); 1180 read_sysreg_case(SYS_ID_ISAR0_EL1); 1181 read_sysreg_case(SYS_ID_ISAR1_EL1); 1182 read_sysreg_case(SYS_ID_ISAR2_EL1); 1183 read_sysreg_case(SYS_ID_ISAR3_EL1); 1184 read_sysreg_case(SYS_ID_ISAR4_EL1); 1185 read_sysreg_case(SYS_ID_ISAR5_EL1); 1186 read_sysreg_case(SYS_ID_ISAR6_EL1); 1187 read_sysreg_case(SYS_MVFR0_EL1); 1188 read_sysreg_case(SYS_MVFR1_EL1); 1189 read_sysreg_case(SYS_MVFR2_EL1); 1190 1191 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1192 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1193 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1194 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1195 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1196 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1197 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1198 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1199 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1200 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1201 1202 read_sysreg_case(SYS_CNTFRQ_EL0); 1203 read_sysreg_case(SYS_CTR_EL0); 1204 read_sysreg_case(SYS_DCZID_EL0); 1205 1206 default: 1207 BUG(); 1208 return 0; 1209 } 1210 1211 regp = get_arm64_ftr_reg(sys_id); 1212 if (regp) { 1213 val &= ~regp->override->mask; 1214 val |= (regp->override->val & regp->override->mask); 1215 } 1216 1217 return val; 1218 } 1219 1220 #include <linux/irqchip/arm-gic-v3.h> 1221 1222 static bool 1223 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1224 { 1225 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 1226 1227 return val >= entry->min_field_value; 1228 } 1229 1230 static bool 1231 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1232 { 1233 u64 val; 1234 1235 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1236 if (scope == SCOPE_SYSTEM) 1237 val = read_sanitised_ftr_reg(entry->sys_reg); 1238 else 1239 val = __read_sysreg_by_encoding(entry->sys_reg); 1240 1241 return feature_matches(val, entry); 1242 } 1243 1244 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1245 { 1246 bool has_sre; 1247 1248 if (!has_cpuid_feature(entry, scope)) 1249 return false; 1250 1251 has_sre = gic_enable_sre(); 1252 if (!has_sre) 1253 pr_warn_once("%s present but disabled by higher exception level\n", 1254 entry->desc); 1255 1256 return has_sre; 1257 } 1258 1259 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1260 { 1261 u32 midr = read_cpuid_id(); 1262 1263 /* Cavium ThunderX pass 1.x and 2.x */ 1264 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1265 MIDR_CPU_VAR_REV(0, 0), 1266 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1267 } 1268 1269 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1270 { 1271 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1272 1273 return cpuid_feature_extract_signed_field(pfr0, 1274 ID_AA64PFR0_FP_SHIFT) < 0; 1275 } 1276 1277 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1278 int scope) 1279 { 1280 u64 ctr; 1281 1282 if (scope == SCOPE_SYSTEM) 1283 ctr = arm64_ftr_reg_ctrel0.sys_val; 1284 else 1285 ctr = read_cpuid_effective_cachetype(); 1286 1287 return ctr & BIT(CTR_IDC_SHIFT); 1288 } 1289 1290 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1291 { 1292 /* 1293 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1294 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1295 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1296 * value. 1297 */ 1298 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 1299 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1300 } 1301 1302 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1303 int scope) 1304 { 1305 u64 ctr; 1306 1307 if (scope == SCOPE_SYSTEM) 1308 ctr = arm64_ftr_reg_ctrel0.sys_val; 1309 else 1310 ctr = read_cpuid_cachetype(); 1311 1312 return ctr & BIT(CTR_DIC_SHIFT); 1313 } 1314 1315 static bool __maybe_unused 1316 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1317 { 1318 /* 1319 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1320 * may share TLB entries with a CPU stuck in the crashed 1321 * kernel. 1322 */ 1323 if (is_kdump_kernel()) 1324 return false; 1325 1326 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1327 return false; 1328 1329 return has_cpuid_feature(entry, scope); 1330 } 1331 1332 /* 1333 * This check is triggered during the early boot before the cpufeature 1334 * is initialised. Checking the status on the local CPU allows the boot 1335 * CPU to detect the need for non-global mappings and thus avoiding a 1336 * pagetable re-write after all the CPUs are booted. This check will be 1337 * anyway run on individual CPUs, allowing us to get the consistent 1338 * state once the SMP CPUs are up and thus make the switch to non-global 1339 * mappings if required. 1340 */ 1341 bool kaslr_requires_kpti(void) 1342 { 1343 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1344 return false; 1345 1346 /* 1347 * E0PD does a similar job to KPTI so can be used instead 1348 * where available. 1349 */ 1350 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1351 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1352 if (cpuid_feature_extract_unsigned_field(mmfr2, 1353 ID_AA64MMFR2_E0PD_SHIFT)) 1354 return false; 1355 } 1356 1357 /* 1358 * Systems affected by Cavium erratum 24756 are incompatible 1359 * with KPTI. 1360 */ 1361 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1362 extern const struct midr_range cavium_erratum_27456_cpus[]; 1363 1364 if (is_midr_in_range_list(read_cpuid_id(), 1365 cavium_erratum_27456_cpus)) 1366 return false; 1367 } 1368 1369 return kaslr_offset() > 0; 1370 } 1371 1372 static bool __meltdown_safe = true; 1373 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1374 1375 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1376 int scope) 1377 { 1378 /* List of CPUs that are not vulnerable and don't need KPTI */ 1379 static const struct midr_range kpti_safe_list[] = { 1380 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1381 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1382 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1383 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1384 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1385 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1386 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1387 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1388 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1389 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1390 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1391 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1392 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1393 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1394 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1395 { /* sentinel */ } 1396 }; 1397 char const *str = "kpti command line option"; 1398 bool meltdown_safe; 1399 1400 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1401 1402 /* Defer to CPU feature registers */ 1403 if (has_cpuid_feature(entry, scope)) 1404 meltdown_safe = true; 1405 1406 if (!meltdown_safe) 1407 __meltdown_safe = false; 1408 1409 /* 1410 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1411 * ThunderX leads to apparent I-cache corruption of kernel text, which 1412 * ends as well as you might imagine. Don't even try. 1413 */ 1414 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1415 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1416 __kpti_forced = -1; 1417 } 1418 1419 /* Useful for KASLR robustness */ 1420 if (kaslr_requires_kpti()) { 1421 if (!__kpti_forced) { 1422 str = "KASLR"; 1423 __kpti_forced = 1; 1424 } 1425 } 1426 1427 if (cpu_mitigations_off() && !__kpti_forced) { 1428 str = "mitigations=off"; 1429 __kpti_forced = -1; 1430 } 1431 1432 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1433 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1434 return false; 1435 } 1436 1437 /* Forced? */ 1438 if (__kpti_forced) { 1439 pr_info_once("kernel page table isolation forced %s by %s\n", 1440 __kpti_forced > 0 ? "ON" : "OFF", str); 1441 return __kpti_forced > 0; 1442 } 1443 1444 return !meltdown_safe; 1445 } 1446 1447 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1448 static void 1449 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1450 { 1451 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1452 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1453 kpti_remap_fn *remap_fn; 1454 1455 int cpu = smp_processor_id(); 1456 1457 /* 1458 * We don't need to rewrite the page-tables if either we've done 1459 * it already or we have KASLR enabled and therefore have not 1460 * created any global mappings at all. 1461 */ 1462 if (arm64_use_ng_mappings) 1463 return; 1464 1465 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1466 1467 cpu_install_idmap(); 1468 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1469 cpu_uninstall_idmap(); 1470 1471 if (!cpu) 1472 arm64_use_ng_mappings = true; 1473 1474 return; 1475 } 1476 #else 1477 static void 1478 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1479 { 1480 } 1481 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1482 1483 static int __init parse_kpti(char *str) 1484 { 1485 bool enabled; 1486 int ret = strtobool(str, &enabled); 1487 1488 if (ret) 1489 return ret; 1490 1491 __kpti_forced = enabled ? 1 : -1; 1492 return 0; 1493 } 1494 early_param("kpti", parse_kpti); 1495 1496 #ifdef CONFIG_ARM64_HW_AFDBM 1497 static inline void __cpu_enable_hw_dbm(void) 1498 { 1499 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1500 1501 write_sysreg(tcr, tcr_el1); 1502 isb(); 1503 local_flush_tlb_all(); 1504 } 1505 1506 static bool cpu_has_broken_dbm(void) 1507 { 1508 /* List of CPUs which have broken DBM support. */ 1509 static const struct midr_range cpus[] = { 1510 #ifdef CONFIG_ARM64_ERRATUM_1024718 1511 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1512 /* Kryo4xx Silver (rdpe => r1p0) */ 1513 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1514 #endif 1515 {}, 1516 }; 1517 1518 return is_midr_in_range_list(read_cpuid_id(), cpus); 1519 } 1520 1521 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1522 { 1523 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1524 !cpu_has_broken_dbm(); 1525 } 1526 1527 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1528 { 1529 if (cpu_can_use_dbm(cap)) 1530 __cpu_enable_hw_dbm(); 1531 } 1532 1533 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1534 int __unused) 1535 { 1536 static bool detected = false; 1537 /* 1538 * DBM is a non-conflicting feature. i.e, the kernel can safely 1539 * run a mix of CPUs with and without the feature. So, we 1540 * unconditionally enable the capability to allow any late CPU 1541 * to use the feature. We only enable the control bits on the 1542 * CPU, if it actually supports. 1543 * 1544 * We have to make sure we print the "feature" detection only 1545 * when at least one CPU actually uses it. So check if this CPU 1546 * can actually use it and print the message exactly once. 1547 * 1548 * This is safe as all CPUs (including secondary CPUs - due to the 1549 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1550 * goes through the "matches" check exactly once. Also if a CPU 1551 * matches the criteria, it is guaranteed that the CPU will turn 1552 * the DBM on, as the capability is unconditionally enabled. 1553 */ 1554 if (!detected && cpu_can_use_dbm(cap)) { 1555 detected = true; 1556 pr_info("detected: Hardware dirty bit management\n"); 1557 } 1558 1559 return true; 1560 } 1561 1562 #endif 1563 1564 #ifdef CONFIG_ARM64_AMU_EXTN 1565 1566 /* 1567 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1568 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1569 * information regarding all the events that it supports. When a CPU bit is 1570 * set in the cpumask, the user of this feature can only rely on the presence 1571 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1572 * counters are enabled or access to these counters is enabled by code 1573 * executed at higher exception levels (firmware). 1574 */ 1575 static struct cpumask amu_cpus __read_mostly; 1576 1577 bool cpu_has_amu_feat(int cpu) 1578 { 1579 return cpumask_test_cpu(cpu, &amu_cpus); 1580 } 1581 1582 int get_cpu_with_amu_feat(void) 1583 { 1584 return cpumask_any(&amu_cpus); 1585 } 1586 1587 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1588 { 1589 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1590 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1591 smp_processor_id()); 1592 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1593 update_freq_counters_refs(); 1594 } 1595 } 1596 1597 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1598 int __unused) 1599 { 1600 /* 1601 * The AMU extension is a non-conflicting feature: the kernel can 1602 * safely run a mix of CPUs with and without support for the 1603 * activity monitors extension. Therefore, unconditionally enable 1604 * the capability to allow any late CPU to use the feature. 1605 * 1606 * With this feature unconditionally enabled, the cpu_enable 1607 * function will be called for all CPUs that match the criteria, 1608 * including secondary and hotplugged, marking this feature as 1609 * present on that respective CPU. The enable function will also 1610 * print a detection message. 1611 */ 1612 1613 return true; 1614 } 1615 #else 1616 int get_cpu_with_amu_feat(void) 1617 { 1618 return nr_cpu_ids; 1619 } 1620 #endif 1621 1622 #ifdef CONFIG_ARM64_VHE 1623 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1624 { 1625 return is_kernel_in_hyp_mode(); 1626 } 1627 1628 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1629 { 1630 /* 1631 * Copy register values that aren't redirected by hardware. 1632 * 1633 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1634 * this value to tpidr_el2 before we patch the code. Once we've done 1635 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1636 * do anything here. 1637 */ 1638 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1639 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1640 } 1641 #endif 1642 1643 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1644 { 1645 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1646 1647 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1648 WARN_ON(val & (7 << 27 | 7 << 21)); 1649 } 1650 1651 #ifdef CONFIG_ARM64_PAN 1652 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1653 { 1654 /* 1655 * We modify PSTATE. This won't work from irq context as the PSTATE 1656 * is discarded once we return from the exception. 1657 */ 1658 WARN_ON_ONCE(in_interrupt()); 1659 1660 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1661 set_pstate_pan(1); 1662 } 1663 #endif /* CONFIG_ARM64_PAN */ 1664 1665 #ifdef CONFIG_ARM64_RAS_EXTN 1666 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1667 { 1668 /* Firmware may have left a deferred SError in this register. */ 1669 write_sysreg_s(0, SYS_DISR_EL1); 1670 } 1671 #endif /* CONFIG_ARM64_RAS_EXTN */ 1672 1673 #ifdef CONFIG_ARM64_PTR_AUTH 1674 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1675 { 1676 int boot_val, sec_val; 1677 1678 /* We don't expect to be called with SCOPE_SYSTEM */ 1679 WARN_ON(scope == SCOPE_SYSTEM); 1680 /* 1681 * The ptr-auth feature levels are not intercompatible with lower 1682 * levels. Hence we must match ptr-auth feature level of the secondary 1683 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1684 * from the sanitised register whereas direct register read is done for 1685 * the secondary CPUs. 1686 * The sanitised feature state is guaranteed to match that of the 1687 * boot CPU as a mismatched secondary CPU is parked before it gets 1688 * a chance to update the state, with the capability. 1689 */ 1690 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1691 entry->field_pos, entry->sign); 1692 if (scope & SCOPE_BOOT_CPU) 1693 return boot_val >= entry->min_field_value; 1694 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 1695 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 1696 entry->field_pos, entry->sign); 1697 return sec_val == boot_val; 1698 } 1699 1700 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 1701 int scope) 1702 { 1703 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) || 1704 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 1705 } 1706 1707 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1708 int __unused) 1709 { 1710 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) || 1711 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1712 } 1713 #endif /* CONFIG_ARM64_PTR_AUTH */ 1714 1715 #ifdef CONFIG_ARM64_E0PD 1716 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1717 { 1718 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1719 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1720 } 1721 #endif /* CONFIG_ARM64_E0PD */ 1722 1723 #ifdef CONFIG_ARM64_PSEUDO_NMI 1724 static bool enable_pseudo_nmi; 1725 1726 static int __init early_enable_pseudo_nmi(char *p) 1727 { 1728 return strtobool(p, &enable_pseudo_nmi); 1729 } 1730 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1731 1732 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1733 int scope) 1734 { 1735 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1736 } 1737 #endif 1738 1739 #ifdef CONFIG_ARM64_BTI 1740 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 1741 { 1742 /* 1743 * Use of X16/X17 for tail-calls and trampolines that jump to 1744 * function entry points using BR is a requirement for 1745 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 1746 * So, be strict and forbid other BRs using other registers to 1747 * jump onto a PACIxSP instruction: 1748 */ 1749 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 1750 isb(); 1751 } 1752 #endif /* CONFIG_ARM64_BTI */ 1753 1754 #ifdef CONFIG_ARM64_MTE 1755 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 1756 { 1757 /* 1758 * Clear the tags in the zero page. This needs to be done via the 1759 * linear map which has the Tagged attribute. 1760 */ 1761 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) 1762 mte_clear_page_tags(lm_alias(empty_zero_page)); 1763 1764 kasan_init_hw_tags_cpu(); 1765 } 1766 #endif /* CONFIG_ARM64_MTE */ 1767 1768 #ifdef CONFIG_KVM 1769 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 1770 { 1771 if (kvm_get_mode() != KVM_MODE_PROTECTED) 1772 return false; 1773 1774 if (is_kernel_in_hyp_mode()) { 1775 pr_warn("Protected KVM not available with VHE\n"); 1776 return false; 1777 } 1778 1779 return true; 1780 } 1781 #endif /* CONFIG_KVM */ 1782 1783 /* Internal helper functions to match cpu capability type */ 1784 static bool 1785 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1786 { 1787 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1788 } 1789 1790 static bool 1791 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1792 { 1793 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1794 } 1795 1796 static bool 1797 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 1798 { 1799 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 1800 } 1801 1802 static const struct arm64_cpu_capabilities arm64_features[] = { 1803 { 1804 .desc = "GIC system register CPU interface", 1805 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1806 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1807 .matches = has_useable_gicv3_cpuif, 1808 .sys_reg = SYS_ID_AA64PFR0_EL1, 1809 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1810 .sign = FTR_UNSIGNED, 1811 .min_field_value = 1, 1812 }, 1813 #ifdef CONFIG_ARM64_PAN 1814 { 1815 .desc = "Privileged Access Never", 1816 .capability = ARM64_HAS_PAN, 1817 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1818 .matches = has_cpuid_feature, 1819 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1820 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1821 .sign = FTR_UNSIGNED, 1822 .min_field_value = 1, 1823 .cpu_enable = cpu_enable_pan, 1824 }, 1825 #endif /* CONFIG_ARM64_PAN */ 1826 #ifdef CONFIG_ARM64_LSE_ATOMICS 1827 { 1828 .desc = "LSE atomic instructions", 1829 .capability = ARM64_HAS_LSE_ATOMICS, 1830 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1831 .matches = has_cpuid_feature, 1832 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1833 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1834 .sign = FTR_UNSIGNED, 1835 .min_field_value = 2, 1836 }, 1837 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 1838 { 1839 .desc = "Software prefetching using PRFM", 1840 .capability = ARM64_HAS_NO_HW_PREFETCH, 1841 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1842 .matches = has_no_hw_prefetch, 1843 }, 1844 #ifdef CONFIG_ARM64_VHE 1845 { 1846 .desc = "Virtualization Host Extensions", 1847 .capability = ARM64_HAS_VIRT_HOST_EXTN, 1848 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1849 .matches = runs_at_el2, 1850 .cpu_enable = cpu_copy_el2regs, 1851 }, 1852 #endif /* CONFIG_ARM64_VHE */ 1853 { 1854 .desc = "32-bit EL0 Support", 1855 .capability = ARM64_HAS_32BIT_EL0, 1856 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1857 .matches = has_cpuid_feature, 1858 .sys_reg = SYS_ID_AA64PFR0_EL1, 1859 .sign = FTR_UNSIGNED, 1860 .field_pos = ID_AA64PFR0_EL0_SHIFT, 1861 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 1862 }, 1863 #ifdef CONFIG_KVM 1864 { 1865 .desc = "32-bit EL1 Support", 1866 .capability = ARM64_HAS_32BIT_EL1, 1867 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1868 .matches = has_cpuid_feature, 1869 .sys_reg = SYS_ID_AA64PFR0_EL1, 1870 .sign = FTR_UNSIGNED, 1871 .field_pos = ID_AA64PFR0_EL1_SHIFT, 1872 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT, 1873 }, 1874 { 1875 .desc = "Protected KVM", 1876 .capability = ARM64_KVM_PROTECTED_MODE, 1877 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1878 .matches = is_kvm_protected_mode, 1879 }, 1880 #endif 1881 { 1882 .desc = "Kernel page table isolation (KPTI)", 1883 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 1884 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1885 /* 1886 * The ID feature fields below are used to indicate that 1887 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 1888 * more details. 1889 */ 1890 .sys_reg = SYS_ID_AA64PFR0_EL1, 1891 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 1892 .min_field_value = 1, 1893 .matches = unmap_kernel_at_el0, 1894 .cpu_enable = kpti_install_ng_mappings, 1895 }, 1896 { 1897 /* FP/SIMD is not implemented */ 1898 .capability = ARM64_HAS_NO_FPSIMD, 1899 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1900 .min_field_value = 0, 1901 .matches = has_no_fpsimd, 1902 }, 1903 #ifdef CONFIG_ARM64_PMEM 1904 { 1905 .desc = "Data cache clean to Point of Persistence", 1906 .capability = ARM64_HAS_DCPOP, 1907 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1908 .matches = has_cpuid_feature, 1909 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1910 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1911 .min_field_value = 1, 1912 }, 1913 { 1914 .desc = "Data cache clean to Point of Deep Persistence", 1915 .capability = ARM64_HAS_DCPODP, 1916 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1917 .matches = has_cpuid_feature, 1918 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1919 .sign = FTR_UNSIGNED, 1920 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1921 .min_field_value = 2, 1922 }, 1923 #endif 1924 #ifdef CONFIG_ARM64_SVE 1925 { 1926 .desc = "Scalable Vector Extension", 1927 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1928 .capability = ARM64_SVE, 1929 .sys_reg = SYS_ID_AA64PFR0_EL1, 1930 .sign = FTR_UNSIGNED, 1931 .field_pos = ID_AA64PFR0_SVE_SHIFT, 1932 .min_field_value = ID_AA64PFR0_SVE, 1933 .matches = has_cpuid_feature, 1934 .cpu_enable = sve_kernel_enable, 1935 }, 1936 #endif /* CONFIG_ARM64_SVE */ 1937 #ifdef CONFIG_ARM64_RAS_EXTN 1938 { 1939 .desc = "RAS Extension Support", 1940 .capability = ARM64_HAS_RAS_EXTN, 1941 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1942 .matches = has_cpuid_feature, 1943 .sys_reg = SYS_ID_AA64PFR0_EL1, 1944 .sign = FTR_UNSIGNED, 1945 .field_pos = ID_AA64PFR0_RAS_SHIFT, 1946 .min_field_value = ID_AA64PFR0_RAS_V1, 1947 .cpu_enable = cpu_clear_disr, 1948 }, 1949 #endif /* CONFIG_ARM64_RAS_EXTN */ 1950 #ifdef CONFIG_ARM64_AMU_EXTN 1951 { 1952 /* 1953 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 1954 * Therefore, don't provide .desc as we don't want the detection 1955 * message to be shown until at least one CPU is detected to 1956 * support the feature. 1957 */ 1958 .capability = ARM64_HAS_AMU_EXTN, 1959 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1960 .matches = has_amu, 1961 .sys_reg = SYS_ID_AA64PFR0_EL1, 1962 .sign = FTR_UNSIGNED, 1963 .field_pos = ID_AA64PFR0_AMU_SHIFT, 1964 .min_field_value = ID_AA64PFR0_AMU, 1965 .cpu_enable = cpu_amu_enable, 1966 }, 1967 #endif /* CONFIG_ARM64_AMU_EXTN */ 1968 { 1969 .desc = "Data cache clean to the PoU not required for I/D coherence", 1970 .capability = ARM64_HAS_CACHE_IDC, 1971 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1972 .matches = has_cache_idc, 1973 .cpu_enable = cpu_emulate_effective_ctr, 1974 }, 1975 { 1976 .desc = "Instruction cache invalidation not required for I/D coherence", 1977 .capability = ARM64_HAS_CACHE_DIC, 1978 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1979 .matches = has_cache_dic, 1980 }, 1981 { 1982 .desc = "Stage-2 Force Write-Back", 1983 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1984 .capability = ARM64_HAS_STAGE2_FWB, 1985 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1986 .sign = FTR_UNSIGNED, 1987 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 1988 .min_field_value = 1, 1989 .matches = has_cpuid_feature, 1990 .cpu_enable = cpu_has_fwb, 1991 }, 1992 { 1993 .desc = "ARMv8.4 Translation Table Level", 1994 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1995 .capability = ARM64_HAS_ARMv8_4_TTL, 1996 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1997 .sign = FTR_UNSIGNED, 1998 .field_pos = ID_AA64MMFR2_TTL_SHIFT, 1999 .min_field_value = 1, 2000 .matches = has_cpuid_feature, 2001 }, 2002 { 2003 .desc = "TLB range maintenance instructions", 2004 .capability = ARM64_HAS_TLB_RANGE, 2005 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2006 .matches = has_cpuid_feature, 2007 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2008 .field_pos = ID_AA64ISAR0_TLB_SHIFT, 2009 .sign = FTR_UNSIGNED, 2010 .min_field_value = ID_AA64ISAR0_TLB_RANGE, 2011 }, 2012 #ifdef CONFIG_ARM64_HW_AFDBM 2013 { 2014 /* 2015 * Since we turn this on always, we don't want the user to 2016 * think that the feature is available when it may not be. 2017 * So hide the description. 2018 * 2019 * .desc = "Hardware pagetable Dirty Bit Management", 2020 * 2021 */ 2022 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2023 .capability = ARM64_HW_DBM, 2024 .sys_reg = SYS_ID_AA64MMFR1_EL1, 2025 .sign = FTR_UNSIGNED, 2026 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 2027 .min_field_value = 2, 2028 .matches = has_hw_dbm, 2029 .cpu_enable = cpu_enable_hw_dbm, 2030 }, 2031 #endif 2032 { 2033 .desc = "CRC32 instructions", 2034 .capability = ARM64_HAS_CRC32, 2035 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2036 .matches = has_cpuid_feature, 2037 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2038 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 2039 .min_field_value = 1, 2040 }, 2041 { 2042 .desc = "Speculative Store Bypassing Safe (SSBS)", 2043 .capability = ARM64_SSBS, 2044 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2045 .matches = has_cpuid_feature, 2046 .sys_reg = SYS_ID_AA64PFR1_EL1, 2047 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 2048 .sign = FTR_UNSIGNED, 2049 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 2050 }, 2051 #ifdef CONFIG_ARM64_CNP 2052 { 2053 .desc = "Common not Private translations", 2054 .capability = ARM64_HAS_CNP, 2055 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2056 .matches = has_useable_cnp, 2057 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2058 .sign = FTR_UNSIGNED, 2059 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 2060 .min_field_value = 1, 2061 .cpu_enable = cpu_enable_cnp, 2062 }, 2063 #endif 2064 { 2065 .desc = "Speculation barrier (SB)", 2066 .capability = ARM64_HAS_SB, 2067 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2068 .matches = has_cpuid_feature, 2069 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2070 .field_pos = ID_AA64ISAR1_SB_SHIFT, 2071 .sign = FTR_UNSIGNED, 2072 .min_field_value = 1, 2073 }, 2074 #ifdef CONFIG_ARM64_PTR_AUTH 2075 { 2076 .desc = "Address authentication (architected algorithm)", 2077 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 2078 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2079 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2080 .sign = FTR_UNSIGNED, 2081 .field_pos = ID_AA64ISAR1_APA_SHIFT, 2082 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 2083 .matches = has_address_auth_cpucap, 2084 }, 2085 { 2086 .desc = "Address authentication (IMP DEF algorithm)", 2087 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2088 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2089 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2090 .sign = FTR_UNSIGNED, 2091 .field_pos = ID_AA64ISAR1_API_SHIFT, 2092 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 2093 .matches = has_address_auth_cpucap, 2094 }, 2095 { 2096 .capability = ARM64_HAS_ADDRESS_AUTH, 2097 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2098 .matches = has_address_auth_metacap, 2099 }, 2100 { 2101 .desc = "Generic authentication (architected algorithm)", 2102 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 2103 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2104 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2105 .sign = FTR_UNSIGNED, 2106 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 2107 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 2108 .matches = has_cpuid_feature, 2109 }, 2110 { 2111 .desc = "Generic authentication (IMP DEF algorithm)", 2112 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2113 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2114 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2115 .sign = FTR_UNSIGNED, 2116 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 2117 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 2118 .matches = has_cpuid_feature, 2119 }, 2120 { 2121 .capability = ARM64_HAS_GENERIC_AUTH, 2122 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2123 .matches = has_generic_auth, 2124 }, 2125 #endif /* CONFIG_ARM64_PTR_AUTH */ 2126 #ifdef CONFIG_ARM64_PSEUDO_NMI 2127 { 2128 /* 2129 * Depends on having GICv3 2130 */ 2131 .desc = "IRQ priority masking", 2132 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2133 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2134 .matches = can_use_gic_priorities, 2135 .sys_reg = SYS_ID_AA64PFR0_EL1, 2136 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2137 .sign = FTR_UNSIGNED, 2138 .min_field_value = 1, 2139 }, 2140 #endif 2141 #ifdef CONFIG_ARM64_E0PD 2142 { 2143 .desc = "E0PD", 2144 .capability = ARM64_HAS_E0PD, 2145 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2146 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2147 .sign = FTR_UNSIGNED, 2148 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2149 .matches = has_cpuid_feature, 2150 .min_field_value = 1, 2151 .cpu_enable = cpu_enable_e0pd, 2152 }, 2153 #endif 2154 #ifdef CONFIG_ARCH_RANDOM 2155 { 2156 .desc = "Random Number Generator", 2157 .capability = ARM64_HAS_RNG, 2158 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2159 .matches = has_cpuid_feature, 2160 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2161 .field_pos = ID_AA64ISAR0_RNDR_SHIFT, 2162 .sign = FTR_UNSIGNED, 2163 .min_field_value = 1, 2164 }, 2165 #endif 2166 #ifdef CONFIG_ARM64_BTI 2167 { 2168 .desc = "Branch Target Identification", 2169 .capability = ARM64_BTI, 2170 #ifdef CONFIG_ARM64_BTI_KERNEL 2171 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2172 #else 2173 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2174 #endif 2175 .matches = has_cpuid_feature, 2176 .cpu_enable = bti_enable, 2177 .sys_reg = SYS_ID_AA64PFR1_EL1, 2178 .field_pos = ID_AA64PFR1_BT_SHIFT, 2179 .min_field_value = ID_AA64PFR1_BT_BTI, 2180 .sign = FTR_UNSIGNED, 2181 }, 2182 #endif 2183 #ifdef CONFIG_ARM64_MTE 2184 { 2185 .desc = "Memory Tagging Extension", 2186 .capability = ARM64_MTE, 2187 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2188 .matches = has_cpuid_feature, 2189 .sys_reg = SYS_ID_AA64PFR1_EL1, 2190 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2191 .min_field_value = ID_AA64PFR1_MTE, 2192 .sign = FTR_UNSIGNED, 2193 .cpu_enable = cpu_enable_mte, 2194 }, 2195 #endif /* CONFIG_ARM64_MTE */ 2196 { 2197 .desc = "RCpc load-acquire (LDAPR)", 2198 .capability = ARM64_HAS_LDAPR, 2199 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2200 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2201 .sign = FTR_UNSIGNED, 2202 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, 2203 .matches = has_cpuid_feature, 2204 .min_field_value = 1, 2205 }, 2206 {}, 2207 }; 2208 2209 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2210 .matches = has_cpuid_feature, \ 2211 .sys_reg = reg, \ 2212 .field_pos = field, \ 2213 .sign = s, \ 2214 .min_field_value = min_value, 2215 2216 #define __HWCAP_CAP(name, cap_type, cap) \ 2217 .desc = name, \ 2218 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2219 .hwcap_type = cap_type, \ 2220 .hwcap = cap, \ 2221 2222 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 2223 { \ 2224 __HWCAP_CAP(#cap, cap_type, cap) \ 2225 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2226 } 2227 2228 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2229 { \ 2230 __HWCAP_CAP(#cap, cap_type, cap) \ 2231 .matches = cpucap_multi_entry_cap_matches, \ 2232 .match_list = list, \ 2233 } 2234 2235 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2236 { \ 2237 __HWCAP_CAP(#cap, cap_type, cap) \ 2238 .matches = match, \ 2239 } 2240 2241 #ifdef CONFIG_ARM64_PTR_AUTH 2242 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2243 { 2244 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 2245 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 2246 }, 2247 { 2248 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 2249 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 2250 }, 2251 {}, 2252 }; 2253 2254 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2255 { 2256 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 2257 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 2258 }, 2259 { 2260 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 2261 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 2262 }, 2263 {}, 2264 }; 2265 #endif 2266 2267 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2268 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2269 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2270 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2271 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2272 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2273 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2274 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2275 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2276 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2277 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2278 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2279 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2280 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2281 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2282 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2283 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2284 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2285 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2286 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2287 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2288 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2289 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2290 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2291 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2292 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2293 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2294 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2295 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2296 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2297 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2298 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2299 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2300 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2301 #ifdef CONFIG_ARM64_SVE 2302 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2303 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2304 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2305 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2306 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2307 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2308 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2309 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2310 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2311 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2312 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2313 #endif 2314 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2315 #ifdef CONFIG_ARM64_BTI 2316 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2317 #endif 2318 #ifdef CONFIG_ARM64_PTR_AUTH 2319 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2320 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2321 #endif 2322 #ifdef CONFIG_ARM64_MTE 2323 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), 2324 #endif /* CONFIG_ARM64_MTE */ 2325 {}, 2326 }; 2327 2328 #ifdef CONFIG_COMPAT 2329 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2330 { 2331 /* 2332 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2333 * in line with that of arm32 as in vfp_init(). We make sure that the 2334 * check is future proof, by making sure value is non-zero. 2335 */ 2336 u32 mvfr1; 2337 2338 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2339 if (scope == SCOPE_SYSTEM) 2340 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2341 else 2342 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2343 2344 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2345 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2346 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2347 } 2348 #endif 2349 2350 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2351 #ifdef CONFIG_COMPAT 2352 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2353 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2354 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2355 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2356 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2357 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2358 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2359 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2360 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2361 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2362 #endif 2363 {}, 2364 }; 2365 2366 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2367 { 2368 switch (cap->hwcap_type) { 2369 case CAP_HWCAP: 2370 cpu_set_feature(cap->hwcap); 2371 break; 2372 #ifdef CONFIG_COMPAT 2373 case CAP_COMPAT_HWCAP: 2374 compat_elf_hwcap |= (u32)cap->hwcap; 2375 break; 2376 case CAP_COMPAT_HWCAP2: 2377 compat_elf_hwcap2 |= (u32)cap->hwcap; 2378 break; 2379 #endif 2380 default: 2381 WARN_ON(1); 2382 break; 2383 } 2384 } 2385 2386 /* Check if we have a particular HWCAP enabled */ 2387 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2388 { 2389 bool rc; 2390 2391 switch (cap->hwcap_type) { 2392 case CAP_HWCAP: 2393 rc = cpu_have_feature(cap->hwcap); 2394 break; 2395 #ifdef CONFIG_COMPAT 2396 case CAP_COMPAT_HWCAP: 2397 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2398 break; 2399 case CAP_COMPAT_HWCAP2: 2400 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2401 break; 2402 #endif 2403 default: 2404 WARN_ON(1); 2405 rc = false; 2406 } 2407 2408 return rc; 2409 } 2410 2411 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2412 { 2413 /* We support emulation of accesses to CPU ID feature registers */ 2414 cpu_set_named_feature(CPUID); 2415 for (; hwcaps->matches; hwcaps++) 2416 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2417 cap_set_elf_hwcap(hwcaps); 2418 } 2419 2420 static void update_cpu_capabilities(u16 scope_mask) 2421 { 2422 int i; 2423 const struct arm64_cpu_capabilities *caps; 2424 2425 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2426 for (i = 0; i < ARM64_NCAPS; i++) { 2427 caps = cpu_hwcaps_ptrs[i]; 2428 if (!caps || !(caps->type & scope_mask) || 2429 cpus_have_cap(caps->capability) || 2430 !caps->matches(caps, cpucap_default_scope(caps))) 2431 continue; 2432 2433 if (caps->desc) 2434 pr_info("detected: %s\n", caps->desc); 2435 cpus_set_cap(caps->capability); 2436 2437 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2438 set_bit(caps->capability, boot_capabilities); 2439 } 2440 } 2441 2442 /* 2443 * Enable all the available capabilities on this CPU. The capabilities 2444 * with BOOT_CPU scope are handled separately and hence skipped here. 2445 */ 2446 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2447 { 2448 int i; 2449 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2450 2451 for_each_available_cap(i) { 2452 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2453 2454 if (WARN_ON(!cap)) 2455 continue; 2456 2457 if (!(cap->type & non_boot_scope)) 2458 continue; 2459 2460 if (cap->cpu_enable) 2461 cap->cpu_enable(cap); 2462 } 2463 return 0; 2464 } 2465 2466 /* 2467 * Run through the enabled capabilities and enable() it on all active 2468 * CPUs 2469 */ 2470 static void __init enable_cpu_capabilities(u16 scope_mask) 2471 { 2472 int i; 2473 const struct arm64_cpu_capabilities *caps; 2474 bool boot_scope; 2475 2476 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2477 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2478 2479 for (i = 0; i < ARM64_NCAPS; i++) { 2480 unsigned int num; 2481 2482 caps = cpu_hwcaps_ptrs[i]; 2483 if (!caps || !(caps->type & scope_mask)) 2484 continue; 2485 num = caps->capability; 2486 if (!cpus_have_cap(num)) 2487 continue; 2488 2489 /* Ensure cpus_have_const_cap(num) works */ 2490 static_branch_enable(&cpu_hwcap_keys[num]); 2491 2492 if (boot_scope && caps->cpu_enable) 2493 /* 2494 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2495 * before any secondary CPU boots. Thus, each secondary 2496 * will enable the capability as appropriate via 2497 * check_local_cpu_capabilities(). The only exception is 2498 * the boot CPU, for which the capability must be 2499 * enabled here. This approach avoids costly 2500 * stop_machine() calls for this case. 2501 */ 2502 caps->cpu_enable(caps); 2503 } 2504 2505 /* 2506 * For all non-boot scope capabilities, use stop_machine() 2507 * as it schedules the work allowing us to modify PSTATE, 2508 * instead of on_each_cpu() which uses an IPI, giving us a 2509 * PSTATE that disappears when we return. 2510 */ 2511 if (!boot_scope) 2512 stop_machine(cpu_enable_non_boot_scope_capabilities, 2513 NULL, cpu_online_mask); 2514 } 2515 2516 /* 2517 * Run through the list of capabilities to check for conflicts. 2518 * If the system has already detected a capability, take necessary 2519 * action on this CPU. 2520 */ 2521 static void verify_local_cpu_caps(u16 scope_mask) 2522 { 2523 int i; 2524 bool cpu_has_cap, system_has_cap; 2525 const struct arm64_cpu_capabilities *caps; 2526 2527 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2528 2529 for (i = 0; i < ARM64_NCAPS; i++) { 2530 caps = cpu_hwcaps_ptrs[i]; 2531 if (!caps || !(caps->type & scope_mask)) 2532 continue; 2533 2534 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2535 system_has_cap = cpus_have_cap(caps->capability); 2536 2537 if (system_has_cap) { 2538 /* 2539 * Check if the new CPU misses an advertised feature, 2540 * which is not safe to miss. 2541 */ 2542 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2543 break; 2544 /* 2545 * We have to issue cpu_enable() irrespective of 2546 * whether the CPU has it or not, as it is enabeld 2547 * system wide. It is upto the call back to take 2548 * appropriate action on this CPU. 2549 */ 2550 if (caps->cpu_enable) 2551 caps->cpu_enable(caps); 2552 } else { 2553 /* 2554 * Check if the CPU has this capability if it isn't 2555 * safe to have when the system doesn't. 2556 */ 2557 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2558 break; 2559 } 2560 } 2561 2562 if (i < ARM64_NCAPS) { 2563 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2564 smp_processor_id(), caps->capability, 2565 caps->desc, system_has_cap, cpu_has_cap); 2566 2567 if (cpucap_panic_on_conflict(caps)) 2568 cpu_panic_kernel(); 2569 else 2570 cpu_die_early(); 2571 } 2572 } 2573 2574 /* 2575 * Check for CPU features that are used in early boot 2576 * based on the Boot CPU value. 2577 */ 2578 static void check_early_cpu_features(void) 2579 { 2580 verify_cpu_asid_bits(); 2581 2582 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2583 } 2584 2585 static void 2586 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2587 { 2588 2589 for (; caps->matches; caps++) 2590 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2591 pr_crit("CPU%d: missing HWCAP: %s\n", 2592 smp_processor_id(), caps->desc); 2593 cpu_die_early(); 2594 } 2595 } 2596 2597 static void verify_sve_features(void) 2598 { 2599 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2600 u64 zcr = read_zcr_features(); 2601 2602 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2603 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2604 2605 if (len < safe_len || sve_verify_vq_map()) { 2606 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2607 smp_processor_id()); 2608 cpu_die_early(); 2609 } 2610 2611 /* Add checks on other ZCR bits here if necessary */ 2612 } 2613 2614 static void verify_hyp_capabilities(void) 2615 { 2616 u64 safe_mmfr1, mmfr0, mmfr1; 2617 int parange, ipa_max; 2618 unsigned int safe_vmid_bits, vmid_bits; 2619 2620 if (!IS_ENABLED(CONFIG_KVM)) 2621 return; 2622 2623 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 2624 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 2625 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 2626 2627 /* Verify VMID bits */ 2628 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 2629 vmid_bits = get_vmid_bits(mmfr1); 2630 if (vmid_bits < safe_vmid_bits) { 2631 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 2632 cpu_die_early(); 2633 } 2634 2635 /* Verify IPA range */ 2636 parange = cpuid_feature_extract_unsigned_field(mmfr0, 2637 ID_AA64MMFR0_PARANGE_SHIFT); 2638 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 2639 if (ipa_max < get_kvm_ipa_limit()) { 2640 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 2641 cpu_die_early(); 2642 } 2643 } 2644 2645 /* 2646 * Run through the enabled system capabilities and enable() it on this CPU. 2647 * The capabilities were decided based on the available CPUs at the boot time. 2648 * Any new CPU should match the system wide status of the capability. If the 2649 * new CPU doesn't have a capability which the system now has enabled, we 2650 * cannot do anything to fix it up and could cause unexpected failures. So 2651 * we park the CPU. 2652 */ 2653 static void verify_local_cpu_capabilities(void) 2654 { 2655 /* 2656 * The capabilities with SCOPE_BOOT_CPU are checked from 2657 * check_early_cpu_features(), as they need to be verified 2658 * on all secondary CPUs. 2659 */ 2660 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2661 2662 verify_local_elf_hwcaps(arm64_elf_hwcaps); 2663 2664 if (system_supports_32bit_el0()) 2665 verify_local_elf_hwcaps(compat_elf_hwcaps); 2666 2667 if (system_supports_sve()) 2668 verify_sve_features(); 2669 2670 if (is_hyp_mode_available()) 2671 verify_hyp_capabilities(); 2672 } 2673 2674 void check_local_cpu_capabilities(void) 2675 { 2676 /* 2677 * All secondary CPUs should conform to the early CPU features 2678 * in use by the kernel based on boot CPU. 2679 */ 2680 check_early_cpu_features(); 2681 2682 /* 2683 * If we haven't finalised the system capabilities, this CPU gets 2684 * a chance to update the errata work arounds and local features. 2685 * Otherwise, this CPU should verify that it has all the system 2686 * advertised capabilities. 2687 */ 2688 if (!system_capabilities_finalized()) 2689 update_cpu_capabilities(SCOPE_LOCAL_CPU); 2690 else 2691 verify_local_cpu_capabilities(); 2692 } 2693 2694 static void __init setup_boot_cpu_capabilities(void) 2695 { 2696 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 2697 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 2698 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 2699 enable_cpu_capabilities(SCOPE_BOOT_CPU); 2700 } 2701 2702 bool this_cpu_has_cap(unsigned int n) 2703 { 2704 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 2705 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2706 2707 if (cap) 2708 return cap->matches(cap, SCOPE_LOCAL_CPU); 2709 } 2710 2711 return false; 2712 } 2713 2714 /* 2715 * This helper function is used in a narrow window when, 2716 * - The system wide safe registers are set with all the SMP CPUs and, 2717 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 2718 * In all other cases cpus_have_{const_}cap() should be used. 2719 */ 2720 static bool __maybe_unused __system_matches_cap(unsigned int n) 2721 { 2722 if (n < ARM64_NCAPS) { 2723 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2724 2725 if (cap) 2726 return cap->matches(cap, SCOPE_SYSTEM); 2727 } 2728 return false; 2729 } 2730 2731 void cpu_set_feature(unsigned int num) 2732 { 2733 WARN_ON(num >= MAX_CPU_FEATURES); 2734 elf_hwcap |= BIT(num); 2735 } 2736 EXPORT_SYMBOL_GPL(cpu_set_feature); 2737 2738 bool cpu_have_feature(unsigned int num) 2739 { 2740 WARN_ON(num >= MAX_CPU_FEATURES); 2741 return elf_hwcap & BIT(num); 2742 } 2743 EXPORT_SYMBOL_GPL(cpu_have_feature); 2744 2745 unsigned long cpu_get_elf_hwcap(void) 2746 { 2747 /* 2748 * We currently only populate the first 32 bits of AT_HWCAP. Please 2749 * note that for userspace compatibility we guarantee that bits 62 2750 * and 63 will always be returned as 0. 2751 */ 2752 return lower_32_bits(elf_hwcap); 2753 } 2754 2755 unsigned long cpu_get_elf_hwcap2(void) 2756 { 2757 return upper_32_bits(elf_hwcap); 2758 } 2759 2760 static void __init setup_system_capabilities(void) 2761 { 2762 /* 2763 * We have finalised the system-wide safe feature 2764 * registers, finalise the capabilities that depend 2765 * on it. Also enable all the available capabilities, 2766 * that are not enabled already. 2767 */ 2768 update_cpu_capabilities(SCOPE_SYSTEM); 2769 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2770 } 2771 2772 void __init setup_cpu_features(void) 2773 { 2774 u32 cwg; 2775 2776 setup_system_capabilities(); 2777 setup_elf_hwcaps(arm64_elf_hwcaps); 2778 2779 if (system_supports_32bit_el0()) 2780 setup_elf_hwcaps(compat_elf_hwcaps); 2781 2782 if (system_uses_ttbr0_pan()) 2783 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2784 2785 sve_setup(); 2786 minsigstksz_setup(); 2787 2788 /* Advertise that we have computed the system capabilities */ 2789 finalize_system_capabilities(); 2790 2791 /* 2792 * Check for sane CTR_EL0.CWG value. 2793 */ 2794 cwg = cache_type_cwg(); 2795 if (!cwg) 2796 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2797 ARCH_DMA_MINALIGN); 2798 } 2799 2800 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 2801 { 2802 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 2803 } 2804 2805 /* 2806 * We emulate only the following system register space. 2807 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 2808 * See Table C5-6 System instruction encodings for System register accesses, 2809 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 2810 */ 2811 static inline bool __attribute_const__ is_emulated(u32 id) 2812 { 2813 return (sys_reg_Op0(id) == 0x3 && 2814 sys_reg_CRn(id) == 0x0 && 2815 sys_reg_Op1(id) == 0x0 && 2816 (sys_reg_CRm(id) == 0 || 2817 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 2818 } 2819 2820 /* 2821 * With CRm == 0, reg should be one of : 2822 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 2823 */ 2824 static inline int emulate_id_reg(u32 id, u64 *valp) 2825 { 2826 switch (id) { 2827 case SYS_MIDR_EL1: 2828 *valp = read_cpuid_id(); 2829 break; 2830 case SYS_MPIDR_EL1: 2831 *valp = SYS_MPIDR_SAFE_VAL; 2832 break; 2833 case SYS_REVIDR_EL1: 2834 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 2835 *valp = 0; 2836 break; 2837 default: 2838 return -EINVAL; 2839 } 2840 2841 return 0; 2842 } 2843 2844 static int emulate_sys_reg(u32 id, u64 *valp) 2845 { 2846 struct arm64_ftr_reg *regp; 2847 2848 if (!is_emulated(id)) 2849 return -EINVAL; 2850 2851 if (sys_reg_CRm(id) == 0) 2852 return emulate_id_reg(id, valp); 2853 2854 regp = get_arm64_ftr_reg_nowarn(id); 2855 if (regp) 2856 *valp = arm64_ftr_reg_user_value(regp); 2857 else 2858 /* 2859 * The untracked registers are either IMPLEMENTATION DEFINED 2860 * (e.g, ID_AFR0_EL1) or reserved RAZ. 2861 */ 2862 *valp = 0; 2863 return 0; 2864 } 2865 2866 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 2867 { 2868 int rc; 2869 u64 val; 2870 2871 rc = emulate_sys_reg(sys_reg, &val); 2872 if (!rc) { 2873 pt_regs_write_reg(regs, rt, val); 2874 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 2875 } 2876 return rc; 2877 } 2878 2879 static int emulate_mrs(struct pt_regs *regs, u32 insn) 2880 { 2881 u32 sys_reg, rt; 2882 2883 /* 2884 * sys_reg values are defined as used in mrs/msr instruction. 2885 * shift the imm value to get the encoding. 2886 */ 2887 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 2888 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 2889 return do_emulate_mrs(regs, sys_reg, rt); 2890 } 2891 2892 static struct undef_hook mrs_hook = { 2893 .instr_mask = 0xfff00000, 2894 .instr_val = 0xd5300000, 2895 .pstate_mask = PSR_AA32_MODE_MASK, 2896 .pstate_val = PSR_MODE_EL0t, 2897 .fn = emulate_mrs, 2898 }; 2899 2900 static int __init enable_mrs_emulation(void) 2901 { 2902 register_undef_hook(&mrs_hook); 2903 return 0; 2904 } 2905 2906 core_initcall(enable_mrs_emulation); 2907 2908 enum mitigation_state arm64_get_meltdown_state(void) 2909 { 2910 if (__meltdown_safe) 2911 return SPECTRE_UNAFFECTED; 2912 2913 if (arm64_kernel_unmapped_at_el0()) 2914 return SPECTRE_MITIGATED; 2915 2916 return SPECTRE_VULNERABLE; 2917 } 2918 2919 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 2920 char *buf) 2921 { 2922 switch (arm64_get_meltdown_state()) { 2923 case SPECTRE_UNAFFECTED: 2924 return sprintf(buf, "Not affected\n"); 2925 2926 case SPECTRE_MITIGATED: 2927 return sprintf(buf, "Mitigation: PTI\n"); 2928 2929 default: 2930 return sprintf(buf, "Vulnerable\n"); 2931 } 2932 } 2933