1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/types.h> 71 #include <linux/mm.h> 72 #include <linux/cpu.h> 73 #include <asm/cpu.h> 74 #include <asm/cpufeature.h> 75 #include <asm/cpu_ops.h> 76 #include <asm/fpsimd.h> 77 #include <asm/mmu_context.h> 78 #include <asm/processor.h> 79 #include <asm/sysreg.h> 80 #include <asm/traps.h> 81 #include <asm/virt.h> 82 83 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 84 static unsigned long elf_hwcap __read_mostly; 85 86 #ifdef CONFIG_COMPAT 87 #define COMPAT_ELF_HWCAP_DEFAULT \ 88 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 89 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 90 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 91 COMPAT_HWCAP_LPAE) 92 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 93 unsigned int compat_elf_hwcap2 __read_mostly; 94 #endif 95 96 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 97 EXPORT_SYMBOL(cpu_hwcaps); 98 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 99 100 /* Need also bit for ARM64_CB_PATCH */ 101 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 102 103 bool arm64_use_ng_mappings = false; 104 EXPORT_SYMBOL(arm64_use_ng_mappings); 105 106 /* 107 * Flag to indicate if we have computed the system wide 108 * capabilities based on the boot time active CPUs. This 109 * will be used to determine if a new booting CPU should 110 * go through the verification process to make sure that it 111 * supports the system capabilities, without using a hotplug 112 * notifier. This is also used to decide if we could use 113 * the fast path for checking constant CPU caps. 114 */ 115 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 116 EXPORT_SYMBOL(arm64_const_caps_ready); 117 static inline void finalize_system_capabilities(void) 118 { 119 static_branch_enable(&arm64_const_caps_ready); 120 } 121 122 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p) 123 { 124 /* file-wide pr_fmt adds "CPU features: " prefix */ 125 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 126 return 0; 127 } 128 129 static struct notifier_block cpu_hwcaps_notifier = { 130 .notifier_call = dump_cpu_hwcaps 131 }; 132 133 static int __init register_cpu_hwcaps_dumper(void) 134 { 135 atomic_notifier_chain_register(&panic_notifier_list, 136 &cpu_hwcaps_notifier); 137 return 0; 138 } 139 __initcall(register_cpu_hwcaps_dumper); 140 141 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 142 EXPORT_SYMBOL(cpu_hwcap_keys); 143 144 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 145 { \ 146 .sign = SIGNED, \ 147 .visible = VISIBLE, \ 148 .strict = STRICT, \ 149 .type = TYPE, \ 150 .shift = SHIFT, \ 151 .width = WIDTH, \ 152 .safe_val = SAFE_VAL, \ 153 } 154 155 /* Define a feature with unsigned values */ 156 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 157 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 158 159 /* Define a feature with a signed value */ 160 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 161 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 162 163 #define ARM64_FTR_END \ 164 { \ 165 .width = 0, \ 166 } 167 168 /* meta feature for alternatives */ 169 static bool __maybe_unused 170 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused); 171 172 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 173 174 static bool __system_matches_cap(unsigned int n); 175 176 /* 177 * NOTE: Any changes to the visibility of features should be kept in 178 * sync with the documentation of the CPU feature register ABI. 179 */ 180 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), 182 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0), 183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 184 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 195 ARM64_FTR_END, 196 }; 197 198 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 206 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 208 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 213 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 215 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 217 ARM64_FTR_END, 218 }; 219 220 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 228 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 231 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 232 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 237 ARM64_FTR_END, 238 }; 239 240 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 245 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 246 ARM64_FTR_END, 247 }; 248 249 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 256 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 257 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 259 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 261 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 268 ARM64_FTR_END, 269 }; 270 271 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 272 /* 273 * Page size not being supported at Stage-2 is not fatal. You 274 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 275 * your favourite nesting hypervisor. 276 * 277 * There is a small corner case where the hypervisor explicitly 278 * advertises a given granule size at Stage-2 (value 2) on some 279 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 280 * vCPUs. Although this is not forbidden by the architecture, it 281 * indicates that the hypervisor is being silly (or buggy). 282 * 283 * We make no effort to cope with this and pretend that if these 284 * fields are inconsistent across vCPUs, then it isn't worth 285 * trying to bring KVM up. 286 */ 287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 290 /* 291 * We already refuse to boot CPUs that don't support our configured 292 * page size, so we can only detect mismatches for a page size other 293 * than the one we're currently using. Unfortunately, SoCs like this 294 * exist in the wild so, even though we don't like it, we'll have to go 295 * along with it and treat them as non-strict. 296 */ 297 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 298 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 300 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 302 /* Linux shouldn't care about secure memory */ 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 306 /* 307 * Differing PARange is fine as long as all peripherals and memory are mapped 308 * within the minimum PARange of all CPUs 309 */ 310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 311 ARM64_FTR_END, 312 }; 313 314 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 321 ARM64_FTR_END, 322 }; 323 324 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 327 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 333 ARM64_FTR_END, 334 }; 335 336 static const struct arm64_ftr_bits ftr_ctr[] = { 337 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 338 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 339 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 340 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 341 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 342 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 343 /* 344 * Linux can handle differing I-cache policies. Userspace JITs will 345 * make use of *minLine. 346 * If we have differing I-cache policies, report it as the weakest - VIPT. 347 */ 348 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 349 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 350 ARM64_FTR_END, 351 }; 352 353 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 354 .name = "SYS_CTR_EL0", 355 .ftr_bits = ftr_ctr 356 }; 357 358 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 359 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */ 360 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */ 361 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */ 362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */ 363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */ 364 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */ 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */ 366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */ 367 ARM64_FTR_END, 368 }; 369 370 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 371 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 36, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 376 /* 377 * We can instantiate multiple PMU instances with different levels 378 * of support. 379 */ 380 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), 382 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 383 ARM64_FTR_END, 384 }; 385 386 static const struct arm64_ftr_bits ftr_mvfr2[] = { 387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */ 388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */ 389 ARM64_FTR_END, 390 }; 391 392 static const struct arm64_ftr_bits ftr_dczid[] = { 393 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */ 394 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */ 395 ARM64_FTR_END, 396 }; 397 398 static const struct arm64_ftr_bits ftr_id_isar0[] = { 399 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 401 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 403 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 406 ARM64_FTR_END, 407 }; 408 409 static const struct arm64_ftr_bits ftr_id_isar5[] = { 410 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 411 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 416 ARM64_FTR_END, 417 }; 418 419 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 423 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */ 427 /* 428 * SpecSEI = 1 indicates that the PE might generate an SError on an 429 * external abort on speculative read. It is safe to assume that an 430 * SError might be generated than it will not be. Hence it has been 431 * classified as FTR_HIGHER_SAFE. 432 */ 433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 434 ARM64_FTR_END, 435 }; 436 437 static const struct arm64_ftr_bits ftr_id_isar4[] = { 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 446 ARM64_FTR_END, 447 }; 448 449 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 451 ARM64_FTR_END, 452 }; 453 454 static const struct arm64_ftr_bits ftr_id_isar6[] = { 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 462 ARM64_FTR_END, 463 }; 464 465 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */ 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */ 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */ 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */ 472 ARM64_FTR_END, 473 }; 474 475 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 484 ARM64_FTR_END, 485 }; 486 487 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 490 ARM64_FTR_END, 491 }; 492 493 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 494 /* [31:28] TraceFilt */ 495 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 502 ARM64_FTR_END, 503 }; 504 505 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 506 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 507 ARM64_FTR_END, 508 }; 509 510 static const struct arm64_ftr_bits ftr_zcr[] = { 511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 512 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 513 ARM64_FTR_END, 514 }; 515 516 /* 517 * Common ftr bits for a 32bit register with all hidden, strict 518 * attributes, with 4bit feature fields and a default safe value of 519 * 0. Covers the following 32bit registers: 520 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 521 */ 522 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 523 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 524 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 531 ARM64_FTR_END, 532 }; 533 534 /* Table for a single 32bit feature value */ 535 static const struct arm64_ftr_bits ftr_single32[] = { 536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 537 ARM64_FTR_END, 538 }; 539 540 static const struct arm64_ftr_bits ftr_raz[] = { 541 ARM64_FTR_END, 542 }; 543 544 #define ARM64_FTR_REG(id, table) { \ 545 .sys_id = id, \ 546 .reg = &(struct arm64_ftr_reg){ \ 547 .name = #id, \ 548 .ftr_bits = &((table)[0]), \ 549 }} 550 551 static const struct __ftr_reg_entry { 552 u32 sys_id; 553 struct arm64_ftr_reg *reg; 554 } arm64_ftr_regs[] = { 555 556 /* Op1 = 0, CRn = 0, CRm = 1 */ 557 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 558 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 559 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 560 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 561 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 562 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 563 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 564 565 /* Op1 = 0, CRn = 0, CRm = 2 */ 566 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 567 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 568 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 569 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 570 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 571 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 572 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 573 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 574 575 /* Op1 = 0, CRn = 0, CRm = 3 */ 576 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 577 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 578 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 579 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 580 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 581 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 582 583 /* Op1 = 0, CRn = 0, CRm = 4 */ 584 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 585 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1), 586 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 587 588 /* Op1 = 0, CRn = 0, CRm = 5 */ 589 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 590 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 591 592 /* Op1 = 0, CRn = 0, CRm = 6 */ 593 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 594 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), 595 596 /* Op1 = 0, CRn = 0, CRm = 7 */ 597 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 598 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), 599 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 600 601 /* Op1 = 0, CRn = 1, CRm = 2 */ 602 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 603 604 /* Op1 = 3, CRn = 0, CRm = 0 */ 605 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 606 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 607 608 /* Op1 = 3, CRn = 14, CRm = 0 */ 609 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 610 }; 611 612 static int search_cmp_ftr_reg(const void *id, const void *regp) 613 { 614 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 615 } 616 617 /* 618 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 619 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 620 * ascending order of sys_id, we use binary search to find a matching 621 * entry. 622 * 623 * returns - Upon success, matching ftr_reg entry for id. 624 * - NULL on failure. It is upto the caller to decide 625 * the impact of a failure. 626 */ 627 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 628 { 629 const struct __ftr_reg_entry *ret; 630 631 ret = bsearch((const void *)(unsigned long)sys_id, 632 arm64_ftr_regs, 633 ARRAY_SIZE(arm64_ftr_regs), 634 sizeof(arm64_ftr_regs[0]), 635 search_cmp_ftr_reg); 636 if (ret) 637 return ret->reg; 638 return NULL; 639 } 640 641 /* 642 * get_arm64_ftr_reg - Looks up a feature register entry using 643 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 644 * 645 * returns - Upon success, matching ftr_reg entry for id. 646 * - NULL on failure but with an WARN_ON(). 647 */ 648 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 649 { 650 struct arm64_ftr_reg *reg; 651 652 reg = get_arm64_ftr_reg_nowarn(sys_id); 653 654 /* 655 * Requesting a non-existent register search is an error. Warn 656 * and let the caller handle it. 657 */ 658 WARN_ON(!reg); 659 return reg; 660 } 661 662 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 663 s64 ftr_val) 664 { 665 u64 mask = arm64_ftr_mask(ftrp); 666 667 reg &= ~mask; 668 reg |= (ftr_val << ftrp->shift) & mask; 669 return reg; 670 } 671 672 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 673 s64 cur) 674 { 675 s64 ret = 0; 676 677 switch (ftrp->type) { 678 case FTR_EXACT: 679 ret = ftrp->safe_val; 680 break; 681 case FTR_LOWER_SAFE: 682 ret = new < cur ? new : cur; 683 break; 684 case FTR_HIGHER_OR_ZERO_SAFE: 685 if (!cur || !new) 686 break; 687 /* Fallthrough */ 688 case FTR_HIGHER_SAFE: 689 ret = new > cur ? new : cur; 690 break; 691 default: 692 BUG(); 693 } 694 695 return ret; 696 } 697 698 static void __init sort_ftr_regs(void) 699 { 700 int i; 701 702 /* Check that the array is sorted so that we can do the binary search */ 703 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++) 704 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 705 } 706 707 /* 708 * Initialise the CPU feature register from Boot CPU values. 709 * Also initiliases the strict_mask for the register. 710 * Any bits that are not covered by an arm64_ftr_bits entry are considered 711 * RES0 for the system-wide value, and must strictly match. 712 */ 713 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 714 { 715 u64 val = 0; 716 u64 strict_mask = ~0x0ULL; 717 u64 user_mask = 0; 718 u64 valid_mask = 0; 719 720 const struct arm64_ftr_bits *ftrp; 721 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 722 723 if (!reg) 724 return; 725 726 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 727 u64 ftr_mask = arm64_ftr_mask(ftrp); 728 s64 ftr_new = arm64_ftr_value(ftrp, new); 729 730 val = arm64_ftr_set_value(ftrp, val, ftr_new); 731 732 valid_mask |= ftr_mask; 733 if (!ftrp->strict) 734 strict_mask &= ~ftr_mask; 735 if (ftrp->visible) 736 user_mask |= ftr_mask; 737 else 738 reg->user_val = arm64_ftr_set_value(ftrp, 739 reg->user_val, 740 ftrp->safe_val); 741 } 742 743 val &= valid_mask; 744 745 reg->sys_val = val; 746 reg->strict_mask = strict_mask; 747 reg->user_mask = user_mask; 748 } 749 750 extern const struct arm64_cpu_capabilities arm64_errata[]; 751 static const struct arm64_cpu_capabilities arm64_features[]; 752 753 static void __init 754 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 755 { 756 for (; caps->matches; caps++) { 757 if (WARN(caps->capability >= ARM64_NCAPS, 758 "Invalid capability %d\n", caps->capability)) 759 continue; 760 if (WARN(cpu_hwcaps_ptrs[caps->capability], 761 "Duplicate entry for capability %d\n", 762 caps->capability)) 763 continue; 764 cpu_hwcaps_ptrs[caps->capability] = caps; 765 } 766 } 767 768 static void __init init_cpu_hwcaps_indirect_list(void) 769 { 770 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 771 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 772 } 773 774 static void __init setup_boot_cpu_capabilities(void); 775 776 void __init init_cpu_features(struct cpuinfo_arm64 *info) 777 { 778 /* Before we start using the tables, make sure it is sorted */ 779 sort_ftr_regs(); 780 781 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 782 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 783 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 784 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 785 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 786 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 787 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 788 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 789 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 790 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 791 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 792 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 793 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 794 795 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 796 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 797 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 798 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 799 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 800 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 801 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 802 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 803 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 804 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 805 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 806 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 807 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 808 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 809 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 810 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 811 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 812 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 813 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 814 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 815 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 816 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 817 } 818 819 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 820 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 821 sve_init_vq_map(); 822 } 823 824 /* 825 * Initialize the indirect array of CPU hwcaps capabilities pointers 826 * before we handle the boot CPU below. 827 */ 828 init_cpu_hwcaps_indirect_list(); 829 830 /* 831 * Detect and enable early CPU capabilities based on the boot CPU, 832 * after we have initialised the CPU feature infrastructure. 833 */ 834 setup_boot_cpu_capabilities(); 835 } 836 837 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 838 { 839 const struct arm64_ftr_bits *ftrp; 840 841 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 842 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 843 s64 ftr_new = arm64_ftr_value(ftrp, new); 844 845 if (ftr_cur == ftr_new) 846 continue; 847 /* Find a safe value */ 848 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 849 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 850 } 851 852 } 853 854 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 855 { 856 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 857 858 if (!regp) 859 return 0; 860 861 update_cpu_ftr_reg(regp, val); 862 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 863 return 0; 864 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 865 regp->name, boot, cpu, val); 866 return 1; 867 } 868 869 static void relax_cpu_ftr_reg(u32 sys_id, int field) 870 { 871 const struct arm64_ftr_bits *ftrp; 872 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 873 874 if (!regp) 875 return; 876 877 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 878 if (ftrp->shift == field) { 879 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 880 break; 881 } 882 } 883 884 /* Bogus field? */ 885 WARN_ON(!ftrp->width); 886 } 887 888 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info, 889 struct cpuinfo_arm64 *boot) 890 { 891 int taint = 0; 892 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 893 894 /* 895 * If we don't have AArch32 at all then skip the checks entirely 896 * as the register values may be UNKNOWN and we're not going to be 897 * using them for anything. 898 */ 899 if (!id_aa64pfr0_32bit_el0(pfr0)) 900 return taint; 901 902 /* 903 * If we don't have AArch32 at EL1, then relax the strictness of 904 * EL1-dependent register fields to avoid spurious sanity check fails. 905 */ 906 if (!id_aa64pfr0_32bit_el1(pfr0)) { 907 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 908 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 909 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 910 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 911 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 912 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 913 } 914 915 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 916 info->reg_id_dfr0, boot->reg_id_dfr0); 917 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 918 info->reg_id_dfr1, boot->reg_id_dfr1); 919 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 920 info->reg_id_isar0, boot->reg_id_isar0); 921 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 922 info->reg_id_isar1, boot->reg_id_isar1); 923 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 924 info->reg_id_isar2, boot->reg_id_isar2); 925 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 926 info->reg_id_isar3, boot->reg_id_isar3); 927 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 928 info->reg_id_isar4, boot->reg_id_isar4); 929 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 930 info->reg_id_isar5, boot->reg_id_isar5); 931 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 932 info->reg_id_isar6, boot->reg_id_isar6); 933 934 /* 935 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 936 * ACTLR formats could differ across CPUs and therefore would have to 937 * be trapped for virtualization anyway. 938 */ 939 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 940 info->reg_id_mmfr0, boot->reg_id_mmfr0); 941 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 942 info->reg_id_mmfr1, boot->reg_id_mmfr1); 943 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 944 info->reg_id_mmfr2, boot->reg_id_mmfr2); 945 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 946 info->reg_id_mmfr3, boot->reg_id_mmfr3); 947 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 948 info->reg_id_mmfr4, boot->reg_id_mmfr4); 949 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 950 info->reg_id_mmfr5, boot->reg_id_mmfr5); 951 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 952 info->reg_id_pfr0, boot->reg_id_pfr0); 953 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 954 info->reg_id_pfr1, boot->reg_id_pfr1); 955 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 956 info->reg_id_pfr2, boot->reg_id_pfr2); 957 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 958 info->reg_mvfr0, boot->reg_mvfr0); 959 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 960 info->reg_mvfr1, boot->reg_mvfr1); 961 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 962 info->reg_mvfr2, boot->reg_mvfr2); 963 964 return taint; 965 } 966 967 /* 968 * Update system wide CPU feature registers with the values from a 969 * non-boot CPU. Also performs SANITY checks to make sure that there 970 * aren't any insane variations from that of the boot CPU. 971 */ 972 void update_cpu_features(int cpu, 973 struct cpuinfo_arm64 *info, 974 struct cpuinfo_arm64 *boot) 975 { 976 int taint = 0; 977 978 /* 979 * The kernel can handle differing I-cache policies, but otherwise 980 * caches should look identical. Userspace JITs will make use of 981 * *minLine. 982 */ 983 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 984 info->reg_ctr, boot->reg_ctr); 985 986 /* 987 * Userspace may perform DC ZVA instructions. Mismatched block sizes 988 * could result in too much or too little memory being zeroed if a 989 * process is preempted and migrated between CPUs. 990 */ 991 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 992 info->reg_dczid, boot->reg_dczid); 993 994 /* If different, timekeeping will be broken (especially with KVM) */ 995 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 996 info->reg_cntfrq, boot->reg_cntfrq); 997 998 /* 999 * The kernel uses self-hosted debug features and expects CPUs to 1000 * support identical debug features. We presently need CTX_CMPs, WRPs, 1001 * and BRPs to be identical. 1002 * ID_AA64DFR1 is currently RES0. 1003 */ 1004 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1005 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1006 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1007 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1008 /* 1009 * Even in big.LITTLE, processors should be identical instruction-set 1010 * wise. 1011 */ 1012 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1013 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1014 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1015 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1016 1017 /* 1018 * Differing PARange support is fine as long as all peripherals and 1019 * memory are mapped within the minimum PARange of all CPUs. 1020 * Linux should not care about secure memory. 1021 */ 1022 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1023 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1024 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1025 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1026 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1027 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1028 1029 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1030 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1031 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1032 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1033 1034 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1035 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1036 1037 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 1038 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1039 info->reg_zcr, boot->reg_zcr); 1040 1041 /* Probe vector lengths, unless we already gave up on SVE */ 1042 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 1043 !system_capabilities_finalized()) 1044 sve_update_vq_map(); 1045 } 1046 1047 /* 1048 * This relies on a sanitised view of the AArch64 ID registers 1049 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1050 */ 1051 taint |= update_32bit_cpu_features(cpu, info, boot); 1052 1053 /* 1054 * Mismatched CPU features are a recipe for disaster. Don't even 1055 * pretend to support them. 1056 */ 1057 if (taint) { 1058 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1059 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1060 } 1061 } 1062 1063 u64 read_sanitised_ftr_reg(u32 id) 1064 { 1065 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1066 1067 if (!regp) 1068 return 0; 1069 return regp->sys_val; 1070 } 1071 1072 #define read_sysreg_case(r) \ 1073 case r: return read_sysreg_s(r) 1074 1075 /* 1076 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1077 * Read the system register on the current CPU 1078 */ 1079 static u64 __read_sysreg_by_encoding(u32 sys_id) 1080 { 1081 switch (sys_id) { 1082 read_sysreg_case(SYS_ID_PFR0_EL1); 1083 read_sysreg_case(SYS_ID_PFR1_EL1); 1084 read_sysreg_case(SYS_ID_PFR2_EL1); 1085 read_sysreg_case(SYS_ID_DFR0_EL1); 1086 read_sysreg_case(SYS_ID_DFR1_EL1); 1087 read_sysreg_case(SYS_ID_MMFR0_EL1); 1088 read_sysreg_case(SYS_ID_MMFR1_EL1); 1089 read_sysreg_case(SYS_ID_MMFR2_EL1); 1090 read_sysreg_case(SYS_ID_MMFR3_EL1); 1091 read_sysreg_case(SYS_ID_MMFR4_EL1); 1092 read_sysreg_case(SYS_ID_MMFR5_EL1); 1093 read_sysreg_case(SYS_ID_ISAR0_EL1); 1094 read_sysreg_case(SYS_ID_ISAR1_EL1); 1095 read_sysreg_case(SYS_ID_ISAR2_EL1); 1096 read_sysreg_case(SYS_ID_ISAR3_EL1); 1097 read_sysreg_case(SYS_ID_ISAR4_EL1); 1098 read_sysreg_case(SYS_ID_ISAR5_EL1); 1099 read_sysreg_case(SYS_ID_ISAR6_EL1); 1100 read_sysreg_case(SYS_MVFR0_EL1); 1101 read_sysreg_case(SYS_MVFR1_EL1); 1102 read_sysreg_case(SYS_MVFR2_EL1); 1103 1104 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1105 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1106 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1107 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1108 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1109 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1110 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1111 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1112 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1113 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1114 1115 read_sysreg_case(SYS_CNTFRQ_EL0); 1116 read_sysreg_case(SYS_CTR_EL0); 1117 read_sysreg_case(SYS_DCZID_EL0); 1118 1119 default: 1120 BUG(); 1121 return 0; 1122 } 1123 } 1124 1125 #include <linux/irqchip/arm-gic-v3.h> 1126 1127 static bool 1128 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1129 { 1130 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 1131 1132 return val >= entry->min_field_value; 1133 } 1134 1135 static bool 1136 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1137 { 1138 u64 val; 1139 1140 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1141 if (scope == SCOPE_SYSTEM) 1142 val = read_sanitised_ftr_reg(entry->sys_reg); 1143 else 1144 val = __read_sysreg_by_encoding(entry->sys_reg); 1145 1146 return feature_matches(val, entry); 1147 } 1148 1149 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1150 { 1151 bool has_sre; 1152 1153 if (!has_cpuid_feature(entry, scope)) 1154 return false; 1155 1156 has_sre = gic_enable_sre(); 1157 if (!has_sre) 1158 pr_warn_once("%s present but disabled by higher exception level\n", 1159 entry->desc); 1160 1161 return has_sre; 1162 } 1163 1164 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1165 { 1166 u32 midr = read_cpuid_id(); 1167 1168 /* Cavium ThunderX pass 1.x and 2.x */ 1169 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1170 MIDR_CPU_VAR_REV(0, 0), 1171 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1172 } 1173 1174 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1175 { 1176 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1177 1178 return cpuid_feature_extract_signed_field(pfr0, 1179 ID_AA64PFR0_FP_SHIFT) < 0; 1180 } 1181 1182 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1183 int scope) 1184 { 1185 u64 ctr; 1186 1187 if (scope == SCOPE_SYSTEM) 1188 ctr = arm64_ftr_reg_ctrel0.sys_val; 1189 else 1190 ctr = read_cpuid_effective_cachetype(); 1191 1192 return ctr & BIT(CTR_IDC_SHIFT); 1193 } 1194 1195 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1196 { 1197 /* 1198 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1199 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1200 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1201 * value. 1202 */ 1203 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 1204 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1205 } 1206 1207 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1208 int scope) 1209 { 1210 u64 ctr; 1211 1212 if (scope == SCOPE_SYSTEM) 1213 ctr = arm64_ftr_reg_ctrel0.sys_val; 1214 else 1215 ctr = read_cpuid_cachetype(); 1216 1217 return ctr & BIT(CTR_DIC_SHIFT); 1218 } 1219 1220 static bool __maybe_unused 1221 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1222 { 1223 /* 1224 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1225 * may share TLB entries with a CPU stuck in the crashed 1226 * kernel. 1227 */ 1228 if (is_kdump_kernel()) 1229 return false; 1230 1231 return has_cpuid_feature(entry, scope); 1232 } 1233 1234 /* 1235 * This check is triggered during the early boot before the cpufeature 1236 * is initialised. Checking the status on the local CPU allows the boot 1237 * CPU to detect the need for non-global mappings and thus avoiding a 1238 * pagetable re-write after all the CPUs are booted. This check will be 1239 * anyway run on individual CPUs, allowing us to get the consistent 1240 * state once the SMP CPUs are up and thus make the switch to non-global 1241 * mappings if required. 1242 */ 1243 bool kaslr_requires_kpti(void) 1244 { 1245 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1246 return false; 1247 1248 /* 1249 * E0PD does a similar job to KPTI so can be used instead 1250 * where available. 1251 */ 1252 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1253 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1254 if (cpuid_feature_extract_unsigned_field(mmfr2, 1255 ID_AA64MMFR2_E0PD_SHIFT)) 1256 return false; 1257 } 1258 1259 /* 1260 * Systems affected by Cavium erratum 24756 are incompatible 1261 * with KPTI. 1262 */ 1263 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1264 extern const struct midr_range cavium_erratum_27456_cpus[]; 1265 1266 if (is_midr_in_range_list(read_cpuid_id(), 1267 cavium_erratum_27456_cpus)) 1268 return false; 1269 } 1270 1271 return kaslr_offset() > 0; 1272 } 1273 1274 static bool __meltdown_safe = true; 1275 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1276 1277 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1278 int scope) 1279 { 1280 /* List of CPUs that are not vulnerable and don't need KPTI */ 1281 static const struct midr_range kpti_safe_list[] = { 1282 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1283 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1284 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1285 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1286 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1287 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1288 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1289 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1290 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1291 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1292 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1293 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1294 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1295 { /* sentinel */ } 1296 }; 1297 char const *str = "kpti command line option"; 1298 bool meltdown_safe; 1299 1300 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1301 1302 /* Defer to CPU feature registers */ 1303 if (has_cpuid_feature(entry, scope)) 1304 meltdown_safe = true; 1305 1306 if (!meltdown_safe) 1307 __meltdown_safe = false; 1308 1309 /* 1310 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1311 * ThunderX leads to apparent I-cache corruption of kernel text, which 1312 * ends as well as you might imagine. Don't even try. 1313 */ 1314 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1315 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1316 __kpti_forced = -1; 1317 } 1318 1319 /* Useful for KASLR robustness */ 1320 if (kaslr_requires_kpti()) { 1321 if (!__kpti_forced) { 1322 str = "KASLR"; 1323 __kpti_forced = 1; 1324 } 1325 } 1326 1327 if (cpu_mitigations_off() && !__kpti_forced) { 1328 str = "mitigations=off"; 1329 __kpti_forced = -1; 1330 } 1331 1332 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1333 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1334 return false; 1335 } 1336 1337 /* Forced? */ 1338 if (__kpti_forced) { 1339 pr_info_once("kernel page table isolation forced %s by %s\n", 1340 __kpti_forced > 0 ? "ON" : "OFF", str); 1341 return __kpti_forced > 0; 1342 } 1343 1344 return !meltdown_safe; 1345 } 1346 1347 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1348 static void 1349 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1350 { 1351 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1352 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1353 kpti_remap_fn *remap_fn; 1354 1355 int cpu = smp_processor_id(); 1356 1357 /* 1358 * We don't need to rewrite the page-tables if either we've done 1359 * it already or we have KASLR enabled and therefore have not 1360 * created any global mappings at all. 1361 */ 1362 if (arm64_use_ng_mappings) 1363 return; 1364 1365 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1366 1367 cpu_install_idmap(); 1368 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1369 cpu_uninstall_idmap(); 1370 1371 if (!cpu) 1372 arm64_use_ng_mappings = true; 1373 1374 return; 1375 } 1376 #else 1377 static void 1378 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1379 { 1380 } 1381 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1382 1383 static int __init parse_kpti(char *str) 1384 { 1385 bool enabled; 1386 int ret = strtobool(str, &enabled); 1387 1388 if (ret) 1389 return ret; 1390 1391 __kpti_forced = enabled ? 1 : -1; 1392 return 0; 1393 } 1394 early_param("kpti", parse_kpti); 1395 1396 #ifdef CONFIG_ARM64_HW_AFDBM 1397 static inline void __cpu_enable_hw_dbm(void) 1398 { 1399 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1400 1401 write_sysreg(tcr, tcr_el1); 1402 isb(); 1403 } 1404 1405 static bool cpu_has_broken_dbm(void) 1406 { 1407 /* List of CPUs which have broken DBM support. */ 1408 static const struct midr_range cpus[] = { 1409 #ifdef CONFIG_ARM64_ERRATUM_1024718 1410 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 1411 #endif 1412 {}, 1413 }; 1414 1415 return is_midr_in_range_list(read_cpuid_id(), cpus); 1416 } 1417 1418 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1419 { 1420 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1421 !cpu_has_broken_dbm(); 1422 } 1423 1424 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1425 { 1426 if (cpu_can_use_dbm(cap)) 1427 __cpu_enable_hw_dbm(); 1428 } 1429 1430 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1431 int __unused) 1432 { 1433 static bool detected = false; 1434 /* 1435 * DBM is a non-conflicting feature. i.e, the kernel can safely 1436 * run a mix of CPUs with and without the feature. So, we 1437 * unconditionally enable the capability to allow any late CPU 1438 * to use the feature. We only enable the control bits on the 1439 * CPU, if it actually supports. 1440 * 1441 * We have to make sure we print the "feature" detection only 1442 * when at least one CPU actually uses it. So check if this CPU 1443 * can actually use it and print the message exactly once. 1444 * 1445 * This is safe as all CPUs (including secondary CPUs - due to the 1446 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1447 * goes through the "matches" check exactly once. Also if a CPU 1448 * matches the criteria, it is guaranteed that the CPU will turn 1449 * the DBM on, as the capability is unconditionally enabled. 1450 */ 1451 if (!detected && cpu_can_use_dbm(cap)) { 1452 detected = true; 1453 pr_info("detected: Hardware dirty bit management\n"); 1454 } 1455 1456 return true; 1457 } 1458 1459 #endif 1460 1461 #ifdef CONFIG_ARM64_AMU_EXTN 1462 1463 /* 1464 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1465 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1466 * information regarding all the events that it supports. When a CPU bit is 1467 * set in the cpumask, the user of this feature can only rely on the presence 1468 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1469 * counters are enabled or access to these counters is enabled by code 1470 * executed at higher exception levels (firmware). 1471 */ 1472 static struct cpumask amu_cpus __read_mostly; 1473 1474 bool cpu_has_amu_feat(int cpu) 1475 { 1476 return cpumask_test_cpu(cpu, &amu_cpus); 1477 } 1478 1479 /* Initialize the use of AMU counters for frequency invariance */ 1480 extern void init_cpu_freq_invariance_counters(void); 1481 1482 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1483 { 1484 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1485 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1486 smp_processor_id()); 1487 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1488 init_cpu_freq_invariance_counters(); 1489 } 1490 } 1491 1492 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1493 int __unused) 1494 { 1495 /* 1496 * The AMU extension is a non-conflicting feature: the kernel can 1497 * safely run a mix of CPUs with and without support for the 1498 * activity monitors extension. Therefore, unconditionally enable 1499 * the capability to allow any late CPU to use the feature. 1500 * 1501 * With this feature unconditionally enabled, the cpu_enable 1502 * function will be called for all CPUs that match the criteria, 1503 * including secondary and hotplugged, marking this feature as 1504 * present on that respective CPU. The enable function will also 1505 * print a detection message. 1506 */ 1507 1508 return true; 1509 } 1510 #endif 1511 1512 #ifdef CONFIG_ARM64_VHE 1513 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1514 { 1515 return is_kernel_in_hyp_mode(); 1516 } 1517 1518 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1519 { 1520 /* 1521 * Copy register values that aren't redirected by hardware. 1522 * 1523 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1524 * this value to tpidr_el2 before we patch the code. Once we've done 1525 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1526 * do anything here. 1527 */ 1528 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1529 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1530 } 1531 #endif 1532 1533 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1534 { 1535 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1536 1537 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1538 WARN_ON(val & (7 << 27 | 7 << 21)); 1539 } 1540 1541 #ifdef CONFIG_ARM64_SSBD 1542 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr) 1543 { 1544 if (user_mode(regs)) 1545 return 1; 1546 1547 if (instr & BIT(PSTATE_Imm_shift)) 1548 regs->pstate |= PSR_SSBS_BIT; 1549 else 1550 regs->pstate &= ~PSR_SSBS_BIT; 1551 1552 arm64_skip_faulting_instruction(regs, 4); 1553 return 0; 1554 } 1555 1556 static struct undef_hook ssbs_emulation_hook = { 1557 .instr_mask = ~(1U << PSTATE_Imm_shift), 1558 .instr_val = 0xd500401f | PSTATE_SSBS, 1559 .fn = ssbs_emulation_handler, 1560 }; 1561 1562 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused) 1563 { 1564 static bool undef_hook_registered = false; 1565 static DEFINE_RAW_SPINLOCK(hook_lock); 1566 1567 raw_spin_lock(&hook_lock); 1568 if (!undef_hook_registered) { 1569 register_undef_hook(&ssbs_emulation_hook); 1570 undef_hook_registered = true; 1571 } 1572 raw_spin_unlock(&hook_lock); 1573 1574 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) { 1575 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS); 1576 arm64_set_ssbd_mitigation(false); 1577 } else { 1578 arm64_set_ssbd_mitigation(true); 1579 } 1580 } 1581 #endif /* CONFIG_ARM64_SSBD */ 1582 1583 #ifdef CONFIG_ARM64_PAN 1584 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1585 { 1586 /* 1587 * We modify PSTATE. This won't work from irq context as the PSTATE 1588 * is discarded once we return from the exception. 1589 */ 1590 WARN_ON_ONCE(in_interrupt()); 1591 1592 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1593 asm(SET_PSTATE_PAN(1)); 1594 } 1595 #endif /* CONFIG_ARM64_PAN */ 1596 1597 #ifdef CONFIG_ARM64_RAS_EXTN 1598 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1599 { 1600 /* Firmware may have left a deferred SError in this register. */ 1601 write_sysreg_s(0, SYS_DISR_EL1); 1602 } 1603 #endif /* CONFIG_ARM64_RAS_EXTN */ 1604 1605 #ifdef CONFIG_ARM64_PTR_AUTH 1606 static bool has_address_auth(const struct arm64_cpu_capabilities *entry, 1607 int __unused) 1608 { 1609 return __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_ARCH) || 1610 __system_matches_cap(ARM64_HAS_ADDRESS_AUTH_IMP_DEF); 1611 } 1612 1613 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1614 int __unused) 1615 { 1616 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) || 1617 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1618 } 1619 #endif /* CONFIG_ARM64_PTR_AUTH */ 1620 1621 #ifdef CONFIG_ARM64_E0PD 1622 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1623 { 1624 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1625 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1626 } 1627 #endif /* CONFIG_ARM64_E0PD */ 1628 1629 #ifdef CONFIG_ARM64_PSEUDO_NMI 1630 static bool enable_pseudo_nmi; 1631 1632 static int __init early_enable_pseudo_nmi(char *p) 1633 { 1634 return strtobool(p, &enable_pseudo_nmi); 1635 } 1636 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1637 1638 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1639 int scope) 1640 { 1641 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1642 } 1643 #endif 1644 1645 #ifdef CONFIG_ARM64_BTI 1646 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 1647 { 1648 /* 1649 * Use of X16/X17 for tail-calls and trampolines that jump to 1650 * function entry points using BR is a requirement for 1651 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 1652 * So, be strict and forbid other BRs using other registers to 1653 * jump onto a PACIxSP instruction: 1654 */ 1655 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 1656 isb(); 1657 } 1658 #endif /* CONFIG_ARM64_BTI */ 1659 1660 /* Internal helper functions to match cpu capability type */ 1661 static bool 1662 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1663 { 1664 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1665 } 1666 1667 static bool 1668 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1669 { 1670 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1671 } 1672 1673 static bool 1674 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 1675 { 1676 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 1677 } 1678 1679 static const struct arm64_cpu_capabilities arm64_features[] = { 1680 { 1681 .desc = "GIC system register CPU interface", 1682 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1683 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1684 .matches = has_useable_gicv3_cpuif, 1685 .sys_reg = SYS_ID_AA64PFR0_EL1, 1686 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1687 .sign = FTR_UNSIGNED, 1688 .min_field_value = 1, 1689 }, 1690 #ifdef CONFIG_ARM64_PAN 1691 { 1692 .desc = "Privileged Access Never", 1693 .capability = ARM64_HAS_PAN, 1694 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1695 .matches = has_cpuid_feature, 1696 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1697 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1698 .sign = FTR_UNSIGNED, 1699 .min_field_value = 1, 1700 .cpu_enable = cpu_enable_pan, 1701 }, 1702 #endif /* CONFIG_ARM64_PAN */ 1703 #ifdef CONFIG_ARM64_LSE_ATOMICS 1704 { 1705 .desc = "LSE atomic instructions", 1706 .capability = ARM64_HAS_LSE_ATOMICS, 1707 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1708 .matches = has_cpuid_feature, 1709 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1710 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1711 .sign = FTR_UNSIGNED, 1712 .min_field_value = 2, 1713 }, 1714 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 1715 { 1716 .desc = "Software prefetching using PRFM", 1717 .capability = ARM64_HAS_NO_HW_PREFETCH, 1718 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1719 .matches = has_no_hw_prefetch, 1720 }, 1721 #ifdef CONFIG_ARM64_UAO 1722 { 1723 .desc = "User Access Override", 1724 .capability = ARM64_HAS_UAO, 1725 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1726 .matches = has_cpuid_feature, 1727 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1728 .field_pos = ID_AA64MMFR2_UAO_SHIFT, 1729 .min_field_value = 1, 1730 /* 1731 * We rely on stop_machine() calling uao_thread_switch() to set 1732 * UAO immediately after patching. 1733 */ 1734 }, 1735 #endif /* CONFIG_ARM64_UAO */ 1736 #ifdef CONFIG_ARM64_PAN 1737 { 1738 .capability = ARM64_ALT_PAN_NOT_UAO, 1739 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1740 .matches = cpufeature_pan_not_uao, 1741 }, 1742 #endif /* CONFIG_ARM64_PAN */ 1743 #ifdef CONFIG_ARM64_VHE 1744 { 1745 .desc = "Virtualization Host Extensions", 1746 .capability = ARM64_HAS_VIRT_HOST_EXTN, 1747 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1748 .matches = runs_at_el2, 1749 .cpu_enable = cpu_copy_el2regs, 1750 }, 1751 #endif /* CONFIG_ARM64_VHE */ 1752 { 1753 .desc = "32-bit EL0 Support", 1754 .capability = ARM64_HAS_32BIT_EL0, 1755 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1756 .matches = has_cpuid_feature, 1757 .sys_reg = SYS_ID_AA64PFR0_EL1, 1758 .sign = FTR_UNSIGNED, 1759 .field_pos = ID_AA64PFR0_EL0_SHIFT, 1760 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 1761 }, 1762 #ifdef CONFIG_KVM 1763 { 1764 .desc = "32-bit EL1 Support", 1765 .capability = ARM64_HAS_32BIT_EL1, 1766 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1767 .matches = has_cpuid_feature, 1768 .sys_reg = SYS_ID_AA64PFR0_EL1, 1769 .sign = FTR_UNSIGNED, 1770 .field_pos = ID_AA64PFR0_EL1_SHIFT, 1771 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT, 1772 }, 1773 #endif 1774 { 1775 .desc = "Kernel page table isolation (KPTI)", 1776 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 1777 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1778 /* 1779 * The ID feature fields below are used to indicate that 1780 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 1781 * more details. 1782 */ 1783 .sys_reg = SYS_ID_AA64PFR0_EL1, 1784 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 1785 .min_field_value = 1, 1786 .matches = unmap_kernel_at_el0, 1787 .cpu_enable = kpti_install_ng_mappings, 1788 }, 1789 { 1790 /* FP/SIMD is not implemented */ 1791 .capability = ARM64_HAS_NO_FPSIMD, 1792 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1793 .min_field_value = 0, 1794 .matches = has_no_fpsimd, 1795 }, 1796 #ifdef CONFIG_ARM64_PMEM 1797 { 1798 .desc = "Data cache clean to Point of Persistence", 1799 .capability = ARM64_HAS_DCPOP, 1800 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1801 .matches = has_cpuid_feature, 1802 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1803 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1804 .min_field_value = 1, 1805 }, 1806 { 1807 .desc = "Data cache clean to Point of Deep Persistence", 1808 .capability = ARM64_HAS_DCPODP, 1809 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1810 .matches = has_cpuid_feature, 1811 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1812 .sign = FTR_UNSIGNED, 1813 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1814 .min_field_value = 2, 1815 }, 1816 #endif 1817 #ifdef CONFIG_ARM64_SVE 1818 { 1819 .desc = "Scalable Vector Extension", 1820 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1821 .capability = ARM64_SVE, 1822 .sys_reg = SYS_ID_AA64PFR0_EL1, 1823 .sign = FTR_UNSIGNED, 1824 .field_pos = ID_AA64PFR0_SVE_SHIFT, 1825 .min_field_value = ID_AA64PFR0_SVE, 1826 .matches = has_cpuid_feature, 1827 .cpu_enable = sve_kernel_enable, 1828 }, 1829 #endif /* CONFIG_ARM64_SVE */ 1830 #ifdef CONFIG_ARM64_RAS_EXTN 1831 { 1832 .desc = "RAS Extension Support", 1833 .capability = ARM64_HAS_RAS_EXTN, 1834 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1835 .matches = has_cpuid_feature, 1836 .sys_reg = SYS_ID_AA64PFR0_EL1, 1837 .sign = FTR_UNSIGNED, 1838 .field_pos = ID_AA64PFR0_RAS_SHIFT, 1839 .min_field_value = ID_AA64PFR0_RAS_V1, 1840 .cpu_enable = cpu_clear_disr, 1841 }, 1842 #endif /* CONFIG_ARM64_RAS_EXTN */ 1843 #ifdef CONFIG_ARM64_AMU_EXTN 1844 { 1845 /* 1846 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 1847 * Therefore, don't provide .desc as we don't want the detection 1848 * message to be shown until at least one CPU is detected to 1849 * support the feature. 1850 */ 1851 .capability = ARM64_HAS_AMU_EXTN, 1852 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1853 .matches = has_amu, 1854 .sys_reg = SYS_ID_AA64PFR0_EL1, 1855 .sign = FTR_UNSIGNED, 1856 .field_pos = ID_AA64PFR0_AMU_SHIFT, 1857 .min_field_value = ID_AA64PFR0_AMU, 1858 .cpu_enable = cpu_amu_enable, 1859 }, 1860 #endif /* CONFIG_ARM64_AMU_EXTN */ 1861 { 1862 .desc = "Data cache clean to the PoU not required for I/D coherence", 1863 .capability = ARM64_HAS_CACHE_IDC, 1864 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1865 .matches = has_cache_idc, 1866 .cpu_enable = cpu_emulate_effective_ctr, 1867 }, 1868 { 1869 .desc = "Instruction cache invalidation not required for I/D coherence", 1870 .capability = ARM64_HAS_CACHE_DIC, 1871 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1872 .matches = has_cache_dic, 1873 }, 1874 { 1875 .desc = "Stage-2 Force Write-Back", 1876 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1877 .capability = ARM64_HAS_STAGE2_FWB, 1878 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1879 .sign = FTR_UNSIGNED, 1880 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 1881 .min_field_value = 1, 1882 .matches = has_cpuid_feature, 1883 .cpu_enable = cpu_has_fwb, 1884 }, 1885 #ifdef CONFIG_ARM64_HW_AFDBM 1886 { 1887 /* 1888 * Since we turn this on always, we don't want the user to 1889 * think that the feature is available when it may not be. 1890 * So hide the description. 1891 * 1892 * .desc = "Hardware pagetable Dirty Bit Management", 1893 * 1894 */ 1895 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1896 .capability = ARM64_HW_DBM, 1897 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1898 .sign = FTR_UNSIGNED, 1899 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 1900 .min_field_value = 2, 1901 .matches = has_hw_dbm, 1902 .cpu_enable = cpu_enable_hw_dbm, 1903 }, 1904 #endif 1905 { 1906 .desc = "CRC32 instructions", 1907 .capability = ARM64_HAS_CRC32, 1908 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1909 .matches = has_cpuid_feature, 1910 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1911 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 1912 .min_field_value = 1, 1913 }, 1914 #ifdef CONFIG_ARM64_SSBD 1915 { 1916 .desc = "Speculative Store Bypassing Safe (SSBS)", 1917 .capability = ARM64_SSBS, 1918 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1919 .matches = has_cpuid_feature, 1920 .sys_reg = SYS_ID_AA64PFR1_EL1, 1921 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 1922 .sign = FTR_UNSIGNED, 1923 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 1924 .cpu_enable = cpu_enable_ssbs, 1925 }, 1926 #endif 1927 #ifdef CONFIG_ARM64_CNP 1928 { 1929 .desc = "Common not Private translations", 1930 .capability = ARM64_HAS_CNP, 1931 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1932 .matches = has_useable_cnp, 1933 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1934 .sign = FTR_UNSIGNED, 1935 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 1936 .min_field_value = 1, 1937 .cpu_enable = cpu_enable_cnp, 1938 }, 1939 #endif 1940 { 1941 .desc = "Speculation barrier (SB)", 1942 .capability = ARM64_HAS_SB, 1943 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1944 .matches = has_cpuid_feature, 1945 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1946 .field_pos = ID_AA64ISAR1_SB_SHIFT, 1947 .sign = FTR_UNSIGNED, 1948 .min_field_value = 1, 1949 }, 1950 #ifdef CONFIG_ARM64_PTR_AUTH 1951 { 1952 .desc = "Address authentication (architected algorithm)", 1953 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 1954 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 1955 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1956 .sign = FTR_UNSIGNED, 1957 .field_pos = ID_AA64ISAR1_APA_SHIFT, 1958 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 1959 .matches = has_cpuid_feature, 1960 }, 1961 { 1962 .desc = "Address authentication (IMP DEF algorithm)", 1963 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 1964 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 1965 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1966 .sign = FTR_UNSIGNED, 1967 .field_pos = ID_AA64ISAR1_API_SHIFT, 1968 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 1969 .matches = has_cpuid_feature, 1970 }, 1971 { 1972 .capability = ARM64_HAS_ADDRESS_AUTH, 1973 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 1974 .matches = has_address_auth, 1975 }, 1976 { 1977 .desc = "Generic authentication (architected algorithm)", 1978 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 1979 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1980 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1981 .sign = FTR_UNSIGNED, 1982 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 1983 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 1984 .matches = has_cpuid_feature, 1985 }, 1986 { 1987 .desc = "Generic authentication (IMP DEF algorithm)", 1988 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 1989 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1990 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1991 .sign = FTR_UNSIGNED, 1992 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 1993 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 1994 .matches = has_cpuid_feature, 1995 }, 1996 { 1997 .capability = ARM64_HAS_GENERIC_AUTH, 1998 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1999 .matches = has_generic_auth, 2000 }, 2001 #endif /* CONFIG_ARM64_PTR_AUTH */ 2002 #ifdef CONFIG_ARM64_PSEUDO_NMI 2003 { 2004 /* 2005 * Depends on having GICv3 2006 */ 2007 .desc = "IRQ priority masking", 2008 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2009 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2010 .matches = can_use_gic_priorities, 2011 .sys_reg = SYS_ID_AA64PFR0_EL1, 2012 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2013 .sign = FTR_UNSIGNED, 2014 .min_field_value = 1, 2015 }, 2016 #endif 2017 #ifdef CONFIG_ARM64_E0PD 2018 { 2019 .desc = "E0PD", 2020 .capability = ARM64_HAS_E0PD, 2021 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2022 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2023 .sign = FTR_UNSIGNED, 2024 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2025 .matches = has_cpuid_feature, 2026 .min_field_value = 1, 2027 .cpu_enable = cpu_enable_e0pd, 2028 }, 2029 #endif 2030 #ifdef CONFIG_ARCH_RANDOM 2031 { 2032 .desc = "Random Number Generator", 2033 .capability = ARM64_HAS_RNG, 2034 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2035 .matches = has_cpuid_feature, 2036 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2037 .field_pos = ID_AA64ISAR0_RNDR_SHIFT, 2038 .sign = FTR_UNSIGNED, 2039 .min_field_value = 1, 2040 }, 2041 #endif 2042 #ifdef CONFIG_ARM64_BTI 2043 { 2044 .desc = "Branch Target Identification", 2045 .capability = ARM64_BTI, 2046 #ifdef CONFIG_ARM64_BTI_KERNEL 2047 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2048 #else 2049 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2050 #endif 2051 .matches = has_cpuid_feature, 2052 .cpu_enable = bti_enable, 2053 .sys_reg = SYS_ID_AA64PFR1_EL1, 2054 .field_pos = ID_AA64PFR1_BT_SHIFT, 2055 .min_field_value = ID_AA64PFR1_BT_BTI, 2056 .sign = FTR_UNSIGNED, 2057 }, 2058 #endif 2059 {}, 2060 }; 2061 2062 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2063 .matches = has_cpuid_feature, \ 2064 .sys_reg = reg, \ 2065 .field_pos = field, \ 2066 .sign = s, \ 2067 .min_field_value = min_value, 2068 2069 #define __HWCAP_CAP(name, cap_type, cap) \ 2070 .desc = name, \ 2071 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2072 .hwcap_type = cap_type, \ 2073 .hwcap = cap, \ 2074 2075 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 2076 { \ 2077 __HWCAP_CAP(#cap, cap_type, cap) \ 2078 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2079 } 2080 2081 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2082 { \ 2083 __HWCAP_CAP(#cap, cap_type, cap) \ 2084 .matches = cpucap_multi_entry_cap_matches, \ 2085 .match_list = list, \ 2086 } 2087 2088 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2089 { \ 2090 __HWCAP_CAP(#cap, cap_type, cap) \ 2091 .matches = match, \ 2092 } 2093 2094 #ifdef CONFIG_ARM64_PTR_AUTH 2095 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2096 { 2097 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 2098 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 2099 }, 2100 { 2101 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 2102 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 2103 }, 2104 {}, 2105 }; 2106 2107 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2108 { 2109 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 2110 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 2111 }, 2112 { 2113 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 2114 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 2115 }, 2116 {}, 2117 }; 2118 #endif 2119 2120 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2121 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2122 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2123 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2124 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2125 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2126 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2127 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2128 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2129 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2130 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2131 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2132 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2133 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2134 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2135 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2136 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2137 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2138 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2139 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2140 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2141 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2142 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2143 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2144 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2145 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2146 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2147 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2148 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2149 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2150 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2151 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2152 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2153 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2154 #ifdef CONFIG_ARM64_SVE 2155 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2156 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2157 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2158 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2159 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2160 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2161 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2162 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2163 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2164 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2165 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2166 #endif 2167 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2168 #ifdef CONFIG_ARM64_BTI 2169 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2170 #endif 2171 #ifdef CONFIG_ARM64_PTR_AUTH 2172 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2173 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2174 #endif 2175 {}, 2176 }; 2177 2178 #ifdef CONFIG_COMPAT 2179 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2180 { 2181 /* 2182 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2183 * in line with that of arm32 as in vfp_init(). We make sure that the 2184 * check is future proof, by making sure value is non-zero. 2185 */ 2186 u32 mvfr1; 2187 2188 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2189 if (scope == SCOPE_SYSTEM) 2190 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2191 else 2192 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2193 2194 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2195 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2196 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2197 } 2198 #endif 2199 2200 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2201 #ifdef CONFIG_COMPAT 2202 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2203 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2204 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2205 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2206 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2207 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2208 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2209 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2210 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2211 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2212 #endif 2213 {}, 2214 }; 2215 2216 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2217 { 2218 switch (cap->hwcap_type) { 2219 case CAP_HWCAP: 2220 cpu_set_feature(cap->hwcap); 2221 break; 2222 #ifdef CONFIG_COMPAT 2223 case CAP_COMPAT_HWCAP: 2224 compat_elf_hwcap |= (u32)cap->hwcap; 2225 break; 2226 case CAP_COMPAT_HWCAP2: 2227 compat_elf_hwcap2 |= (u32)cap->hwcap; 2228 break; 2229 #endif 2230 default: 2231 WARN_ON(1); 2232 break; 2233 } 2234 } 2235 2236 /* Check if we have a particular HWCAP enabled */ 2237 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2238 { 2239 bool rc; 2240 2241 switch (cap->hwcap_type) { 2242 case CAP_HWCAP: 2243 rc = cpu_have_feature(cap->hwcap); 2244 break; 2245 #ifdef CONFIG_COMPAT 2246 case CAP_COMPAT_HWCAP: 2247 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2248 break; 2249 case CAP_COMPAT_HWCAP2: 2250 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2251 break; 2252 #endif 2253 default: 2254 WARN_ON(1); 2255 rc = false; 2256 } 2257 2258 return rc; 2259 } 2260 2261 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2262 { 2263 /* We support emulation of accesses to CPU ID feature registers */ 2264 cpu_set_named_feature(CPUID); 2265 for (; hwcaps->matches; hwcaps++) 2266 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2267 cap_set_elf_hwcap(hwcaps); 2268 } 2269 2270 static void update_cpu_capabilities(u16 scope_mask) 2271 { 2272 int i; 2273 const struct arm64_cpu_capabilities *caps; 2274 2275 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2276 for (i = 0; i < ARM64_NCAPS; i++) { 2277 caps = cpu_hwcaps_ptrs[i]; 2278 if (!caps || !(caps->type & scope_mask) || 2279 cpus_have_cap(caps->capability) || 2280 !caps->matches(caps, cpucap_default_scope(caps))) 2281 continue; 2282 2283 if (caps->desc) 2284 pr_info("detected: %s\n", caps->desc); 2285 cpus_set_cap(caps->capability); 2286 2287 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2288 set_bit(caps->capability, boot_capabilities); 2289 } 2290 } 2291 2292 /* 2293 * Enable all the available capabilities on this CPU. The capabilities 2294 * with BOOT_CPU scope are handled separately and hence skipped here. 2295 */ 2296 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2297 { 2298 int i; 2299 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2300 2301 for_each_available_cap(i) { 2302 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2303 2304 if (WARN_ON(!cap)) 2305 continue; 2306 2307 if (!(cap->type & non_boot_scope)) 2308 continue; 2309 2310 if (cap->cpu_enable) 2311 cap->cpu_enable(cap); 2312 } 2313 return 0; 2314 } 2315 2316 /* 2317 * Run through the enabled capabilities and enable() it on all active 2318 * CPUs 2319 */ 2320 static void __init enable_cpu_capabilities(u16 scope_mask) 2321 { 2322 int i; 2323 const struct arm64_cpu_capabilities *caps; 2324 bool boot_scope; 2325 2326 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2327 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2328 2329 for (i = 0; i < ARM64_NCAPS; i++) { 2330 unsigned int num; 2331 2332 caps = cpu_hwcaps_ptrs[i]; 2333 if (!caps || !(caps->type & scope_mask)) 2334 continue; 2335 num = caps->capability; 2336 if (!cpus_have_cap(num)) 2337 continue; 2338 2339 /* Ensure cpus_have_const_cap(num) works */ 2340 static_branch_enable(&cpu_hwcap_keys[num]); 2341 2342 if (boot_scope && caps->cpu_enable) 2343 /* 2344 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2345 * before any secondary CPU boots. Thus, each secondary 2346 * will enable the capability as appropriate via 2347 * check_local_cpu_capabilities(). The only exception is 2348 * the boot CPU, for which the capability must be 2349 * enabled here. This approach avoids costly 2350 * stop_machine() calls for this case. 2351 */ 2352 caps->cpu_enable(caps); 2353 } 2354 2355 /* 2356 * For all non-boot scope capabilities, use stop_machine() 2357 * as it schedules the work allowing us to modify PSTATE, 2358 * instead of on_each_cpu() which uses an IPI, giving us a 2359 * PSTATE that disappears when we return. 2360 */ 2361 if (!boot_scope) 2362 stop_machine(cpu_enable_non_boot_scope_capabilities, 2363 NULL, cpu_online_mask); 2364 } 2365 2366 /* 2367 * Run through the list of capabilities to check for conflicts. 2368 * If the system has already detected a capability, take necessary 2369 * action on this CPU. 2370 */ 2371 static void verify_local_cpu_caps(u16 scope_mask) 2372 { 2373 int i; 2374 bool cpu_has_cap, system_has_cap; 2375 const struct arm64_cpu_capabilities *caps; 2376 2377 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2378 2379 for (i = 0; i < ARM64_NCAPS; i++) { 2380 caps = cpu_hwcaps_ptrs[i]; 2381 if (!caps || !(caps->type & scope_mask)) 2382 continue; 2383 2384 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2385 system_has_cap = cpus_have_cap(caps->capability); 2386 2387 if (system_has_cap) { 2388 /* 2389 * Check if the new CPU misses an advertised feature, 2390 * which is not safe to miss. 2391 */ 2392 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2393 break; 2394 /* 2395 * We have to issue cpu_enable() irrespective of 2396 * whether the CPU has it or not, as it is enabeld 2397 * system wide. It is upto the call back to take 2398 * appropriate action on this CPU. 2399 */ 2400 if (caps->cpu_enable) 2401 caps->cpu_enable(caps); 2402 } else { 2403 /* 2404 * Check if the CPU has this capability if it isn't 2405 * safe to have when the system doesn't. 2406 */ 2407 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2408 break; 2409 } 2410 } 2411 2412 if (i < ARM64_NCAPS) { 2413 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2414 smp_processor_id(), caps->capability, 2415 caps->desc, system_has_cap, cpu_has_cap); 2416 2417 if (cpucap_panic_on_conflict(caps)) 2418 cpu_panic_kernel(); 2419 else 2420 cpu_die_early(); 2421 } 2422 } 2423 2424 /* 2425 * Check for CPU features that are used in early boot 2426 * based on the Boot CPU value. 2427 */ 2428 static void check_early_cpu_features(void) 2429 { 2430 verify_cpu_asid_bits(); 2431 2432 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2433 } 2434 2435 static void 2436 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2437 { 2438 2439 for (; caps->matches; caps++) 2440 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2441 pr_crit("CPU%d: missing HWCAP: %s\n", 2442 smp_processor_id(), caps->desc); 2443 cpu_die_early(); 2444 } 2445 } 2446 2447 static void verify_sve_features(void) 2448 { 2449 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2450 u64 zcr = read_zcr_features(); 2451 2452 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2453 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2454 2455 if (len < safe_len || sve_verify_vq_map()) { 2456 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2457 smp_processor_id()); 2458 cpu_die_early(); 2459 } 2460 2461 /* Add checks on other ZCR bits here if necessary */ 2462 } 2463 2464 static void verify_hyp_capabilities(void) 2465 { 2466 u64 safe_mmfr1, mmfr0, mmfr1; 2467 int parange, ipa_max; 2468 unsigned int safe_vmid_bits, vmid_bits; 2469 2470 if (!IS_ENABLED(CONFIG_KVM) || !IS_ENABLED(CONFIG_KVM_ARM_HOST)) 2471 return; 2472 2473 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 2474 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 2475 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 2476 2477 /* Verify VMID bits */ 2478 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 2479 vmid_bits = get_vmid_bits(mmfr1); 2480 if (vmid_bits < safe_vmid_bits) { 2481 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 2482 cpu_die_early(); 2483 } 2484 2485 /* Verify IPA range */ 2486 parange = cpuid_feature_extract_unsigned_field(mmfr0, 2487 ID_AA64MMFR0_PARANGE_SHIFT); 2488 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 2489 if (ipa_max < get_kvm_ipa_limit()) { 2490 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 2491 cpu_die_early(); 2492 } 2493 } 2494 2495 /* 2496 * Run through the enabled system capabilities and enable() it on this CPU. 2497 * The capabilities were decided based on the available CPUs at the boot time. 2498 * Any new CPU should match the system wide status of the capability. If the 2499 * new CPU doesn't have a capability which the system now has enabled, we 2500 * cannot do anything to fix it up and could cause unexpected failures. So 2501 * we park the CPU. 2502 */ 2503 static void verify_local_cpu_capabilities(void) 2504 { 2505 /* 2506 * The capabilities with SCOPE_BOOT_CPU are checked from 2507 * check_early_cpu_features(), as they need to be verified 2508 * on all secondary CPUs. 2509 */ 2510 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2511 2512 verify_local_elf_hwcaps(arm64_elf_hwcaps); 2513 2514 if (system_supports_32bit_el0()) 2515 verify_local_elf_hwcaps(compat_elf_hwcaps); 2516 2517 if (system_supports_sve()) 2518 verify_sve_features(); 2519 2520 if (is_hyp_mode_available()) 2521 verify_hyp_capabilities(); 2522 } 2523 2524 void check_local_cpu_capabilities(void) 2525 { 2526 /* 2527 * All secondary CPUs should conform to the early CPU features 2528 * in use by the kernel based on boot CPU. 2529 */ 2530 check_early_cpu_features(); 2531 2532 /* 2533 * If we haven't finalised the system capabilities, this CPU gets 2534 * a chance to update the errata work arounds and local features. 2535 * Otherwise, this CPU should verify that it has all the system 2536 * advertised capabilities. 2537 */ 2538 if (!system_capabilities_finalized()) 2539 update_cpu_capabilities(SCOPE_LOCAL_CPU); 2540 else 2541 verify_local_cpu_capabilities(); 2542 } 2543 2544 static void __init setup_boot_cpu_capabilities(void) 2545 { 2546 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 2547 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 2548 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 2549 enable_cpu_capabilities(SCOPE_BOOT_CPU); 2550 } 2551 2552 bool this_cpu_has_cap(unsigned int n) 2553 { 2554 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 2555 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2556 2557 if (cap) 2558 return cap->matches(cap, SCOPE_LOCAL_CPU); 2559 } 2560 2561 return false; 2562 } 2563 2564 /* 2565 * This helper function is used in a narrow window when, 2566 * - The system wide safe registers are set with all the SMP CPUs and, 2567 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 2568 * In all other cases cpus_have_{const_}cap() should be used. 2569 */ 2570 static bool __system_matches_cap(unsigned int n) 2571 { 2572 if (n < ARM64_NCAPS) { 2573 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2574 2575 if (cap) 2576 return cap->matches(cap, SCOPE_SYSTEM); 2577 } 2578 return false; 2579 } 2580 2581 void cpu_set_feature(unsigned int num) 2582 { 2583 WARN_ON(num >= MAX_CPU_FEATURES); 2584 elf_hwcap |= BIT(num); 2585 } 2586 EXPORT_SYMBOL_GPL(cpu_set_feature); 2587 2588 bool cpu_have_feature(unsigned int num) 2589 { 2590 WARN_ON(num >= MAX_CPU_FEATURES); 2591 return elf_hwcap & BIT(num); 2592 } 2593 EXPORT_SYMBOL_GPL(cpu_have_feature); 2594 2595 unsigned long cpu_get_elf_hwcap(void) 2596 { 2597 /* 2598 * We currently only populate the first 32 bits of AT_HWCAP. Please 2599 * note that for userspace compatibility we guarantee that bits 62 2600 * and 63 will always be returned as 0. 2601 */ 2602 return lower_32_bits(elf_hwcap); 2603 } 2604 2605 unsigned long cpu_get_elf_hwcap2(void) 2606 { 2607 return upper_32_bits(elf_hwcap); 2608 } 2609 2610 static void __init setup_system_capabilities(void) 2611 { 2612 /* 2613 * We have finalised the system-wide safe feature 2614 * registers, finalise the capabilities that depend 2615 * on it. Also enable all the available capabilities, 2616 * that are not enabled already. 2617 */ 2618 update_cpu_capabilities(SCOPE_SYSTEM); 2619 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2620 } 2621 2622 void __init setup_cpu_features(void) 2623 { 2624 u32 cwg; 2625 2626 setup_system_capabilities(); 2627 setup_elf_hwcaps(arm64_elf_hwcaps); 2628 2629 if (system_supports_32bit_el0()) 2630 setup_elf_hwcaps(compat_elf_hwcaps); 2631 2632 if (system_uses_ttbr0_pan()) 2633 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2634 2635 sve_setup(); 2636 minsigstksz_setup(); 2637 2638 /* Advertise that we have computed the system capabilities */ 2639 finalize_system_capabilities(); 2640 2641 /* 2642 * Check for sane CTR_EL0.CWG value. 2643 */ 2644 cwg = cache_type_cwg(); 2645 if (!cwg) 2646 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2647 ARCH_DMA_MINALIGN); 2648 } 2649 2650 static bool __maybe_unused 2651 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) 2652 { 2653 return (__system_matches_cap(ARM64_HAS_PAN) && !__system_matches_cap(ARM64_HAS_UAO)); 2654 } 2655 2656 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 2657 { 2658 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 2659 } 2660 2661 /* 2662 * We emulate only the following system register space. 2663 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 2664 * See Table C5-6 System instruction encodings for System register accesses, 2665 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 2666 */ 2667 static inline bool __attribute_const__ is_emulated(u32 id) 2668 { 2669 return (sys_reg_Op0(id) == 0x3 && 2670 sys_reg_CRn(id) == 0x0 && 2671 sys_reg_Op1(id) == 0x0 && 2672 (sys_reg_CRm(id) == 0 || 2673 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 2674 } 2675 2676 /* 2677 * With CRm == 0, reg should be one of : 2678 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 2679 */ 2680 static inline int emulate_id_reg(u32 id, u64 *valp) 2681 { 2682 switch (id) { 2683 case SYS_MIDR_EL1: 2684 *valp = read_cpuid_id(); 2685 break; 2686 case SYS_MPIDR_EL1: 2687 *valp = SYS_MPIDR_SAFE_VAL; 2688 break; 2689 case SYS_REVIDR_EL1: 2690 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 2691 *valp = 0; 2692 break; 2693 default: 2694 return -EINVAL; 2695 } 2696 2697 return 0; 2698 } 2699 2700 static int emulate_sys_reg(u32 id, u64 *valp) 2701 { 2702 struct arm64_ftr_reg *regp; 2703 2704 if (!is_emulated(id)) 2705 return -EINVAL; 2706 2707 if (sys_reg_CRm(id) == 0) 2708 return emulate_id_reg(id, valp); 2709 2710 regp = get_arm64_ftr_reg_nowarn(id); 2711 if (regp) 2712 *valp = arm64_ftr_reg_user_value(regp); 2713 else 2714 /* 2715 * The untracked registers are either IMPLEMENTATION DEFINED 2716 * (e.g, ID_AFR0_EL1) or reserved RAZ. 2717 */ 2718 *valp = 0; 2719 return 0; 2720 } 2721 2722 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 2723 { 2724 int rc; 2725 u64 val; 2726 2727 rc = emulate_sys_reg(sys_reg, &val); 2728 if (!rc) { 2729 pt_regs_write_reg(regs, rt, val); 2730 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 2731 } 2732 return rc; 2733 } 2734 2735 static int emulate_mrs(struct pt_regs *regs, u32 insn) 2736 { 2737 u32 sys_reg, rt; 2738 2739 /* 2740 * sys_reg values are defined as used in mrs/msr instruction. 2741 * shift the imm value to get the encoding. 2742 */ 2743 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 2744 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 2745 return do_emulate_mrs(regs, sys_reg, rt); 2746 } 2747 2748 static struct undef_hook mrs_hook = { 2749 .instr_mask = 0xfff00000, 2750 .instr_val = 0xd5300000, 2751 .pstate_mask = PSR_AA32_MODE_MASK, 2752 .pstate_val = PSR_MODE_EL0t, 2753 .fn = emulate_mrs, 2754 }; 2755 2756 static int __init enable_mrs_emulation(void) 2757 { 2758 register_undef_hook(&mrs_hook); 2759 return 0; 2760 } 2761 2762 core_initcall(enable_mrs_emulation); 2763 2764 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 2765 char *buf) 2766 { 2767 if (__meltdown_safe) 2768 return sprintf(buf, "Not affected\n"); 2769 2770 if (arm64_kernel_unmapped_at_el0()) 2771 return sprintf(buf, "Mitigation: PTI\n"); 2772 2773 return sprintf(buf, "Vulnerable\n"); 2774 } 2775