1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU specific errata definitions 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 8 #include <linux/arm-smccc.h> 9 #include <linux/types.h> 10 #include <linux/cpu.h> 11 #include <asm/cpu.h> 12 #include <asm/cputype.h> 13 #include <asm/cpufeature.h> 14 #include <asm/kvm_asm.h> 15 #include <asm/smp_plat.h> 16 17 static bool __maybe_unused 18 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) 19 { 20 const struct arm64_midr_revidr *fix; 21 u32 midr = read_cpuid_id(), revidr; 22 23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 24 if (!is_midr_in_range(midr, &entry->midr_range)) 25 return false; 26 27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; 28 revidr = read_cpuid(REVIDR_EL1); 29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) 30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) 31 return false; 32 33 return true; 34 } 35 36 static bool __maybe_unused 37 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry, 38 int scope) 39 { 40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list); 42 } 43 44 static bool __maybe_unused 45 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) 46 { 47 u32 model; 48 49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 50 51 model = read_cpuid_id(); 52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) | 53 MIDR_ARCHITECTURE_MASK; 54 55 return model == entry->midr_range.model; 56 } 57 58 static bool 59 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, 60 int scope) 61 { 62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask; 64 u64 ctr_raw, ctr_real; 65 66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 67 68 /* 69 * We want to make sure that all the CPUs in the system expose 70 * a consistent CTR_EL0 to make sure that applications behaves 71 * correctly with migration. 72 * 73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 : 74 * 75 * 1) It is safe if the system doesn't support IDC, as CPU anyway 76 * reports IDC = 0, consistent with the rest. 77 * 78 * 2) If the system has IDC, it is still safe as we trap CTR_EL0 79 * access on this CPU via the ARM64_HAS_CACHE_IDC capability. 80 * 81 * So, we need to make sure either the raw CTR_EL0 or the effective 82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot. 83 */ 84 ctr_raw = read_cpuid_cachetype() & mask; 85 ctr_real = read_cpuid_effective_cachetype() & mask; 86 87 return (ctr_real != sys) && (ctr_raw != sys); 88 } 89 90 static void 91 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) 92 { 93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 94 bool enable_uct_trap = false; 95 96 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */ 97 if ((read_cpuid_cachetype() & mask) != 98 (arm64_ftr_reg_ctrel0.sys_val & mask)) 99 enable_uct_trap = true; 100 101 /* ... or if the system is affected by an erratum */ 102 if (cap->capability == ARM64_WORKAROUND_1542419) 103 enable_uct_trap = true; 104 105 if (enable_uct_trap) 106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 107 } 108 109 #ifdef CONFIG_ARM64_ERRATUM_1463225 110 static bool 111 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry, 112 int scope) 113 { 114 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode(); 115 } 116 #endif 117 118 static void __maybe_unused 119 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) 120 { 121 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); 122 } 123 124 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 125 .matches = is_affected_midr_range, \ 126 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) 127 128 #define CAP_MIDR_ALL_VERSIONS(model) \ 129 .matches = is_affected_midr_range, \ 130 .midr_range = MIDR_ALL_VERSIONS(model) 131 132 #define MIDR_FIXED(rev, revidr_mask) \ 133 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}} 134 135 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 136 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 137 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) 138 139 #define CAP_MIDR_RANGE_LIST(list) \ 140 .matches = is_affected_midr_range_list, \ 141 .midr_range_list = list 142 143 /* Errata affecting a range of revisions of given model variant */ 144 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \ 145 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) 146 147 /* Errata affecting a single variant/revision of a model */ 148 #define ERRATA_MIDR_REV(model, var, rev) \ 149 ERRATA_MIDR_RANGE(model, var, rev, var, rev) 150 151 /* Errata affecting all variants/revisions of a given a model */ 152 #define ERRATA_MIDR_ALL_VERSIONS(model) \ 153 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 154 CAP_MIDR_ALL_VERSIONS(model) 155 156 /* Errata affecting a list of midr ranges, with same work around */ 157 #define ERRATA_MIDR_RANGE_LIST(midr_list) \ 158 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 159 CAP_MIDR_RANGE_LIST(midr_list) 160 161 static const __maybe_unused struct midr_range tx2_family_cpus[] = { 162 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 163 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 164 {}, 165 }; 166 167 static bool __maybe_unused 168 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, 169 int scope) 170 { 171 int i; 172 173 if (!is_affected_midr_range_list(entry, scope) || 174 !is_hyp_mode_available()) 175 return false; 176 177 for_each_possible_cpu(i) { 178 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0) 179 return true; 180 } 181 182 return false; 183 } 184 185 static bool __maybe_unused 186 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, 187 int scope) 188 { 189 u32 midr = read_cpuid_id(); 190 bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT); 191 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); 192 193 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 194 return is_midr_in_range(midr, &range) && has_dic; 195 } 196 197 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 198 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { 199 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 200 { 201 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0) 202 }, 203 { 204 .midr_range.model = MIDR_QCOM_KRYO, 205 .matches = is_kryo_midr, 206 }, 207 #endif 208 #ifdef CONFIG_ARM64_ERRATUM_1286807 209 { 210 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), 211 }, 212 #endif 213 {}, 214 }; 215 #endif 216 217 #ifdef CONFIG_CAVIUM_ERRATUM_27456 218 const struct midr_range cavium_erratum_27456_cpus[] = { 219 /* Cavium ThunderX, T88 pass 1.x - 2.1 */ 220 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1), 221 /* Cavium ThunderX, T81 pass 1.0 */ 222 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0), 223 {}, 224 }; 225 #endif 226 227 #ifdef CONFIG_CAVIUM_ERRATUM_30115 228 static const struct midr_range cavium_erratum_30115_cpus[] = { 229 /* Cavium ThunderX, T88 pass 1.x - 2.2 */ 230 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2), 231 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ 232 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2), 233 /* Cavium ThunderX, T83 pass 1.0 */ 234 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0), 235 {}, 236 }; 237 #endif 238 239 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 240 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = { 241 { 242 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0), 243 }, 244 { 245 .midr_range.model = MIDR_QCOM_KRYO, 246 .matches = is_kryo_midr, 247 }, 248 {}, 249 }; 250 #endif 251 252 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 253 static const struct midr_range workaround_clean_cache[] = { 254 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 255 defined(CONFIG_ARM64_ERRATUM_827319) || \ 256 defined(CONFIG_ARM64_ERRATUM_824069) 257 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */ 258 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2), 259 #endif 260 #ifdef CONFIG_ARM64_ERRATUM_819472 261 /* Cortex-A53 r0p[01] : ARM errata 819472 */ 262 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1), 263 #endif 264 {}, 265 }; 266 #endif 267 268 #ifdef CONFIG_ARM64_ERRATUM_1418040 269 /* 270 * - 1188873 affects r0p0 to r2p0 271 * - 1418040 affects r0p0 to r3p1 272 */ 273 static const struct midr_range erratum_1418040_list[] = { 274 /* Cortex-A76 r0p0 to r3p1 */ 275 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 276 /* Neoverse-N1 r0p0 to r3p1 */ 277 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1), 278 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 279 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 280 {}, 281 }; 282 #endif 283 284 #ifdef CONFIG_ARM64_ERRATUM_845719 285 static const struct midr_range erratum_845719_list[] = { 286 /* Cortex-A53 r0p[01234] */ 287 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 288 /* Brahma-B53 r0p[0] */ 289 MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 290 /* Kryo2XX Silver rAp4 */ 291 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4), 292 {}, 293 }; 294 #endif 295 296 #ifdef CONFIG_ARM64_ERRATUM_843419 297 static const struct arm64_cpu_capabilities erratum_843419_list[] = { 298 { 299 /* Cortex-A53 r0p[01234] */ 300 .matches = is_affected_midr_range, 301 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 302 MIDR_FIXED(0x4, BIT(8)), 303 }, 304 { 305 /* Brahma-B53 r0p[0] */ 306 .matches = is_affected_midr_range, 307 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 308 }, 309 {}, 310 }; 311 #endif 312 313 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 314 static const struct midr_range erratum_speculative_at_list[] = { 315 #ifdef CONFIG_ARM64_ERRATUM_1165522 316 /* Cortex A76 r0p0 to r2p0 */ 317 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), 318 #endif 319 #ifdef CONFIG_ARM64_ERRATUM_1319367 320 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 321 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 322 #endif 323 #ifdef CONFIG_ARM64_ERRATUM_1530923 324 /* Cortex A55 r0p0 to r2p0 */ 325 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0), 326 /* Kryo4xx Silver (rdpe => r1p0) */ 327 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 328 #endif 329 {}, 330 }; 331 #endif 332 333 #ifdef CONFIG_ARM64_ERRATUM_1463225 334 static const struct midr_range erratum_1463225[] = { 335 /* Cortex-A76 r0p0 - r3p1 */ 336 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 337 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 338 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 339 {}, 340 }; 341 #endif 342 343 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 344 static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { 345 #ifdef CONFIG_ARM64_ERRATUM_2139208 346 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 347 #endif 348 #ifdef CONFIG_ARM64_ERRATUM_2119858 349 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 350 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 351 #endif 352 {}, 353 }; 354 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ 355 356 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 357 static const struct midr_range tsb_flush_fail_cpus[] = { 358 #ifdef CONFIG_ARM64_ERRATUM_2067961 359 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 360 #endif 361 #ifdef CONFIG_ARM64_ERRATUM_2054223 362 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 363 #endif 364 {}, 365 }; 366 #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ 367 368 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 369 static struct midr_range trbe_write_out_of_range_cpus[] = { 370 #ifdef CONFIG_ARM64_ERRATUM_2253138 371 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 372 #endif 373 #ifdef CONFIG_ARM64_ERRATUM_2224489 374 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 375 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 376 #endif 377 {}, 378 }; 379 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 380 381 const struct arm64_cpu_capabilities arm64_errata[] = { 382 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 383 { 384 .desc = "ARM errata 826319, 827319, 824069, or 819472", 385 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 386 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache), 387 .cpu_enable = cpu_enable_cache_maint_trap, 388 }, 389 #endif 390 #ifdef CONFIG_ARM64_ERRATUM_832075 391 { 392 /* Cortex-A57 r0p0 - r1p2 */ 393 .desc = "ARM erratum 832075", 394 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 395 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 396 0, 0, 397 1, 2), 398 }, 399 #endif 400 #ifdef CONFIG_ARM64_ERRATUM_834220 401 { 402 /* Cortex-A57 r0p0 - r1p2 */ 403 .desc = "ARM erratum 834220", 404 .capability = ARM64_WORKAROUND_834220, 405 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 406 0, 0, 407 1, 2), 408 }, 409 #endif 410 #ifdef CONFIG_ARM64_ERRATUM_843419 411 { 412 .desc = "ARM erratum 843419", 413 .capability = ARM64_WORKAROUND_843419, 414 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 415 .matches = cpucap_multi_entry_cap_matches, 416 .match_list = erratum_843419_list, 417 }, 418 #endif 419 #ifdef CONFIG_ARM64_ERRATUM_845719 420 { 421 .desc = "ARM erratum 845719", 422 .capability = ARM64_WORKAROUND_845719, 423 ERRATA_MIDR_RANGE_LIST(erratum_845719_list), 424 }, 425 #endif 426 #ifdef CONFIG_CAVIUM_ERRATUM_23154 427 { 428 /* Cavium ThunderX, pass 1.x */ 429 .desc = "Cavium erratum 23154", 430 .capability = ARM64_WORKAROUND_CAVIUM_23154, 431 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1), 432 }, 433 #endif 434 #ifdef CONFIG_CAVIUM_ERRATUM_27456 435 { 436 .desc = "Cavium erratum 27456", 437 .capability = ARM64_WORKAROUND_CAVIUM_27456, 438 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus), 439 }, 440 #endif 441 #ifdef CONFIG_CAVIUM_ERRATUM_30115 442 { 443 .desc = "Cavium erratum 30115", 444 .capability = ARM64_WORKAROUND_CAVIUM_30115, 445 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus), 446 }, 447 #endif 448 { 449 .desc = "Mismatched cache type (CTR_EL0)", 450 .capability = ARM64_MISMATCHED_CACHE_TYPE, 451 .matches = has_mismatched_cache_type, 452 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 453 .cpu_enable = cpu_enable_trap_ctr_access, 454 }, 455 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 456 { 457 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003", 458 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, 459 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 460 .matches = cpucap_multi_entry_cap_matches, 461 .match_list = qcom_erratum_1003_list, 462 }, 463 #endif 464 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 465 { 466 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807", 467 .capability = ARM64_WORKAROUND_REPEAT_TLBI, 468 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 469 .matches = cpucap_multi_entry_cap_matches, 470 .match_list = arm64_repeat_tlbi_list, 471 }, 472 #endif 473 #ifdef CONFIG_ARM64_ERRATUM_858921 474 { 475 /* Cortex-A73 all versions */ 476 .desc = "ARM erratum 858921", 477 .capability = ARM64_WORKAROUND_858921, 478 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 479 }, 480 #endif 481 { 482 .desc = "Spectre-v2", 483 .capability = ARM64_SPECTRE_V2, 484 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 485 .matches = has_spectre_v2, 486 .cpu_enable = spectre_v2_enable_mitigation, 487 }, 488 #ifdef CONFIG_RANDOMIZE_BASE 489 { 490 /* Must come after the Spectre-v2 entry */ 491 .desc = "Spectre-v3a", 492 .capability = ARM64_SPECTRE_V3A, 493 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 494 .matches = has_spectre_v3a, 495 .cpu_enable = spectre_v3a_enable_mitigation, 496 }, 497 #endif 498 { 499 .desc = "Spectre-v4", 500 .capability = ARM64_SPECTRE_V4, 501 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 502 .matches = has_spectre_v4, 503 .cpu_enable = spectre_v4_enable_mitigation, 504 }, 505 #ifdef CONFIG_ARM64_ERRATUM_1418040 506 { 507 .desc = "ARM erratum 1418040", 508 .capability = ARM64_WORKAROUND_1418040, 509 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list), 510 /* 511 * We need to allow affected CPUs to come in late, but 512 * also need the non-affected CPUs to be able to come 513 * in at any point in time. Wonderful. 514 */ 515 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 516 }, 517 #endif 518 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 519 { 520 .desc = "ARM errata 1165522, 1319367, or 1530923", 521 .capability = ARM64_WORKAROUND_SPECULATIVE_AT, 522 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list), 523 }, 524 #endif 525 #ifdef CONFIG_ARM64_ERRATUM_1463225 526 { 527 .desc = "ARM erratum 1463225", 528 .capability = ARM64_WORKAROUND_1463225, 529 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 530 .matches = has_cortex_a76_erratum_1463225, 531 .midr_range_list = erratum_1463225, 532 }, 533 #endif 534 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219 535 { 536 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)", 537 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM, 538 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 539 .matches = needs_tx2_tvm_workaround, 540 }, 541 { 542 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)", 543 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM, 544 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 545 }, 546 #endif 547 #ifdef CONFIG_ARM64_ERRATUM_1542419 548 { 549 /* we depend on the firmware portion for correctness */ 550 .desc = "ARM erratum 1542419 (kernel portion)", 551 .capability = ARM64_WORKAROUND_1542419, 552 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 553 .matches = has_neoverse_n1_erratum_1542419, 554 .cpu_enable = cpu_enable_trap_ctr_access, 555 }, 556 #endif 557 #ifdef CONFIG_ARM64_ERRATUM_1508412 558 { 559 /* we depend on the firmware portion for correctness */ 560 .desc = "ARM erratum 1508412 (kernel portion)", 561 .capability = ARM64_WORKAROUND_1508412, 562 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77, 563 0, 0, 564 1, 0), 565 }, 566 #endif 567 #ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM 568 { 569 /* NVIDIA Carmel */ 570 .desc = "NVIDIA Carmel CNP erratum", 571 .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP, 572 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 573 }, 574 #endif 575 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 576 { 577 /* 578 * The erratum work around is handled within the TRBE 579 * driver and can be applied per-cpu. So, we can allow 580 * a late CPU to come online with this erratum. 581 */ 582 .desc = "ARM erratum 2119858 or 2139208", 583 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, 584 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 585 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), 586 }, 587 #endif 588 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 589 { 590 .desc = "ARM erratum 2067961 or 2054223", 591 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, 592 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus), 593 }, 594 #endif 595 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 596 { 597 .desc = "ARM erratum 2253138 or 2224489", 598 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, 599 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 600 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), 601 }, 602 #endif 603 #ifdef CONFIG_ARM64_ERRATUM_2077057 604 { 605 .desc = "ARM erratum 2077057", 606 .capability = ARM64_WORKAROUND_2077057, 607 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 608 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 609 }, 610 #endif 611 #ifdef CONFIG_ARM64_ERRATUM_2064142 612 { 613 .desc = "ARM erratum 2064142", 614 .capability = ARM64_WORKAROUND_2064142, 615 616 /* Cortex-A510 r0p0 - r0p2 */ 617 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 618 }, 619 #endif 620 #ifdef CONFIG_ARM64_ERRATUM_2038923 621 { 622 .desc = "ARM erratum 2038923", 623 .capability = ARM64_WORKAROUND_2038923, 624 625 /* Cortex-A510 r0p0 - r0p2 */ 626 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 627 }, 628 #endif 629 #ifdef CONFIG_ARM64_ERRATUM_1902691 630 { 631 .desc = "ARM erratum 1902691", 632 .capability = ARM64_WORKAROUND_1902691, 633 634 /* Cortex-A510 r0p0 - r0p1 */ 635 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1) 636 }, 637 #endif 638 { 639 } 640 }; 641