1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU specific errata definitions 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 8 #include <linux/arm-smccc.h> 9 #include <linux/types.h> 10 #include <linux/cpu.h> 11 #include <asm/cpu.h> 12 #include <asm/cputype.h> 13 #include <asm/cpufeature.h> 14 #include <asm/kvm_asm.h> 15 #include <asm/smp_plat.h> 16 17 static bool __maybe_unused 18 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) 19 { 20 const struct arm64_midr_revidr *fix; 21 u32 midr = read_cpuid_id(), revidr; 22 23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 24 if (!is_midr_in_range(midr, &entry->midr_range)) 25 return false; 26 27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; 28 revidr = read_cpuid(REVIDR_EL1); 29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) 30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) 31 return false; 32 33 return true; 34 } 35 36 static bool __maybe_unused 37 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry, 38 int scope) 39 { 40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list); 42 } 43 44 static bool __maybe_unused 45 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) 46 { 47 u32 model; 48 49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 50 51 model = read_cpuid_id(); 52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) | 53 MIDR_ARCHITECTURE_MASK; 54 55 return model == entry->midr_range.model; 56 } 57 58 static bool 59 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, 60 int scope) 61 { 62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask; 64 u64 ctr_raw, ctr_real; 65 66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 67 68 /* 69 * We want to make sure that all the CPUs in the system expose 70 * a consistent CTR_EL0 to make sure that applications behaves 71 * correctly with migration. 72 * 73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 : 74 * 75 * 1) It is safe if the system doesn't support IDC, as CPU anyway 76 * reports IDC = 0, consistent with the rest. 77 * 78 * 2) If the system has IDC, it is still safe as we trap CTR_EL0 79 * access on this CPU via the ARM64_HAS_CACHE_IDC capability. 80 * 81 * So, we need to make sure either the raw CTR_EL0 or the effective 82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot. 83 */ 84 ctr_raw = read_cpuid_cachetype() & mask; 85 ctr_real = read_cpuid_effective_cachetype() & mask; 86 87 return (ctr_real != sys) && (ctr_raw != sys); 88 } 89 90 static void 91 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) 92 { 93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 94 bool enable_uct_trap = false; 95 96 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */ 97 if ((read_cpuid_cachetype() & mask) != 98 (arm64_ftr_reg_ctrel0.sys_val & mask)) 99 enable_uct_trap = true; 100 101 /* ... or if the system is affected by an erratum */ 102 if (cap->capability == ARM64_WORKAROUND_1542419) 103 enable_uct_trap = true; 104 105 if (enable_uct_trap) 106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 107 } 108 109 #ifdef CONFIG_ARM64_ERRATUM_1463225 110 DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); 111 112 static bool 113 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry, 114 int scope) 115 { 116 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode(); 117 } 118 #endif 119 120 static void __maybe_unused 121 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) 122 { 123 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); 124 } 125 126 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 127 .matches = is_affected_midr_range, \ 128 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) 129 130 #define CAP_MIDR_ALL_VERSIONS(model) \ 131 .matches = is_affected_midr_range, \ 132 .midr_range = MIDR_ALL_VERSIONS(model) 133 134 #define MIDR_FIXED(rev, revidr_mask) \ 135 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}} 136 137 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 138 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 139 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) 140 141 #define CAP_MIDR_RANGE_LIST(list) \ 142 .matches = is_affected_midr_range_list, \ 143 .midr_range_list = list 144 145 /* Errata affecting a range of revisions of given model variant */ 146 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \ 147 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) 148 149 /* Errata affecting a single variant/revision of a model */ 150 #define ERRATA_MIDR_REV(model, var, rev) \ 151 ERRATA_MIDR_RANGE(model, var, rev, var, rev) 152 153 /* Errata affecting all variants/revisions of a given a model */ 154 #define ERRATA_MIDR_ALL_VERSIONS(model) \ 155 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 156 CAP_MIDR_ALL_VERSIONS(model) 157 158 /* Errata affecting a list of midr ranges, with same work around */ 159 #define ERRATA_MIDR_RANGE_LIST(midr_list) \ 160 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 161 CAP_MIDR_RANGE_LIST(midr_list) 162 163 static const __maybe_unused struct midr_range tx2_family_cpus[] = { 164 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 165 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 166 {}, 167 }; 168 169 static bool __maybe_unused 170 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, 171 int scope) 172 { 173 int i; 174 175 if (!is_affected_midr_range_list(entry, scope) || 176 !is_hyp_mode_available()) 177 return false; 178 179 for_each_possible_cpu(i) { 180 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0) 181 return true; 182 } 183 184 return false; 185 } 186 187 static bool __maybe_unused 188 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, 189 int scope) 190 { 191 u32 midr = read_cpuid_id(); 192 bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT); 193 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); 194 195 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 196 return is_midr_in_range(midr, &range) && has_dic; 197 } 198 199 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 200 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { 201 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 202 { 203 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0) 204 }, 205 { 206 .midr_range.model = MIDR_QCOM_KRYO, 207 .matches = is_kryo_midr, 208 }, 209 #endif 210 #ifdef CONFIG_ARM64_ERRATUM_1286807 211 { 212 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), 213 }, 214 #endif 215 {}, 216 }; 217 #endif 218 219 #ifdef CONFIG_CAVIUM_ERRATUM_27456 220 const struct midr_range cavium_erratum_27456_cpus[] = { 221 /* Cavium ThunderX, T88 pass 1.x - 2.1 */ 222 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1), 223 /* Cavium ThunderX, T81 pass 1.0 */ 224 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0), 225 {}, 226 }; 227 #endif 228 229 #ifdef CONFIG_CAVIUM_ERRATUM_30115 230 static const struct midr_range cavium_erratum_30115_cpus[] = { 231 /* Cavium ThunderX, T88 pass 1.x - 2.2 */ 232 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2), 233 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ 234 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2), 235 /* Cavium ThunderX, T83 pass 1.0 */ 236 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0), 237 {}, 238 }; 239 #endif 240 241 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 242 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = { 243 { 244 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0), 245 }, 246 { 247 .midr_range.model = MIDR_QCOM_KRYO, 248 .matches = is_kryo_midr, 249 }, 250 {}, 251 }; 252 #endif 253 254 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 255 static const struct midr_range workaround_clean_cache[] = { 256 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 257 defined(CONFIG_ARM64_ERRATUM_827319) || \ 258 defined(CONFIG_ARM64_ERRATUM_824069) 259 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */ 260 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2), 261 #endif 262 #ifdef CONFIG_ARM64_ERRATUM_819472 263 /* Cortex-A53 r0p[01] : ARM errata 819472 */ 264 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1), 265 #endif 266 {}, 267 }; 268 #endif 269 270 #ifdef CONFIG_ARM64_ERRATUM_1418040 271 /* 272 * - 1188873 affects r0p0 to r2p0 273 * - 1418040 affects r0p0 to r3p1 274 */ 275 static const struct midr_range erratum_1418040_list[] = { 276 /* Cortex-A76 r0p0 to r3p1 */ 277 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 278 /* Neoverse-N1 r0p0 to r3p1 */ 279 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1), 280 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 281 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 282 {}, 283 }; 284 #endif 285 286 #ifdef CONFIG_ARM64_ERRATUM_845719 287 static const struct midr_range erratum_845719_list[] = { 288 /* Cortex-A53 r0p[01234] */ 289 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 290 /* Brahma-B53 r0p[0] */ 291 MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 292 /* Kryo2XX Silver rAp4 */ 293 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4), 294 {}, 295 }; 296 #endif 297 298 #ifdef CONFIG_ARM64_ERRATUM_843419 299 static const struct arm64_cpu_capabilities erratum_843419_list[] = { 300 { 301 /* Cortex-A53 r0p[01234] */ 302 .matches = is_affected_midr_range, 303 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 304 MIDR_FIXED(0x4, BIT(8)), 305 }, 306 { 307 /* Brahma-B53 r0p[0] */ 308 .matches = is_affected_midr_range, 309 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 310 }, 311 {}, 312 }; 313 #endif 314 315 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 316 static const struct midr_range erratum_speculative_at_list[] = { 317 #ifdef CONFIG_ARM64_ERRATUM_1165522 318 /* Cortex A76 r0p0 to r2p0 */ 319 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), 320 #endif 321 #ifdef CONFIG_ARM64_ERRATUM_1319367 322 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 323 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 324 #endif 325 #ifdef CONFIG_ARM64_ERRATUM_1530923 326 /* Cortex A55 r0p0 to r2p0 */ 327 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0), 328 /* Kryo4xx Silver (rdpe => r1p0) */ 329 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 330 #endif 331 {}, 332 }; 333 #endif 334 335 #ifdef CONFIG_ARM64_ERRATUM_1463225 336 static const struct midr_range erratum_1463225[] = { 337 /* Cortex-A76 r0p0 - r3p1 */ 338 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 339 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 340 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 341 {}, 342 }; 343 #endif 344 345 const struct arm64_cpu_capabilities arm64_errata[] = { 346 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 347 { 348 .desc = "ARM errata 826319, 827319, 824069, or 819472", 349 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 350 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache), 351 .cpu_enable = cpu_enable_cache_maint_trap, 352 }, 353 #endif 354 #ifdef CONFIG_ARM64_ERRATUM_832075 355 { 356 /* Cortex-A57 r0p0 - r1p2 */ 357 .desc = "ARM erratum 832075", 358 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 359 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 360 0, 0, 361 1, 2), 362 }, 363 #endif 364 #ifdef CONFIG_ARM64_ERRATUM_834220 365 { 366 /* Cortex-A57 r0p0 - r1p2 */ 367 .desc = "ARM erratum 834220", 368 .capability = ARM64_WORKAROUND_834220, 369 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 370 0, 0, 371 1, 2), 372 }, 373 #endif 374 #ifdef CONFIG_ARM64_ERRATUM_843419 375 { 376 .desc = "ARM erratum 843419", 377 .capability = ARM64_WORKAROUND_843419, 378 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 379 .matches = cpucap_multi_entry_cap_matches, 380 .match_list = erratum_843419_list, 381 }, 382 #endif 383 #ifdef CONFIG_ARM64_ERRATUM_845719 384 { 385 .desc = "ARM erratum 845719", 386 .capability = ARM64_WORKAROUND_845719, 387 ERRATA_MIDR_RANGE_LIST(erratum_845719_list), 388 }, 389 #endif 390 #ifdef CONFIG_CAVIUM_ERRATUM_23154 391 { 392 /* Cavium ThunderX, pass 1.x */ 393 .desc = "Cavium erratum 23154", 394 .capability = ARM64_WORKAROUND_CAVIUM_23154, 395 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1), 396 }, 397 #endif 398 #ifdef CONFIG_CAVIUM_ERRATUM_27456 399 { 400 .desc = "Cavium erratum 27456", 401 .capability = ARM64_WORKAROUND_CAVIUM_27456, 402 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus), 403 }, 404 #endif 405 #ifdef CONFIG_CAVIUM_ERRATUM_30115 406 { 407 .desc = "Cavium erratum 30115", 408 .capability = ARM64_WORKAROUND_CAVIUM_30115, 409 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus), 410 }, 411 #endif 412 { 413 .desc = "Mismatched cache type (CTR_EL0)", 414 .capability = ARM64_MISMATCHED_CACHE_TYPE, 415 .matches = has_mismatched_cache_type, 416 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 417 .cpu_enable = cpu_enable_trap_ctr_access, 418 }, 419 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 420 { 421 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003", 422 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, 423 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 424 .matches = cpucap_multi_entry_cap_matches, 425 .match_list = qcom_erratum_1003_list, 426 }, 427 #endif 428 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 429 { 430 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807", 431 .capability = ARM64_WORKAROUND_REPEAT_TLBI, 432 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 433 .matches = cpucap_multi_entry_cap_matches, 434 .match_list = arm64_repeat_tlbi_list, 435 }, 436 #endif 437 #ifdef CONFIG_ARM64_ERRATUM_858921 438 { 439 /* Cortex-A73 all versions */ 440 .desc = "ARM erratum 858921", 441 .capability = ARM64_WORKAROUND_858921, 442 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 443 }, 444 #endif 445 { 446 .desc = "Spectre-v2", 447 .capability = ARM64_SPECTRE_V2, 448 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 449 .matches = has_spectre_v2, 450 .cpu_enable = spectre_v2_enable_mitigation, 451 }, 452 #ifdef CONFIG_RANDOMIZE_BASE 453 { 454 /* Must come after the Spectre-v2 entry */ 455 .desc = "Spectre-v3a", 456 .capability = ARM64_SPECTRE_V3A, 457 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 458 .matches = has_spectre_v3a, 459 .cpu_enable = spectre_v3a_enable_mitigation, 460 }, 461 #endif 462 { 463 .desc = "Spectre-v4", 464 .capability = ARM64_SPECTRE_V4, 465 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 466 .matches = has_spectre_v4, 467 .cpu_enable = spectre_v4_enable_mitigation, 468 }, 469 #ifdef CONFIG_ARM64_ERRATUM_1418040 470 { 471 .desc = "ARM erratum 1418040", 472 .capability = ARM64_WORKAROUND_1418040, 473 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list), 474 /* 475 * We need to allow affected CPUs to come in late, but 476 * also need the non-affected CPUs to be able to come 477 * in at any point in time. Wonderful. 478 */ 479 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 480 }, 481 #endif 482 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 483 { 484 .desc = "ARM errata 1165522, 1319367, or 1530923", 485 .capability = ARM64_WORKAROUND_SPECULATIVE_AT, 486 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list), 487 }, 488 #endif 489 #ifdef CONFIG_ARM64_ERRATUM_1463225 490 { 491 .desc = "ARM erratum 1463225", 492 .capability = ARM64_WORKAROUND_1463225, 493 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 494 .matches = has_cortex_a76_erratum_1463225, 495 .midr_range_list = erratum_1463225, 496 }, 497 #endif 498 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219 499 { 500 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)", 501 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM, 502 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 503 .matches = needs_tx2_tvm_workaround, 504 }, 505 { 506 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)", 507 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM, 508 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 509 }, 510 #endif 511 #ifdef CONFIG_ARM64_ERRATUM_1542419 512 { 513 /* we depend on the firmware portion for correctness */ 514 .desc = "ARM erratum 1542419 (kernel portion)", 515 .capability = ARM64_WORKAROUND_1542419, 516 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 517 .matches = has_neoverse_n1_erratum_1542419, 518 .cpu_enable = cpu_enable_trap_ctr_access, 519 }, 520 #endif 521 #ifdef CONFIG_ARM64_ERRATUM_1508412 522 { 523 /* we depend on the firmware portion for correctness */ 524 .desc = "ARM erratum 1508412 (kernel portion)", 525 .capability = ARM64_WORKAROUND_1508412, 526 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77, 527 0, 0, 528 1, 0), 529 }, 530 #endif 531 { 532 } 533 }; 534