1 /* 2 * Contains CPU specific errata definitions 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/types.h> 20 #include <asm/cpu.h> 21 #include <asm/cputype.h> 22 #include <asm/cpufeature.h> 23 24 #define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) 25 #define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) 26 #define MIDR_THUNDERX MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) 27 28 #define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ 29 MIDR_ARCHITECTURE_MASK) 30 31 static bool __maybe_unused 32 is_affected_midr_range(const struct arm64_cpu_capabilities *entry) 33 { 34 u32 midr = read_cpuid_id(); 35 36 if ((midr & CPU_MODEL_MASK) != entry->midr_model) 37 return false; 38 39 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; 40 41 return (midr >= entry->midr_range_min && midr <= entry->midr_range_max); 42 } 43 44 #define MIDR_RANGE(model, min, max) \ 45 .matches = is_affected_midr_range, \ 46 .midr_model = model, \ 47 .midr_range_min = min, \ 48 .midr_range_max = max 49 50 const struct arm64_cpu_capabilities arm64_errata[] = { 51 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 52 defined(CONFIG_ARM64_ERRATUM_827319) || \ 53 defined(CONFIG_ARM64_ERRATUM_824069) 54 { 55 /* Cortex-A53 r0p[012] */ 56 .desc = "ARM errata 826319, 827319, 824069", 57 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 58 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02), 59 }, 60 #endif 61 #ifdef CONFIG_ARM64_ERRATUM_819472 62 { 63 /* Cortex-A53 r0p[01] */ 64 .desc = "ARM errata 819472", 65 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 66 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01), 67 }, 68 #endif 69 #ifdef CONFIG_ARM64_ERRATUM_832075 70 { 71 /* Cortex-A57 r0p0 - r1p2 */ 72 .desc = "ARM erratum 832075", 73 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 74 MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 75 (1 << MIDR_VARIANT_SHIFT) | 2), 76 }, 77 #endif 78 #ifdef CONFIG_ARM64_ERRATUM_834220 79 { 80 /* Cortex-A57 r0p0 - r1p2 */ 81 .desc = "ARM erratum 834220", 82 .capability = ARM64_WORKAROUND_834220, 83 MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 84 (1 << MIDR_VARIANT_SHIFT) | 2), 85 }, 86 #endif 87 #ifdef CONFIG_ARM64_ERRATUM_845719 88 { 89 /* Cortex-A53 r0p[01234] */ 90 .desc = "ARM erratum 845719", 91 .capability = ARM64_WORKAROUND_845719, 92 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), 93 }, 94 #endif 95 #ifdef CONFIG_CAVIUM_ERRATUM_23154 96 { 97 /* Cavium ThunderX, pass 1.x */ 98 .desc = "Cavium erratum 23154", 99 .capability = ARM64_WORKAROUND_CAVIUM_23154, 100 MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01), 101 }, 102 #endif 103 { 104 } 105 }; 106 107 void check_local_cpu_errata(void) 108 { 109 update_cpu_capabilities(arm64_errata, "enabling workaround for"); 110 } 111