1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU specific errata definitions 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 8 #include <linux/arm-smccc.h> 9 #include <linux/types.h> 10 #include <linux/cpu.h> 11 #include <asm/cpu.h> 12 #include <asm/cputype.h> 13 #include <asm/cpufeature.h> 14 #include <asm/kvm_asm.h> 15 #include <asm/smp_plat.h> 16 17 static bool __maybe_unused 18 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) 19 { 20 const struct arm64_midr_revidr *fix; 21 u32 midr = read_cpuid_id(), revidr; 22 23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 24 if (!is_midr_in_range(midr, &entry->midr_range)) 25 return false; 26 27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; 28 revidr = read_cpuid(REVIDR_EL1); 29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) 30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) 31 return false; 32 33 return true; 34 } 35 36 static bool __maybe_unused 37 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry, 38 int scope) 39 { 40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list); 42 } 43 44 static bool __maybe_unused 45 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) 46 { 47 u32 model; 48 49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 50 51 model = read_cpuid_id(); 52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) | 53 MIDR_ARCHITECTURE_MASK; 54 55 return model == entry->midr_range.model; 56 } 57 58 static bool 59 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, 60 int scope) 61 { 62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask; 64 u64 ctr_raw, ctr_real; 65 66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 67 68 /* 69 * We want to make sure that all the CPUs in the system expose 70 * a consistent CTR_EL0 to make sure that applications behaves 71 * correctly with migration. 72 * 73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 : 74 * 75 * 1) It is safe if the system doesn't support IDC, as CPU anyway 76 * reports IDC = 0, consistent with the rest. 77 * 78 * 2) If the system has IDC, it is still safe as we trap CTR_EL0 79 * access on this CPU via the ARM64_HAS_CACHE_IDC capability. 80 * 81 * So, we need to make sure either the raw CTR_EL0 or the effective 82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot. 83 */ 84 ctr_raw = read_cpuid_cachetype() & mask; 85 ctr_real = read_cpuid_effective_cachetype() & mask; 86 87 return (ctr_real != sys) && (ctr_raw != sys); 88 } 89 90 static void 91 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) 92 { 93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 94 bool enable_uct_trap = false; 95 96 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */ 97 if ((read_cpuid_cachetype() & mask) != 98 (arm64_ftr_reg_ctrel0.sys_val & mask)) 99 enable_uct_trap = true; 100 101 /* ... or if the system is affected by an erratum */ 102 if (cap->capability == ARM64_WORKAROUND_1542419) 103 enable_uct_trap = true; 104 105 if (enable_uct_trap) 106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 107 } 108 109 #ifdef CONFIG_ARM64_ERRATUM_1463225 110 DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); 111 112 static bool 113 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry, 114 int scope) 115 { 116 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode(); 117 } 118 #endif 119 120 static void __maybe_unused 121 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) 122 { 123 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); 124 } 125 126 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 127 .matches = is_affected_midr_range, \ 128 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) 129 130 #define CAP_MIDR_ALL_VERSIONS(model) \ 131 .matches = is_affected_midr_range, \ 132 .midr_range = MIDR_ALL_VERSIONS(model) 133 134 #define MIDR_FIXED(rev, revidr_mask) \ 135 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}} 136 137 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 138 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 139 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) 140 141 #define CAP_MIDR_RANGE_LIST(list) \ 142 .matches = is_affected_midr_range_list, \ 143 .midr_range_list = list 144 145 /* Errata affecting a range of revisions of given model variant */ 146 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \ 147 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) 148 149 /* Errata affecting a single variant/revision of a model */ 150 #define ERRATA_MIDR_REV(model, var, rev) \ 151 ERRATA_MIDR_RANGE(model, var, rev, var, rev) 152 153 /* Errata affecting all variants/revisions of a given a model */ 154 #define ERRATA_MIDR_ALL_VERSIONS(model) \ 155 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 156 CAP_MIDR_ALL_VERSIONS(model) 157 158 /* Errata affecting a list of midr ranges, with same work around */ 159 #define ERRATA_MIDR_RANGE_LIST(midr_list) \ 160 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 161 CAP_MIDR_RANGE_LIST(midr_list) 162 163 static const __maybe_unused struct midr_range tx2_family_cpus[] = { 164 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 165 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 166 {}, 167 }; 168 169 static bool __maybe_unused 170 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, 171 int scope) 172 { 173 int i; 174 175 if (!is_affected_midr_range_list(entry, scope) || 176 !is_hyp_mode_available()) 177 return false; 178 179 for_each_possible_cpu(i) { 180 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0) 181 return true; 182 } 183 184 return false; 185 } 186 187 static bool __maybe_unused 188 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, 189 int scope) 190 { 191 u32 midr = read_cpuid_id(); 192 bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT); 193 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); 194 195 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 196 return is_midr_in_range(midr, &range) && has_dic; 197 } 198 199 #ifdef CONFIG_RANDOMIZE_BASE 200 201 static const struct midr_range ca57_a72[] = { 202 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 203 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 204 {}, 205 }; 206 207 #endif 208 209 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 210 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { 211 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 212 { 213 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0) 214 }, 215 { 216 .midr_range.model = MIDR_QCOM_KRYO, 217 .matches = is_kryo_midr, 218 }, 219 #endif 220 #ifdef CONFIG_ARM64_ERRATUM_1286807 221 { 222 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), 223 }, 224 #endif 225 {}, 226 }; 227 #endif 228 229 #ifdef CONFIG_CAVIUM_ERRATUM_27456 230 const struct midr_range cavium_erratum_27456_cpus[] = { 231 /* Cavium ThunderX, T88 pass 1.x - 2.1 */ 232 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1), 233 /* Cavium ThunderX, T81 pass 1.0 */ 234 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0), 235 {}, 236 }; 237 #endif 238 239 #ifdef CONFIG_CAVIUM_ERRATUM_30115 240 static const struct midr_range cavium_erratum_30115_cpus[] = { 241 /* Cavium ThunderX, T88 pass 1.x - 2.2 */ 242 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2), 243 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ 244 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2), 245 /* Cavium ThunderX, T83 pass 1.0 */ 246 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0), 247 {}, 248 }; 249 #endif 250 251 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 252 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = { 253 { 254 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0), 255 }, 256 { 257 .midr_range.model = MIDR_QCOM_KRYO, 258 .matches = is_kryo_midr, 259 }, 260 {}, 261 }; 262 #endif 263 264 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 265 static const struct midr_range workaround_clean_cache[] = { 266 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 267 defined(CONFIG_ARM64_ERRATUM_827319) || \ 268 defined(CONFIG_ARM64_ERRATUM_824069) 269 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */ 270 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2), 271 #endif 272 #ifdef CONFIG_ARM64_ERRATUM_819472 273 /* Cortex-A53 r0p[01] : ARM errata 819472 */ 274 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1), 275 #endif 276 {}, 277 }; 278 #endif 279 280 #ifdef CONFIG_ARM64_ERRATUM_1418040 281 /* 282 * - 1188873 affects r0p0 to r2p0 283 * - 1418040 affects r0p0 to r3p1 284 */ 285 static const struct midr_range erratum_1418040_list[] = { 286 /* Cortex-A76 r0p0 to r3p1 */ 287 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 288 /* Neoverse-N1 r0p0 to r3p1 */ 289 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1), 290 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 291 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 292 {}, 293 }; 294 #endif 295 296 #ifdef CONFIG_ARM64_ERRATUM_845719 297 static const struct midr_range erratum_845719_list[] = { 298 /* Cortex-A53 r0p[01234] */ 299 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 300 /* Brahma-B53 r0p[0] */ 301 MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 302 /* Kryo2XX Silver rAp4 */ 303 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4), 304 {}, 305 }; 306 #endif 307 308 #ifdef CONFIG_ARM64_ERRATUM_843419 309 static const struct arm64_cpu_capabilities erratum_843419_list[] = { 310 { 311 /* Cortex-A53 r0p[01234] */ 312 .matches = is_affected_midr_range, 313 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 314 MIDR_FIXED(0x4, BIT(8)), 315 }, 316 { 317 /* Brahma-B53 r0p[0] */ 318 .matches = is_affected_midr_range, 319 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 320 }, 321 {}, 322 }; 323 #endif 324 325 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 326 static const struct midr_range erratum_speculative_at_list[] = { 327 #ifdef CONFIG_ARM64_ERRATUM_1165522 328 /* Cortex A76 r0p0 to r2p0 */ 329 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), 330 #endif 331 #ifdef CONFIG_ARM64_ERRATUM_1319367 332 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 333 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 334 #endif 335 #ifdef CONFIG_ARM64_ERRATUM_1530923 336 /* Cortex A55 r0p0 to r2p0 */ 337 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0), 338 /* Kryo4xx Silver (rdpe => r1p0) */ 339 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 340 #endif 341 {}, 342 }; 343 #endif 344 345 #ifdef CONFIG_ARM64_ERRATUM_1463225 346 static const struct midr_range erratum_1463225[] = { 347 /* Cortex-A76 r0p0 - r3p1 */ 348 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 349 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 350 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 351 {}, 352 }; 353 #endif 354 355 const struct arm64_cpu_capabilities arm64_errata[] = { 356 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 357 { 358 .desc = "ARM errata 826319, 827319, 824069, or 819472", 359 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 360 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache), 361 .cpu_enable = cpu_enable_cache_maint_trap, 362 }, 363 #endif 364 #ifdef CONFIG_ARM64_ERRATUM_832075 365 { 366 /* Cortex-A57 r0p0 - r1p2 */ 367 .desc = "ARM erratum 832075", 368 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 369 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 370 0, 0, 371 1, 2), 372 }, 373 #endif 374 #ifdef CONFIG_ARM64_ERRATUM_834220 375 { 376 /* Cortex-A57 r0p0 - r1p2 */ 377 .desc = "ARM erratum 834220", 378 .capability = ARM64_WORKAROUND_834220, 379 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 380 0, 0, 381 1, 2), 382 }, 383 #endif 384 #ifdef CONFIG_ARM64_ERRATUM_843419 385 { 386 .desc = "ARM erratum 843419", 387 .capability = ARM64_WORKAROUND_843419, 388 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 389 .matches = cpucap_multi_entry_cap_matches, 390 .match_list = erratum_843419_list, 391 }, 392 #endif 393 #ifdef CONFIG_ARM64_ERRATUM_845719 394 { 395 .desc = "ARM erratum 845719", 396 .capability = ARM64_WORKAROUND_845719, 397 ERRATA_MIDR_RANGE_LIST(erratum_845719_list), 398 }, 399 #endif 400 #ifdef CONFIG_CAVIUM_ERRATUM_23154 401 { 402 /* Cavium ThunderX, pass 1.x */ 403 .desc = "Cavium erratum 23154", 404 .capability = ARM64_WORKAROUND_CAVIUM_23154, 405 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1), 406 }, 407 #endif 408 #ifdef CONFIG_CAVIUM_ERRATUM_27456 409 { 410 .desc = "Cavium erratum 27456", 411 .capability = ARM64_WORKAROUND_CAVIUM_27456, 412 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus), 413 }, 414 #endif 415 #ifdef CONFIG_CAVIUM_ERRATUM_30115 416 { 417 .desc = "Cavium erratum 30115", 418 .capability = ARM64_WORKAROUND_CAVIUM_30115, 419 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus), 420 }, 421 #endif 422 { 423 .desc = "Mismatched cache type (CTR_EL0)", 424 .capability = ARM64_MISMATCHED_CACHE_TYPE, 425 .matches = has_mismatched_cache_type, 426 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 427 .cpu_enable = cpu_enable_trap_ctr_access, 428 }, 429 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 430 { 431 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003", 432 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, 433 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 434 .matches = cpucap_multi_entry_cap_matches, 435 .match_list = qcom_erratum_1003_list, 436 }, 437 #endif 438 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 439 { 440 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807", 441 .capability = ARM64_WORKAROUND_REPEAT_TLBI, 442 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 443 .matches = cpucap_multi_entry_cap_matches, 444 .match_list = arm64_repeat_tlbi_list, 445 }, 446 #endif 447 #ifdef CONFIG_ARM64_ERRATUM_858921 448 { 449 /* Cortex-A73 all versions */ 450 .desc = "ARM erratum 858921", 451 .capability = ARM64_WORKAROUND_858921, 452 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 453 }, 454 #endif 455 { 456 .desc = "Spectre-v2", 457 .capability = ARM64_SPECTRE_V2, 458 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 459 .matches = has_spectre_v2, 460 .cpu_enable = spectre_v2_enable_mitigation, 461 }, 462 #ifdef CONFIG_RANDOMIZE_BASE 463 { 464 .desc = "EL2 vector hardening", 465 .capability = ARM64_HARDEN_EL2_VECTORS, 466 ERRATA_MIDR_RANGE_LIST(ca57_a72), 467 }, 468 #endif 469 { 470 .desc = "Spectre-v4", 471 .capability = ARM64_SPECTRE_V4, 472 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 473 .matches = has_spectre_v4, 474 .cpu_enable = spectre_v4_enable_mitigation, 475 }, 476 #ifdef CONFIG_ARM64_ERRATUM_1418040 477 { 478 .desc = "ARM erratum 1418040", 479 .capability = ARM64_WORKAROUND_1418040, 480 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list), 481 /* 482 * We need to allow affected CPUs to come in late, but 483 * also need the non-affected CPUs to be able to come 484 * in at any point in time. Wonderful. 485 */ 486 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 487 }, 488 #endif 489 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 490 { 491 .desc = "ARM errata 1165522, 1319367, or 1530923", 492 .capability = ARM64_WORKAROUND_SPECULATIVE_AT, 493 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list), 494 }, 495 #endif 496 #ifdef CONFIG_ARM64_ERRATUM_1463225 497 { 498 .desc = "ARM erratum 1463225", 499 .capability = ARM64_WORKAROUND_1463225, 500 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 501 .matches = has_cortex_a76_erratum_1463225, 502 .midr_range_list = erratum_1463225, 503 }, 504 #endif 505 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219 506 { 507 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)", 508 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM, 509 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 510 .matches = needs_tx2_tvm_workaround, 511 }, 512 { 513 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)", 514 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM, 515 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 516 }, 517 #endif 518 #ifdef CONFIG_ARM64_ERRATUM_1542419 519 { 520 /* we depend on the firmware portion for correctness */ 521 .desc = "ARM erratum 1542419 (kernel portion)", 522 .capability = ARM64_WORKAROUND_1542419, 523 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 524 .matches = has_neoverse_n1_erratum_1542419, 525 .cpu_enable = cpu_enable_trap_ctr_access, 526 }, 527 #endif 528 #ifdef CONFIG_ARM64_ERRATUM_1508412 529 { 530 /* we depend on the firmware portion for correctness */ 531 .desc = "ARM erratum 1508412 (kernel portion)", 532 .capability = ARM64_WORKAROUND_1508412, 533 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77, 534 0, 0, 535 1, 0), 536 }, 537 #endif 538 { 539 } 540 }; 541