1 /* 2 * Contains CPU specific errata definitions 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/types.h> 20 #include <asm/cpu.h> 21 #include <asm/cputype.h> 22 #include <asm/cpufeature.h> 23 24 static bool __maybe_unused 25 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) 26 { 27 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 28 return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model, 29 entry->midr_range_min, 30 entry->midr_range_max); 31 } 32 33 #define MIDR_RANGE(model, min, max) \ 34 .def_scope = SCOPE_LOCAL_CPU, \ 35 .matches = is_affected_midr_range, \ 36 .midr_model = model, \ 37 .midr_range_min = min, \ 38 .midr_range_max = max 39 40 const struct arm64_cpu_capabilities arm64_errata[] = { 41 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 42 defined(CONFIG_ARM64_ERRATUM_827319) || \ 43 defined(CONFIG_ARM64_ERRATUM_824069) 44 { 45 /* Cortex-A53 r0p[012] */ 46 .desc = "ARM errata 826319, 827319, 824069", 47 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 48 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02), 49 }, 50 #endif 51 #ifdef CONFIG_ARM64_ERRATUM_819472 52 { 53 /* Cortex-A53 r0p[01] */ 54 .desc = "ARM errata 819472", 55 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 56 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01), 57 }, 58 #endif 59 #ifdef CONFIG_ARM64_ERRATUM_832075 60 { 61 /* Cortex-A57 r0p0 - r1p2 */ 62 .desc = "ARM erratum 832075", 63 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 64 MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 65 (1 << MIDR_VARIANT_SHIFT) | 2), 66 }, 67 #endif 68 #ifdef CONFIG_ARM64_ERRATUM_834220 69 { 70 /* Cortex-A57 r0p0 - r1p2 */ 71 .desc = "ARM erratum 834220", 72 .capability = ARM64_WORKAROUND_834220, 73 MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 74 (1 << MIDR_VARIANT_SHIFT) | 2), 75 }, 76 #endif 77 #ifdef CONFIG_ARM64_ERRATUM_845719 78 { 79 /* Cortex-A53 r0p[01234] */ 80 .desc = "ARM erratum 845719", 81 .capability = ARM64_WORKAROUND_845719, 82 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), 83 }, 84 #endif 85 #ifdef CONFIG_CAVIUM_ERRATUM_23154 86 { 87 /* Cavium ThunderX, pass 1.x */ 88 .desc = "Cavium erratum 23154", 89 .capability = ARM64_WORKAROUND_CAVIUM_23154, 90 MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01), 91 }, 92 #endif 93 #ifdef CONFIG_CAVIUM_ERRATUM_27456 94 { 95 /* Cavium ThunderX, T88 pass 1.x - 2.1 */ 96 .desc = "Cavium erratum 27456", 97 .capability = ARM64_WORKAROUND_CAVIUM_27456, 98 MIDR_RANGE(MIDR_THUNDERX, 0x00, 99 (1 << MIDR_VARIANT_SHIFT) | 1), 100 }, 101 #endif 102 { 103 } 104 }; 105 106 /* 107 * The CPU Errata work arounds are detected and applied at boot time 108 * and the related information is freed soon after. If the new CPU requires 109 * an errata not detected at boot, fail this CPU. 110 */ 111 void verify_local_cpu_errata(void) 112 { 113 const struct arm64_cpu_capabilities *caps = arm64_errata; 114 115 for (; caps->matches; caps++) 116 if (!cpus_have_cap(caps->capability) && 117 caps->matches(caps, SCOPE_LOCAL_CPU)) { 118 pr_crit("CPU%d: Requires work around for %s, not detected" 119 " at boot time\n", 120 smp_processor_id(), 121 caps->desc ? : "an erratum"); 122 cpu_die_early(); 123 } 124 } 125 126 void check_local_cpu_errata(void) 127 { 128 update_cpu_capabilities(arm64_errata, "enabling workaround for"); 129 } 130