1 /* 2 * Contains CPU specific errata definitions 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/types.h> 20 #include <asm/cpu.h> 21 #include <asm/cputype.h> 22 #include <asm/cpufeature.h> 23 24 static bool __maybe_unused 25 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) 26 { 27 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 28 return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model, 29 entry->midr_range_min, 30 entry->midr_range_max); 31 } 32 33 #define MIDR_RANGE(model, min, max) \ 34 .def_scope = SCOPE_LOCAL_CPU, \ 35 .matches = is_affected_midr_range, \ 36 .midr_model = model, \ 37 .midr_range_min = min, \ 38 .midr_range_max = max 39 40 const struct arm64_cpu_capabilities arm64_errata[] = { 41 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 42 defined(CONFIG_ARM64_ERRATUM_827319) || \ 43 defined(CONFIG_ARM64_ERRATUM_824069) 44 { 45 /* Cortex-A53 r0p[012] */ 46 .desc = "ARM errata 826319, 827319, 824069", 47 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 48 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02), 49 .enable = cpu_enable_cache_maint_trap, 50 }, 51 #endif 52 #ifdef CONFIG_ARM64_ERRATUM_819472 53 { 54 /* Cortex-A53 r0p[01] */ 55 .desc = "ARM errata 819472", 56 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 57 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01), 58 .enable = cpu_enable_cache_maint_trap, 59 }, 60 #endif 61 #ifdef CONFIG_ARM64_ERRATUM_832075 62 { 63 /* Cortex-A57 r0p0 - r1p2 */ 64 .desc = "ARM erratum 832075", 65 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 66 MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 67 (1 << MIDR_VARIANT_SHIFT) | 2), 68 }, 69 #endif 70 #ifdef CONFIG_ARM64_ERRATUM_834220 71 { 72 /* Cortex-A57 r0p0 - r1p2 */ 73 .desc = "ARM erratum 834220", 74 .capability = ARM64_WORKAROUND_834220, 75 MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 76 (1 << MIDR_VARIANT_SHIFT) | 2), 77 }, 78 #endif 79 #ifdef CONFIG_ARM64_ERRATUM_845719 80 { 81 /* Cortex-A53 r0p[01234] */ 82 .desc = "ARM erratum 845719", 83 .capability = ARM64_WORKAROUND_845719, 84 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), 85 }, 86 #endif 87 #ifdef CONFIG_CAVIUM_ERRATUM_23154 88 { 89 /* Cavium ThunderX, pass 1.x */ 90 .desc = "Cavium erratum 23154", 91 .capability = ARM64_WORKAROUND_CAVIUM_23154, 92 MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01), 93 }, 94 #endif 95 #ifdef CONFIG_CAVIUM_ERRATUM_27456 96 { 97 /* Cavium ThunderX, T88 pass 1.x - 2.1 */ 98 .desc = "Cavium erratum 27456", 99 .capability = ARM64_WORKAROUND_CAVIUM_27456, 100 MIDR_RANGE(MIDR_THUNDERX, 0x00, 101 (1 << MIDR_VARIANT_SHIFT) | 1), 102 }, 103 { 104 /* Cavium ThunderX, T81 pass 1.0 */ 105 .desc = "Cavium erratum 27456", 106 .capability = ARM64_WORKAROUND_CAVIUM_27456, 107 MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00), 108 }, 109 #endif 110 { 111 } 112 }; 113 114 /* 115 * The CPU Errata work arounds are detected and applied at boot time 116 * and the related information is freed soon after. If the new CPU requires 117 * an errata not detected at boot, fail this CPU. 118 */ 119 void verify_local_cpu_errata(void) 120 { 121 const struct arm64_cpu_capabilities *caps = arm64_errata; 122 123 for (; caps->matches; caps++) 124 if (!cpus_have_cap(caps->capability) && 125 caps->matches(caps, SCOPE_LOCAL_CPU)) { 126 pr_crit("CPU%d: Requires work around for %s, not detected" 127 " at boot time\n", 128 smp_processor_id(), 129 caps->desc ? : "an erratum"); 130 cpu_die_early(); 131 } 132 } 133 134 void check_local_cpu_errata(void) 135 { 136 update_cpu_capabilities(arm64_errata, "enabling workaround for"); 137 } 138 139 void __init enable_errata_workarounds(void) 140 { 141 enable_cpu_capabilities(arm64_errata); 142 } 143