1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU specific errata definitions 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 8 #include <linux/arm-smccc.h> 9 #include <linux/types.h> 10 #include <linux/cpu.h> 11 #include <asm/cpu.h> 12 #include <asm/cputype.h> 13 #include <asm/cpufeature.h> 14 #include <asm/kvm_asm.h> 15 #include <asm/smp_plat.h> 16 17 static bool __maybe_unused 18 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) 19 { 20 const struct arm64_midr_revidr *fix; 21 u32 midr = read_cpuid_id(), revidr; 22 23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 24 if (!is_midr_in_range(midr, &entry->midr_range)) 25 return false; 26 27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; 28 revidr = read_cpuid(REVIDR_EL1); 29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) 30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) 31 return false; 32 33 return true; 34 } 35 36 static bool __maybe_unused 37 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry, 38 int scope) 39 { 40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list); 42 } 43 44 static bool __maybe_unused 45 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) 46 { 47 u32 model; 48 49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 50 51 model = read_cpuid_id(); 52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) | 53 MIDR_ARCHITECTURE_MASK; 54 55 return model == entry->midr_range.model; 56 } 57 58 static bool 59 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, 60 int scope) 61 { 62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask; 64 u64 ctr_raw, ctr_real; 65 66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 67 68 /* 69 * We want to make sure that all the CPUs in the system expose 70 * a consistent CTR_EL0 to make sure that applications behaves 71 * correctly with migration. 72 * 73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 : 74 * 75 * 1) It is safe if the system doesn't support IDC, as CPU anyway 76 * reports IDC = 0, consistent with the rest. 77 * 78 * 2) If the system has IDC, it is still safe as we trap CTR_EL0 79 * access on this CPU via the ARM64_HAS_CACHE_IDC capability. 80 * 81 * So, we need to make sure either the raw CTR_EL0 or the effective 82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot. 83 */ 84 ctr_raw = read_cpuid_cachetype() & mask; 85 ctr_real = read_cpuid_effective_cachetype() & mask; 86 87 return (ctr_real != sys) && (ctr_raw != sys); 88 } 89 90 static void 91 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) 92 { 93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 94 bool enable_uct_trap = false; 95 96 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */ 97 if ((read_cpuid_cachetype() & mask) != 98 (arm64_ftr_reg_ctrel0.sys_val & mask)) 99 enable_uct_trap = true; 100 101 /* ... or if the system is affected by an erratum */ 102 if (cap->capability == ARM64_WORKAROUND_1542419) 103 enable_uct_trap = true; 104 105 if (enable_uct_trap) 106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 107 } 108 109 #ifdef CONFIG_ARM64_ERRATUM_1463225 110 static bool 111 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry, 112 int scope) 113 { 114 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode(); 115 } 116 #endif 117 118 static void __maybe_unused 119 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) 120 { 121 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); 122 } 123 124 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 125 .matches = is_affected_midr_range, \ 126 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) 127 128 #define CAP_MIDR_ALL_VERSIONS(model) \ 129 .matches = is_affected_midr_range, \ 130 .midr_range = MIDR_ALL_VERSIONS(model) 131 132 #define MIDR_FIXED(rev, revidr_mask) \ 133 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}} 134 135 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 136 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 137 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) 138 139 #define CAP_MIDR_RANGE_LIST(list) \ 140 .matches = is_affected_midr_range_list, \ 141 .midr_range_list = list 142 143 /* Errata affecting a range of revisions of given model variant */ 144 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \ 145 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) 146 147 /* Errata affecting a single variant/revision of a model */ 148 #define ERRATA_MIDR_REV(model, var, rev) \ 149 ERRATA_MIDR_RANGE(model, var, rev, var, rev) 150 151 /* Errata affecting all variants/revisions of a given a model */ 152 #define ERRATA_MIDR_ALL_VERSIONS(model) \ 153 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 154 CAP_MIDR_ALL_VERSIONS(model) 155 156 /* Errata affecting a list of midr ranges, with same work around */ 157 #define ERRATA_MIDR_RANGE_LIST(midr_list) \ 158 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 159 CAP_MIDR_RANGE_LIST(midr_list) 160 161 static const __maybe_unused struct midr_range tx2_family_cpus[] = { 162 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 163 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 164 {}, 165 }; 166 167 static bool __maybe_unused 168 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, 169 int scope) 170 { 171 int i; 172 173 if (!is_affected_midr_range_list(entry, scope) || 174 !is_hyp_mode_available()) 175 return false; 176 177 for_each_possible_cpu(i) { 178 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0) 179 return true; 180 } 181 182 return false; 183 } 184 185 static bool __maybe_unused 186 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, 187 int scope) 188 { 189 u32 midr = read_cpuid_id(); 190 bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT); 191 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); 192 193 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 194 return is_midr_in_range(midr, &range) && has_dic; 195 } 196 197 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 198 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { 199 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 200 { 201 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0) 202 }, 203 { 204 .midr_range.model = MIDR_QCOM_KRYO, 205 .matches = is_kryo_midr, 206 }, 207 #endif 208 #ifdef CONFIG_ARM64_ERRATUM_1286807 209 { 210 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), 211 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */ 212 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), 213 }, 214 #endif 215 #ifdef CONFIG_ARM64_ERRATUM_2441009 216 { 217 /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */ 218 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), 219 }, 220 #endif 221 {}, 222 }; 223 #endif 224 225 #ifdef CONFIG_CAVIUM_ERRATUM_23154 226 static const struct midr_range cavium_erratum_23154_cpus[] = { 227 MIDR_ALL_VERSIONS(MIDR_THUNDERX), 228 MIDR_ALL_VERSIONS(MIDR_THUNDERX_81XX), 229 MIDR_ALL_VERSIONS(MIDR_THUNDERX_83XX), 230 MIDR_ALL_VERSIONS(MIDR_OCTX2_98XX), 231 MIDR_ALL_VERSIONS(MIDR_OCTX2_96XX), 232 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XX), 233 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN), 234 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM), 235 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO), 236 {}, 237 }; 238 #endif 239 240 #ifdef CONFIG_CAVIUM_ERRATUM_27456 241 const struct midr_range cavium_erratum_27456_cpus[] = { 242 /* Cavium ThunderX, T88 pass 1.x - 2.1 */ 243 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1), 244 /* Cavium ThunderX, T81 pass 1.0 */ 245 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0), 246 {}, 247 }; 248 #endif 249 250 #ifdef CONFIG_CAVIUM_ERRATUM_30115 251 static const struct midr_range cavium_erratum_30115_cpus[] = { 252 /* Cavium ThunderX, T88 pass 1.x - 2.2 */ 253 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2), 254 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ 255 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2), 256 /* Cavium ThunderX, T83 pass 1.0 */ 257 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0), 258 {}, 259 }; 260 #endif 261 262 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 263 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = { 264 { 265 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0), 266 }, 267 { 268 .midr_range.model = MIDR_QCOM_KRYO, 269 .matches = is_kryo_midr, 270 }, 271 {}, 272 }; 273 #endif 274 275 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 276 static const struct midr_range workaround_clean_cache[] = { 277 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 278 defined(CONFIG_ARM64_ERRATUM_827319) || \ 279 defined(CONFIG_ARM64_ERRATUM_824069) 280 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */ 281 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2), 282 #endif 283 #ifdef CONFIG_ARM64_ERRATUM_819472 284 /* Cortex-A53 r0p[01] : ARM errata 819472 */ 285 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1), 286 #endif 287 {}, 288 }; 289 #endif 290 291 #ifdef CONFIG_ARM64_ERRATUM_1418040 292 /* 293 * - 1188873 affects r0p0 to r2p0 294 * - 1418040 affects r0p0 to r3p1 295 */ 296 static const struct midr_range erratum_1418040_list[] = { 297 /* Cortex-A76 r0p0 to r3p1 */ 298 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 299 /* Neoverse-N1 r0p0 to r3p1 */ 300 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1), 301 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 302 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 303 {}, 304 }; 305 #endif 306 307 #ifdef CONFIG_ARM64_ERRATUM_845719 308 static const struct midr_range erratum_845719_list[] = { 309 /* Cortex-A53 r0p[01234] */ 310 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 311 /* Brahma-B53 r0p[0] */ 312 MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 313 /* Kryo2XX Silver rAp4 */ 314 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4), 315 {}, 316 }; 317 #endif 318 319 #ifdef CONFIG_ARM64_ERRATUM_843419 320 static const struct arm64_cpu_capabilities erratum_843419_list[] = { 321 { 322 /* Cortex-A53 r0p[01234] */ 323 .matches = is_affected_midr_range, 324 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 325 MIDR_FIXED(0x4, BIT(8)), 326 }, 327 { 328 /* Brahma-B53 r0p[0] */ 329 .matches = is_affected_midr_range, 330 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 331 }, 332 {}, 333 }; 334 #endif 335 336 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 337 static const struct midr_range erratum_speculative_at_list[] = { 338 #ifdef CONFIG_ARM64_ERRATUM_1165522 339 /* Cortex A76 r0p0 to r2p0 */ 340 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), 341 #endif 342 #ifdef CONFIG_ARM64_ERRATUM_1319367 343 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 344 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 345 #endif 346 #ifdef CONFIG_ARM64_ERRATUM_1530923 347 /* Cortex A55 r0p0 to r2p0 */ 348 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0), 349 /* Kryo4xx Silver (rdpe => r1p0) */ 350 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 351 #endif 352 {}, 353 }; 354 #endif 355 356 #ifdef CONFIG_ARM64_ERRATUM_1463225 357 static const struct midr_range erratum_1463225[] = { 358 /* Cortex-A76 r0p0 - r3p1 */ 359 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 360 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 361 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 362 {}, 363 }; 364 #endif 365 366 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 367 static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { 368 #ifdef CONFIG_ARM64_ERRATUM_2139208 369 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 370 #endif 371 #ifdef CONFIG_ARM64_ERRATUM_2119858 372 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 373 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 374 #endif 375 {}, 376 }; 377 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ 378 379 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 380 static const struct midr_range tsb_flush_fail_cpus[] = { 381 #ifdef CONFIG_ARM64_ERRATUM_2067961 382 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 383 #endif 384 #ifdef CONFIG_ARM64_ERRATUM_2054223 385 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 386 #endif 387 {}, 388 }; 389 #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ 390 391 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 392 static struct midr_range trbe_write_out_of_range_cpus[] = { 393 #ifdef CONFIG_ARM64_ERRATUM_2253138 394 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 395 #endif 396 #ifdef CONFIG_ARM64_ERRATUM_2224489 397 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 398 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 399 #endif 400 {}, 401 }; 402 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 403 404 #ifdef CONFIG_ARM64_ERRATUM_1742098 405 static struct midr_range broken_aarch32_aes[] = { 406 MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf), 407 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 408 {}, 409 }; 410 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 411 412 const struct arm64_cpu_capabilities arm64_errata[] = { 413 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 414 { 415 .desc = "ARM errata 826319, 827319, 824069, or 819472", 416 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 417 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache), 418 .cpu_enable = cpu_enable_cache_maint_trap, 419 }, 420 #endif 421 #ifdef CONFIG_ARM64_ERRATUM_832075 422 { 423 /* Cortex-A57 r0p0 - r1p2 */ 424 .desc = "ARM erratum 832075", 425 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 426 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 427 0, 0, 428 1, 2), 429 }, 430 #endif 431 #ifdef CONFIG_ARM64_ERRATUM_834220 432 { 433 /* Cortex-A57 r0p0 - r1p2 */ 434 .desc = "ARM erratum 834220", 435 .capability = ARM64_WORKAROUND_834220, 436 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 437 0, 0, 438 1, 2), 439 }, 440 #endif 441 #ifdef CONFIG_ARM64_ERRATUM_843419 442 { 443 .desc = "ARM erratum 843419", 444 .capability = ARM64_WORKAROUND_843419, 445 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 446 .matches = cpucap_multi_entry_cap_matches, 447 .match_list = erratum_843419_list, 448 }, 449 #endif 450 #ifdef CONFIG_ARM64_ERRATUM_845719 451 { 452 .desc = "ARM erratum 845719", 453 .capability = ARM64_WORKAROUND_845719, 454 ERRATA_MIDR_RANGE_LIST(erratum_845719_list), 455 }, 456 #endif 457 #ifdef CONFIG_CAVIUM_ERRATUM_23154 458 { 459 .desc = "Cavium errata 23154 and 38545", 460 .capability = ARM64_WORKAROUND_CAVIUM_23154, 461 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 462 ERRATA_MIDR_RANGE_LIST(cavium_erratum_23154_cpus), 463 }, 464 #endif 465 #ifdef CONFIG_CAVIUM_ERRATUM_27456 466 { 467 .desc = "Cavium erratum 27456", 468 .capability = ARM64_WORKAROUND_CAVIUM_27456, 469 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus), 470 }, 471 #endif 472 #ifdef CONFIG_CAVIUM_ERRATUM_30115 473 { 474 .desc = "Cavium erratum 30115", 475 .capability = ARM64_WORKAROUND_CAVIUM_30115, 476 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus), 477 }, 478 #endif 479 { 480 .desc = "Mismatched cache type (CTR_EL0)", 481 .capability = ARM64_MISMATCHED_CACHE_TYPE, 482 .matches = has_mismatched_cache_type, 483 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 484 .cpu_enable = cpu_enable_trap_ctr_access, 485 }, 486 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 487 { 488 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003", 489 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, 490 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 491 .matches = cpucap_multi_entry_cap_matches, 492 .match_list = qcom_erratum_1003_list, 493 }, 494 #endif 495 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 496 { 497 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009", 498 .capability = ARM64_WORKAROUND_REPEAT_TLBI, 499 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 500 .matches = cpucap_multi_entry_cap_matches, 501 .match_list = arm64_repeat_tlbi_list, 502 }, 503 #endif 504 #ifdef CONFIG_ARM64_ERRATUM_858921 505 { 506 /* Cortex-A73 all versions */ 507 .desc = "ARM erratum 858921", 508 .capability = ARM64_WORKAROUND_858921, 509 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 510 }, 511 #endif 512 { 513 .desc = "Spectre-v2", 514 .capability = ARM64_SPECTRE_V2, 515 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 516 .matches = has_spectre_v2, 517 .cpu_enable = spectre_v2_enable_mitigation, 518 }, 519 #ifdef CONFIG_RANDOMIZE_BASE 520 { 521 /* Must come after the Spectre-v2 entry */ 522 .desc = "Spectre-v3a", 523 .capability = ARM64_SPECTRE_V3A, 524 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 525 .matches = has_spectre_v3a, 526 .cpu_enable = spectre_v3a_enable_mitigation, 527 }, 528 #endif 529 { 530 .desc = "Spectre-v4", 531 .capability = ARM64_SPECTRE_V4, 532 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 533 .matches = has_spectre_v4, 534 .cpu_enable = spectre_v4_enable_mitigation, 535 }, 536 { 537 .desc = "Spectre-BHB", 538 .capability = ARM64_SPECTRE_BHB, 539 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 540 .matches = is_spectre_bhb_affected, 541 .cpu_enable = spectre_bhb_enable_mitigation, 542 }, 543 #ifdef CONFIG_ARM64_ERRATUM_1418040 544 { 545 .desc = "ARM erratum 1418040", 546 .capability = ARM64_WORKAROUND_1418040, 547 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list), 548 /* 549 * We need to allow affected CPUs to come in late, but 550 * also need the non-affected CPUs to be able to come 551 * in at any point in time. Wonderful. 552 */ 553 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 554 }, 555 #endif 556 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 557 { 558 .desc = "ARM errata 1165522, 1319367, or 1530923", 559 .capability = ARM64_WORKAROUND_SPECULATIVE_AT, 560 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list), 561 }, 562 #endif 563 #ifdef CONFIG_ARM64_ERRATUM_1463225 564 { 565 .desc = "ARM erratum 1463225", 566 .capability = ARM64_WORKAROUND_1463225, 567 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 568 .matches = has_cortex_a76_erratum_1463225, 569 .midr_range_list = erratum_1463225, 570 }, 571 #endif 572 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219 573 { 574 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)", 575 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM, 576 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 577 .matches = needs_tx2_tvm_workaround, 578 }, 579 { 580 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)", 581 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM, 582 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 583 }, 584 #endif 585 #ifdef CONFIG_ARM64_ERRATUM_1542419 586 { 587 /* we depend on the firmware portion for correctness */ 588 .desc = "ARM erratum 1542419 (kernel portion)", 589 .capability = ARM64_WORKAROUND_1542419, 590 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 591 .matches = has_neoverse_n1_erratum_1542419, 592 .cpu_enable = cpu_enable_trap_ctr_access, 593 }, 594 #endif 595 #ifdef CONFIG_ARM64_ERRATUM_1508412 596 { 597 /* we depend on the firmware portion for correctness */ 598 .desc = "ARM erratum 1508412 (kernel portion)", 599 .capability = ARM64_WORKAROUND_1508412, 600 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77, 601 0, 0, 602 1, 0), 603 }, 604 #endif 605 #ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM 606 { 607 /* NVIDIA Carmel */ 608 .desc = "NVIDIA Carmel CNP erratum", 609 .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP, 610 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 611 }, 612 #endif 613 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 614 { 615 /* 616 * The erratum work around is handled within the TRBE 617 * driver and can be applied per-cpu. So, we can allow 618 * a late CPU to come online with this erratum. 619 */ 620 .desc = "ARM erratum 2119858 or 2139208", 621 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, 622 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 623 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), 624 }, 625 #endif 626 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 627 { 628 .desc = "ARM erratum 2067961 or 2054223", 629 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, 630 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus), 631 }, 632 #endif 633 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 634 { 635 .desc = "ARM erratum 2253138 or 2224489", 636 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, 637 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 638 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), 639 }, 640 #endif 641 #ifdef CONFIG_ARM64_ERRATUM_2077057 642 { 643 .desc = "ARM erratum 2077057", 644 .capability = ARM64_WORKAROUND_2077057, 645 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 646 }, 647 #endif 648 #ifdef CONFIG_ARM64_ERRATUM_2064142 649 { 650 .desc = "ARM erratum 2064142", 651 .capability = ARM64_WORKAROUND_2064142, 652 653 /* Cortex-A510 r0p0 - r0p2 */ 654 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 655 }, 656 #endif 657 #ifdef CONFIG_ARM64_ERRATUM_2038923 658 { 659 .desc = "ARM erratum 2038923", 660 .capability = ARM64_WORKAROUND_2038923, 661 662 /* Cortex-A510 r0p0 - r0p2 */ 663 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 664 }, 665 #endif 666 #ifdef CONFIG_ARM64_ERRATUM_1902691 667 { 668 .desc = "ARM erratum 1902691", 669 .capability = ARM64_WORKAROUND_1902691, 670 671 /* Cortex-A510 r0p0 - r0p1 */ 672 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1) 673 }, 674 #endif 675 #ifdef CONFIG_ARM64_ERRATUM_1742098 676 { 677 .desc = "ARM erratum 1742098", 678 .capability = ARM64_WORKAROUND_1742098, 679 CAP_MIDR_RANGE_LIST(broken_aarch32_aes), 680 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 681 }, 682 #endif 683 { 684 } 685 }; 686