1 /* 2 * Contains CPU specific errata definitions 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/types.h> 20 #include <asm/cpu.h> 21 #include <asm/cputype.h> 22 #include <asm/cpufeature.h> 23 24 static bool __maybe_unused 25 is_affected_midr_range(const struct arm64_cpu_capabilities *entry) 26 { 27 return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model, 28 entry->midr_range_min, 29 entry->midr_range_max); 30 } 31 32 #define MIDR_RANGE(model, min, max) \ 33 .matches = is_affected_midr_range, \ 34 .midr_model = model, \ 35 .midr_range_min = min, \ 36 .midr_range_max = max 37 38 const struct arm64_cpu_capabilities arm64_errata[] = { 39 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 40 defined(CONFIG_ARM64_ERRATUM_827319) || \ 41 defined(CONFIG_ARM64_ERRATUM_824069) 42 { 43 /* Cortex-A53 r0p[012] */ 44 .desc = "ARM errata 826319, 827319, 824069", 45 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 46 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02), 47 }, 48 #endif 49 #ifdef CONFIG_ARM64_ERRATUM_819472 50 { 51 /* Cortex-A53 r0p[01] */ 52 .desc = "ARM errata 819472", 53 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 54 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01), 55 }, 56 #endif 57 #ifdef CONFIG_ARM64_ERRATUM_832075 58 { 59 /* Cortex-A57 r0p0 - r1p2 */ 60 .desc = "ARM erratum 832075", 61 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 62 MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 63 (1 << MIDR_VARIANT_SHIFT) | 2), 64 }, 65 #endif 66 #ifdef CONFIG_ARM64_ERRATUM_834220 67 { 68 /* Cortex-A57 r0p0 - r1p2 */ 69 .desc = "ARM erratum 834220", 70 .capability = ARM64_WORKAROUND_834220, 71 MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 72 (1 << MIDR_VARIANT_SHIFT) | 2), 73 }, 74 #endif 75 #ifdef CONFIG_ARM64_ERRATUM_845719 76 { 77 /* Cortex-A53 r0p[01234] */ 78 .desc = "ARM erratum 845719", 79 .capability = ARM64_WORKAROUND_845719, 80 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), 81 }, 82 #endif 83 #ifdef CONFIG_CAVIUM_ERRATUM_23154 84 { 85 /* Cavium ThunderX, pass 1.x */ 86 .desc = "Cavium erratum 23154", 87 .capability = ARM64_WORKAROUND_CAVIUM_23154, 88 MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01), 89 }, 90 #endif 91 #ifdef CONFIG_CAVIUM_ERRATUM_27456 92 { 93 /* Cavium ThunderX, T88 pass 1.x - 2.1 */ 94 .desc = "Cavium erratum 27456", 95 .capability = ARM64_WORKAROUND_CAVIUM_27456, 96 MIDR_RANGE(MIDR_THUNDERX, 0x00, 97 (1 << MIDR_VARIANT_SHIFT) | 1), 98 }, 99 #endif 100 { 101 } 102 }; 103 104 void check_local_cpu_errata(void) 105 { 106 update_cpu_capabilities(arm64_errata, "enabling workaround for"); 107 } 108