1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU specific errata definitions 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 8 #include <linux/arm-smccc.h> 9 #include <linux/types.h> 10 #include <linux/cpu.h> 11 #include <asm/cpu.h> 12 #include <asm/cputype.h> 13 #include <asm/cpufeature.h> 14 #include <asm/kvm_asm.h> 15 #include <asm/smp_plat.h> 16 17 static bool __maybe_unused 18 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) 19 { 20 const struct arm64_midr_revidr *fix; 21 u32 midr = read_cpuid_id(), revidr; 22 23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 24 if (!is_midr_in_range(midr, &entry->midr_range)) 25 return false; 26 27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; 28 revidr = read_cpuid(REVIDR_EL1); 29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) 30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) 31 return false; 32 33 return true; 34 } 35 36 static bool __maybe_unused 37 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry, 38 int scope) 39 { 40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list); 42 } 43 44 static bool __maybe_unused 45 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) 46 { 47 u32 model; 48 49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 50 51 model = read_cpuid_id(); 52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) | 53 MIDR_ARCHITECTURE_MASK; 54 55 return model == entry->midr_range.model; 56 } 57 58 static bool 59 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, 60 int scope) 61 { 62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask; 64 u64 ctr_raw, ctr_real; 65 66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 67 68 /* 69 * We want to make sure that all the CPUs in the system expose 70 * a consistent CTR_EL0 to make sure that applications behaves 71 * correctly with migration. 72 * 73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 : 74 * 75 * 1) It is safe if the system doesn't support IDC, as CPU anyway 76 * reports IDC = 0, consistent with the rest. 77 * 78 * 2) If the system has IDC, it is still safe as we trap CTR_EL0 79 * access on this CPU via the ARM64_HAS_CACHE_IDC capability. 80 * 81 * So, we need to make sure either the raw CTR_EL0 or the effective 82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot. 83 */ 84 ctr_raw = read_cpuid_cachetype() & mask; 85 ctr_real = read_cpuid_effective_cachetype() & mask; 86 87 return (ctr_real != sys) && (ctr_raw != sys); 88 } 89 90 static void 91 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) 92 { 93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 94 bool enable_uct_trap = false; 95 96 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */ 97 if ((read_cpuid_cachetype() & mask) != 98 (arm64_ftr_reg_ctrel0.sys_val & mask)) 99 enable_uct_trap = true; 100 101 /* ... or if the system is affected by an erratum */ 102 if (cap->capability == ARM64_WORKAROUND_1542419) 103 enable_uct_trap = true; 104 105 if (enable_uct_trap) 106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 107 } 108 109 #ifdef CONFIG_ARM64_ERRATUM_1463225 110 static bool 111 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry, 112 int scope) 113 { 114 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode(); 115 } 116 #endif 117 118 static void __maybe_unused 119 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) 120 { 121 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); 122 } 123 124 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 125 .matches = is_affected_midr_range, \ 126 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) 127 128 #define CAP_MIDR_ALL_VERSIONS(model) \ 129 .matches = is_affected_midr_range, \ 130 .midr_range = MIDR_ALL_VERSIONS(model) 131 132 #define MIDR_FIXED(rev, revidr_mask) \ 133 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}} 134 135 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 136 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 137 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) 138 139 #define CAP_MIDR_RANGE_LIST(list) \ 140 .matches = is_affected_midr_range_list, \ 141 .midr_range_list = list 142 143 /* Errata affecting a range of revisions of given model variant */ 144 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \ 145 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) 146 147 /* Errata affecting a single variant/revision of a model */ 148 #define ERRATA_MIDR_REV(model, var, rev) \ 149 ERRATA_MIDR_RANGE(model, var, rev, var, rev) 150 151 /* Errata affecting all variants/revisions of a given a model */ 152 #define ERRATA_MIDR_ALL_VERSIONS(model) \ 153 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 154 CAP_MIDR_ALL_VERSIONS(model) 155 156 /* Errata affecting a list of midr ranges, with same work around */ 157 #define ERRATA_MIDR_RANGE_LIST(midr_list) \ 158 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 159 CAP_MIDR_RANGE_LIST(midr_list) 160 161 static const __maybe_unused struct midr_range tx2_family_cpus[] = { 162 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 163 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 164 {}, 165 }; 166 167 static bool __maybe_unused 168 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, 169 int scope) 170 { 171 int i; 172 173 if (!is_affected_midr_range_list(entry, scope) || 174 !is_hyp_mode_available()) 175 return false; 176 177 for_each_possible_cpu(i) { 178 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0) 179 return true; 180 } 181 182 return false; 183 } 184 185 static bool __maybe_unused 186 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, 187 int scope) 188 { 189 u32 midr = read_cpuid_id(); 190 bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT); 191 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); 192 193 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 194 return is_midr_in_range(midr, &range) && has_dic; 195 } 196 197 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 198 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { 199 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 200 { 201 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0) 202 }, 203 { 204 .midr_range.model = MIDR_QCOM_KRYO, 205 .matches = is_kryo_midr, 206 }, 207 #endif 208 #ifdef CONFIG_ARM64_ERRATUM_1286807 209 { 210 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), 211 }, 212 #endif 213 {}, 214 }; 215 #endif 216 217 #ifdef CONFIG_CAVIUM_ERRATUM_23154 218 const struct midr_range cavium_erratum_23154_cpus[] = { 219 MIDR_ALL_VERSIONS(MIDR_THUNDERX), 220 MIDR_ALL_VERSIONS(MIDR_THUNDERX_81XX), 221 MIDR_ALL_VERSIONS(MIDR_THUNDERX_83XX), 222 MIDR_ALL_VERSIONS(MIDR_OCTX2_98XX), 223 MIDR_ALL_VERSIONS(MIDR_OCTX2_96XX), 224 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XX), 225 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN), 226 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM), 227 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO), 228 {}, 229 }; 230 #endif 231 232 #ifdef CONFIG_CAVIUM_ERRATUM_27456 233 const struct midr_range cavium_erratum_27456_cpus[] = { 234 /* Cavium ThunderX, T88 pass 1.x - 2.1 */ 235 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1), 236 /* Cavium ThunderX, T81 pass 1.0 */ 237 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0), 238 {}, 239 }; 240 #endif 241 242 #ifdef CONFIG_CAVIUM_ERRATUM_30115 243 static const struct midr_range cavium_erratum_30115_cpus[] = { 244 /* Cavium ThunderX, T88 pass 1.x - 2.2 */ 245 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2), 246 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ 247 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2), 248 /* Cavium ThunderX, T83 pass 1.0 */ 249 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0), 250 {}, 251 }; 252 #endif 253 254 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 255 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = { 256 { 257 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0), 258 }, 259 { 260 .midr_range.model = MIDR_QCOM_KRYO, 261 .matches = is_kryo_midr, 262 }, 263 {}, 264 }; 265 #endif 266 267 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 268 static const struct midr_range workaround_clean_cache[] = { 269 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 270 defined(CONFIG_ARM64_ERRATUM_827319) || \ 271 defined(CONFIG_ARM64_ERRATUM_824069) 272 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */ 273 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2), 274 #endif 275 #ifdef CONFIG_ARM64_ERRATUM_819472 276 /* Cortex-A53 r0p[01] : ARM errata 819472 */ 277 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1), 278 #endif 279 {}, 280 }; 281 #endif 282 283 #ifdef CONFIG_ARM64_ERRATUM_1418040 284 /* 285 * - 1188873 affects r0p0 to r2p0 286 * - 1418040 affects r0p0 to r3p1 287 */ 288 static const struct midr_range erratum_1418040_list[] = { 289 /* Cortex-A76 r0p0 to r3p1 */ 290 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 291 /* Neoverse-N1 r0p0 to r3p1 */ 292 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1), 293 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 294 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 295 {}, 296 }; 297 #endif 298 299 #ifdef CONFIG_ARM64_ERRATUM_845719 300 static const struct midr_range erratum_845719_list[] = { 301 /* Cortex-A53 r0p[01234] */ 302 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 303 /* Brahma-B53 r0p[0] */ 304 MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 305 /* Kryo2XX Silver rAp4 */ 306 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4), 307 {}, 308 }; 309 #endif 310 311 #ifdef CONFIG_ARM64_ERRATUM_843419 312 static const struct arm64_cpu_capabilities erratum_843419_list[] = { 313 { 314 /* Cortex-A53 r0p[01234] */ 315 .matches = is_affected_midr_range, 316 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 317 MIDR_FIXED(0x4, BIT(8)), 318 }, 319 { 320 /* Brahma-B53 r0p[0] */ 321 .matches = is_affected_midr_range, 322 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 323 }, 324 {}, 325 }; 326 #endif 327 328 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 329 static const struct midr_range erratum_speculative_at_list[] = { 330 #ifdef CONFIG_ARM64_ERRATUM_1165522 331 /* Cortex A76 r0p0 to r2p0 */ 332 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), 333 #endif 334 #ifdef CONFIG_ARM64_ERRATUM_1319367 335 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 336 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 337 #endif 338 #ifdef CONFIG_ARM64_ERRATUM_1530923 339 /* Cortex A55 r0p0 to r2p0 */ 340 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0), 341 /* Kryo4xx Silver (rdpe => r1p0) */ 342 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 343 #endif 344 {}, 345 }; 346 #endif 347 348 #ifdef CONFIG_ARM64_ERRATUM_1463225 349 static const struct midr_range erratum_1463225[] = { 350 /* Cortex-A76 r0p0 - r3p1 */ 351 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 352 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 353 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 354 {}, 355 }; 356 #endif 357 358 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 359 static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { 360 #ifdef CONFIG_ARM64_ERRATUM_2139208 361 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 362 #endif 363 #ifdef CONFIG_ARM64_ERRATUM_2119858 364 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 365 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 366 #endif 367 {}, 368 }; 369 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ 370 371 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 372 static const struct midr_range tsb_flush_fail_cpus[] = { 373 #ifdef CONFIG_ARM64_ERRATUM_2067961 374 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 375 #endif 376 #ifdef CONFIG_ARM64_ERRATUM_2054223 377 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 378 #endif 379 {}, 380 }; 381 #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ 382 383 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 384 static struct midr_range trbe_write_out_of_range_cpus[] = { 385 #ifdef CONFIG_ARM64_ERRATUM_2253138 386 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 387 #endif 388 #ifdef CONFIG_ARM64_ERRATUM_2224489 389 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 390 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 391 #endif 392 {}, 393 }; 394 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 395 396 const struct arm64_cpu_capabilities arm64_errata[] = { 397 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 398 { 399 .desc = "ARM errata 826319, 827319, 824069, or 819472", 400 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 401 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache), 402 .cpu_enable = cpu_enable_cache_maint_trap, 403 }, 404 #endif 405 #ifdef CONFIG_ARM64_ERRATUM_832075 406 { 407 /* Cortex-A57 r0p0 - r1p2 */ 408 .desc = "ARM erratum 832075", 409 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 410 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 411 0, 0, 412 1, 2), 413 }, 414 #endif 415 #ifdef CONFIG_ARM64_ERRATUM_834220 416 { 417 /* Cortex-A57 r0p0 - r1p2 */ 418 .desc = "ARM erratum 834220", 419 .capability = ARM64_WORKAROUND_834220, 420 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 421 0, 0, 422 1, 2), 423 }, 424 #endif 425 #ifdef CONFIG_ARM64_ERRATUM_843419 426 { 427 .desc = "ARM erratum 843419", 428 .capability = ARM64_WORKAROUND_843419, 429 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 430 .matches = cpucap_multi_entry_cap_matches, 431 .match_list = erratum_843419_list, 432 }, 433 #endif 434 #ifdef CONFIG_ARM64_ERRATUM_845719 435 { 436 .desc = "ARM erratum 845719", 437 .capability = ARM64_WORKAROUND_845719, 438 ERRATA_MIDR_RANGE_LIST(erratum_845719_list), 439 }, 440 #endif 441 #ifdef CONFIG_CAVIUM_ERRATUM_23154 442 { 443 .desc = "Cavium errata 23154 and 38545", 444 .capability = ARM64_WORKAROUND_CAVIUM_23154, 445 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 446 ERRATA_MIDR_RANGE_LIST(cavium_erratum_23154_cpus), 447 }, 448 #endif 449 #ifdef CONFIG_CAVIUM_ERRATUM_27456 450 { 451 .desc = "Cavium erratum 27456", 452 .capability = ARM64_WORKAROUND_CAVIUM_27456, 453 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus), 454 }, 455 #endif 456 #ifdef CONFIG_CAVIUM_ERRATUM_30115 457 { 458 .desc = "Cavium erratum 30115", 459 .capability = ARM64_WORKAROUND_CAVIUM_30115, 460 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus), 461 }, 462 #endif 463 { 464 .desc = "Mismatched cache type (CTR_EL0)", 465 .capability = ARM64_MISMATCHED_CACHE_TYPE, 466 .matches = has_mismatched_cache_type, 467 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 468 .cpu_enable = cpu_enable_trap_ctr_access, 469 }, 470 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 471 { 472 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003", 473 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, 474 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 475 .matches = cpucap_multi_entry_cap_matches, 476 .match_list = qcom_erratum_1003_list, 477 }, 478 #endif 479 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 480 { 481 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807", 482 .capability = ARM64_WORKAROUND_REPEAT_TLBI, 483 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 484 .matches = cpucap_multi_entry_cap_matches, 485 .match_list = arm64_repeat_tlbi_list, 486 }, 487 #endif 488 #ifdef CONFIG_ARM64_ERRATUM_858921 489 { 490 /* Cortex-A73 all versions */ 491 .desc = "ARM erratum 858921", 492 .capability = ARM64_WORKAROUND_858921, 493 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 494 }, 495 #endif 496 { 497 .desc = "Spectre-v2", 498 .capability = ARM64_SPECTRE_V2, 499 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 500 .matches = has_spectre_v2, 501 .cpu_enable = spectre_v2_enable_mitigation, 502 }, 503 #ifdef CONFIG_RANDOMIZE_BASE 504 { 505 /* Must come after the Spectre-v2 entry */ 506 .desc = "Spectre-v3a", 507 .capability = ARM64_SPECTRE_V3A, 508 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 509 .matches = has_spectre_v3a, 510 .cpu_enable = spectre_v3a_enable_mitigation, 511 }, 512 #endif 513 { 514 .desc = "Spectre-v4", 515 .capability = ARM64_SPECTRE_V4, 516 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 517 .matches = has_spectre_v4, 518 .cpu_enable = spectre_v4_enable_mitigation, 519 }, 520 { 521 .desc = "Spectre-BHB", 522 .capability = ARM64_SPECTRE_BHB, 523 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 524 .matches = is_spectre_bhb_affected, 525 .cpu_enable = spectre_bhb_enable_mitigation, 526 }, 527 #ifdef CONFIG_ARM64_ERRATUM_1418040 528 { 529 .desc = "ARM erratum 1418040", 530 .capability = ARM64_WORKAROUND_1418040, 531 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list), 532 /* 533 * We need to allow affected CPUs to come in late, but 534 * also need the non-affected CPUs to be able to come 535 * in at any point in time. Wonderful. 536 */ 537 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 538 }, 539 #endif 540 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 541 { 542 .desc = "ARM errata 1165522, 1319367, or 1530923", 543 .capability = ARM64_WORKAROUND_SPECULATIVE_AT, 544 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list), 545 }, 546 #endif 547 #ifdef CONFIG_ARM64_ERRATUM_1463225 548 { 549 .desc = "ARM erratum 1463225", 550 .capability = ARM64_WORKAROUND_1463225, 551 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 552 .matches = has_cortex_a76_erratum_1463225, 553 .midr_range_list = erratum_1463225, 554 }, 555 #endif 556 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219 557 { 558 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)", 559 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM, 560 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 561 .matches = needs_tx2_tvm_workaround, 562 }, 563 { 564 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)", 565 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM, 566 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 567 }, 568 #endif 569 #ifdef CONFIG_ARM64_ERRATUM_1542419 570 { 571 /* we depend on the firmware portion for correctness */ 572 .desc = "ARM erratum 1542419 (kernel portion)", 573 .capability = ARM64_WORKAROUND_1542419, 574 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 575 .matches = has_neoverse_n1_erratum_1542419, 576 .cpu_enable = cpu_enable_trap_ctr_access, 577 }, 578 #endif 579 #ifdef CONFIG_ARM64_ERRATUM_1508412 580 { 581 /* we depend on the firmware portion for correctness */ 582 .desc = "ARM erratum 1508412 (kernel portion)", 583 .capability = ARM64_WORKAROUND_1508412, 584 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77, 585 0, 0, 586 1, 0), 587 }, 588 #endif 589 #ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM 590 { 591 /* NVIDIA Carmel */ 592 .desc = "NVIDIA Carmel CNP erratum", 593 .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP, 594 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 595 }, 596 #endif 597 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 598 { 599 /* 600 * The erratum work around is handled within the TRBE 601 * driver and can be applied per-cpu. So, we can allow 602 * a late CPU to come online with this erratum. 603 */ 604 .desc = "ARM erratum 2119858 or 2139208", 605 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, 606 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 607 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), 608 }, 609 #endif 610 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 611 { 612 .desc = "ARM erratum 2067961 or 2054223", 613 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, 614 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus), 615 }, 616 #endif 617 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 618 { 619 .desc = "ARM erratum 2253138 or 2224489", 620 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, 621 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 622 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), 623 }, 624 #endif 625 #ifdef CONFIG_ARM64_ERRATUM_2077057 626 { 627 .desc = "ARM erratum 2077057", 628 .capability = ARM64_WORKAROUND_2077057, 629 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 630 }, 631 #endif 632 #ifdef CONFIG_ARM64_ERRATUM_2064142 633 { 634 .desc = "ARM erratum 2064142", 635 .capability = ARM64_WORKAROUND_2064142, 636 637 /* Cortex-A510 r0p0 - r0p2 */ 638 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 639 }, 640 #endif 641 #ifdef CONFIG_ARM64_ERRATUM_2038923 642 { 643 .desc = "ARM erratum 2038923", 644 .capability = ARM64_WORKAROUND_2038923, 645 646 /* Cortex-A510 r0p0 - r0p2 */ 647 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 648 }, 649 #endif 650 #ifdef CONFIG_ARM64_ERRATUM_1902691 651 { 652 .desc = "ARM erratum 1902691", 653 .capability = ARM64_WORKAROUND_1902691, 654 655 /* Cortex-A510 r0p0 - r0p1 */ 656 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1) 657 }, 658 #endif 659 { 660 } 661 }; 662