1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ARM64 cacheinfo support 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * All Rights Reserved 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/cacheinfo.h> 11 #include <linux/of.h> 12 13 #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ 14 15 int cache_line_size(void) 16 { 17 if (coherency_max_size != 0) 18 return coherency_max_size; 19 20 return cache_line_size_of_cpu(); 21 } 22 EXPORT_SYMBOL_GPL(cache_line_size); 23 24 static inline enum cache_type get_cache_type(int level) 25 { 26 u64 clidr; 27 28 if (level > MAX_CACHE_LEVEL) 29 return CACHE_TYPE_NOCACHE; 30 clidr = read_sysreg(clidr_el1); 31 return CLIDR_CTYPE(clidr, level); 32 } 33 34 static void ci_leaf_init(struct cacheinfo *this_leaf, 35 enum cache_type type, unsigned int level) 36 { 37 this_leaf->level = level; 38 this_leaf->type = type; 39 } 40 41 int init_cache_level(unsigned int cpu) 42 { 43 unsigned int ctype, level, leaves; 44 int fw_level, ret; 45 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); 46 47 for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { 48 ctype = get_cache_type(level); 49 if (ctype == CACHE_TYPE_NOCACHE) { 50 level--; 51 break; 52 } 53 /* Separate instruction and data caches */ 54 leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1; 55 } 56 57 if (acpi_disabled) { 58 fw_level = of_find_last_cache_level(cpu); 59 } else { 60 ret = acpi_get_cache_info(cpu, &fw_level, NULL); 61 if (ret < 0) 62 fw_level = 0; 63 } 64 65 if (level < fw_level) { 66 /* 67 * some external caches not specified in CLIDR_EL1 68 * the information may be available in the device tree 69 * only unified external caches are considered here 70 */ 71 leaves += (fw_level - level); 72 level = fw_level; 73 } 74 75 this_cpu_ci->num_levels = level; 76 this_cpu_ci->num_leaves = leaves; 77 return 0; 78 } 79 80 int populate_cache_leaves(unsigned int cpu) 81 { 82 unsigned int level, idx; 83 enum cache_type type; 84 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); 85 struct cacheinfo *this_leaf = this_cpu_ci->info_list; 86 87 for (idx = 0, level = 1; level <= this_cpu_ci->num_levels && 88 idx < this_cpu_ci->num_leaves; idx++, level++) { 89 type = get_cache_type(level); 90 if (type == CACHE_TYPE_SEPARATE) { 91 ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); 92 ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); 93 } else { 94 ci_leaf_init(this_leaf++, type, level); 95 } 96 } 97 return 0; 98 } 99