1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  Copyright (C) 2014 ARM Limited
4  */
5 
6 #include <linux/cpu.h>
7 #include <linux/init.h>
8 #include <linux/list.h>
9 #include <linux/perf_event.h>
10 #include <linux/sched.h>
11 #include <linux/slab.h>
12 #include <linux/sysctl.h>
13 #include <linux/uaccess.h>
14 
15 #include <asm/cpufeature.h>
16 #include <asm/insn.h>
17 #include <asm/sysreg.h>
18 #include <asm/system_misc.h>
19 #include <asm/traps.h>
20 #include <asm/kprobes.h>
21 
22 #define CREATE_TRACE_POINTS
23 #include "trace-events-emulation.h"
24 
25 /*
26  * The runtime support for deprecated instruction support can be in one of
27  * following three states -
28  *
29  * 0 = undef
30  * 1 = emulate (software emulation)
31  * 2 = hw (supported in hardware)
32  */
33 enum insn_emulation_mode {
34 	INSN_UNDEF,
35 	INSN_EMULATE,
36 	INSN_HW,
37 };
38 
39 enum legacy_insn_status {
40 	INSN_DEPRECATED,
41 	INSN_OBSOLETE,
42 };
43 
44 struct insn_emulation_ops {
45 	const char		*name;
46 	enum legacy_insn_status	status;
47 	struct undef_hook	*hooks;
48 	int			(*set_hw_mode)(bool enable);
49 };
50 
51 struct insn_emulation {
52 	struct list_head node;
53 	struct insn_emulation_ops *ops;
54 	int current_mode;
55 	int min;
56 	int max;
57 };
58 
59 static LIST_HEAD(insn_emulation);
60 static int nr_insn_emulated __initdata;
61 static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
62 static DEFINE_MUTEX(insn_emulation_mutex);
63 
64 static void register_emulation_hooks(struct insn_emulation_ops *ops)
65 {
66 	struct undef_hook *hook;
67 
68 	BUG_ON(!ops->hooks);
69 
70 	for (hook = ops->hooks; hook->instr_mask; hook++)
71 		register_undef_hook(hook);
72 
73 	pr_notice("Registered %s emulation handler\n", ops->name);
74 }
75 
76 static void remove_emulation_hooks(struct insn_emulation_ops *ops)
77 {
78 	struct undef_hook *hook;
79 
80 	BUG_ON(!ops->hooks);
81 
82 	for (hook = ops->hooks; hook->instr_mask; hook++)
83 		unregister_undef_hook(hook);
84 
85 	pr_notice("Removed %s emulation handler\n", ops->name);
86 }
87 
88 static void enable_insn_hw_mode(void *data)
89 {
90 	struct insn_emulation *insn = (struct insn_emulation *)data;
91 	if (insn->ops->set_hw_mode)
92 		insn->ops->set_hw_mode(true);
93 }
94 
95 static void disable_insn_hw_mode(void *data)
96 {
97 	struct insn_emulation *insn = (struct insn_emulation *)data;
98 	if (insn->ops->set_hw_mode)
99 		insn->ops->set_hw_mode(false);
100 }
101 
102 /* Run set_hw_mode(mode) on all active CPUs */
103 static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
104 {
105 	if (!insn->ops->set_hw_mode)
106 		return -EINVAL;
107 	if (enable)
108 		on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
109 	else
110 		on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
111 	return 0;
112 }
113 
114 /*
115  * Run set_hw_mode for all insns on a starting CPU.
116  * Returns:
117  *  0 		- If all the hooks ran successfully.
118  * -EINVAL	- At least one hook is not supported by the CPU.
119  */
120 static int run_all_insn_set_hw_mode(unsigned int cpu)
121 {
122 	int rc = 0;
123 	unsigned long flags;
124 	struct insn_emulation *insn;
125 
126 	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
127 	list_for_each_entry(insn, &insn_emulation, node) {
128 		bool enable = (insn->current_mode == INSN_HW);
129 		if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
130 			pr_warn("CPU[%u] cannot support the emulation of %s",
131 				cpu, insn->ops->name);
132 			rc = -EINVAL;
133 		}
134 	}
135 	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
136 	return rc;
137 }
138 
139 static int update_insn_emulation_mode(struct insn_emulation *insn,
140 				       enum insn_emulation_mode prev)
141 {
142 	int ret = 0;
143 
144 	switch (prev) {
145 	case INSN_UNDEF: /* Nothing to be done */
146 		break;
147 	case INSN_EMULATE:
148 		remove_emulation_hooks(insn->ops);
149 		break;
150 	case INSN_HW:
151 		if (!run_all_cpu_set_hw_mode(insn, false))
152 			pr_notice("Disabled %s support\n", insn->ops->name);
153 		break;
154 	}
155 
156 	switch (insn->current_mode) {
157 	case INSN_UNDEF:
158 		break;
159 	case INSN_EMULATE:
160 		register_emulation_hooks(insn->ops);
161 		break;
162 	case INSN_HW:
163 		ret = run_all_cpu_set_hw_mode(insn, true);
164 		if (!ret)
165 			pr_notice("Enabled %s support\n", insn->ops->name);
166 		break;
167 	}
168 
169 	return ret;
170 }
171 
172 static void __init register_insn_emulation(struct insn_emulation_ops *ops)
173 {
174 	unsigned long flags;
175 	struct insn_emulation *insn;
176 
177 	insn = kzalloc(sizeof(*insn), GFP_KERNEL);
178 	if (!insn)
179 		return;
180 
181 	insn->ops = ops;
182 	insn->min = INSN_UNDEF;
183 
184 	switch (ops->status) {
185 	case INSN_DEPRECATED:
186 		insn->current_mode = INSN_EMULATE;
187 		/* Disable the HW mode if it was turned on at early boot time */
188 		run_all_cpu_set_hw_mode(insn, false);
189 		insn->max = INSN_HW;
190 		break;
191 	case INSN_OBSOLETE:
192 		insn->current_mode = INSN_UNDEF;
193 		insn->max = INSN_EMULATE;
194 		break;
195 	}
196 
197 	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
198 	list_add(&insn->node, &insn_emulation);
199 	nr_insn_emulated++;
200 	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
201 
202 	/* Register any handlers if required */
203 	update_insn_emulation_mode(insn, INSN_UNDEF);
204 }
205 
206 static int emulation_proc_handler(struct ctl_table *table, int write,
207 				  void *buffer, size_t *lenp,
208 				  loff_t *ppos)
209 {
210 	int ret = 0;
211 	struct insn_emulation *insn = container_of(table->data, struct insn_emulation, current_mode);
212 	enum insn_emulation_mode prev_mode = insn->current_mode;
213 
214 	mutex_lock(&insn_emulation_mutex);
215 	ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
216 
217 	if (ret || !write || prev_mode == insn->current_mode)
218 		goto ret;
219 
220 	ret = update_insn_emulation_mode(insn, prev_mode);
221 	if (ret) {
222 		/* Mode change failed, revert to previous mode. */
223 		insn->current_mode = prev_mode;
224 		update_insn_emulation_mode(insn, INSN_UNDEF);
225 	}
226 ret:
227 	mutex_unlock(&insn_emulation_mutex);
228 	return ret;
229 }
230 
231 static void __init register_insn_emulation_sysctl(void)
232 {
233 	unsigned long flags;
234 	int i = 0;
235 	struct insn_emulation *insn;
236 	struct ctl_table *insns_sysctl, *sysctl;
237 
238 	insns_sysctl = kcalloc(nr_insn_emulated + 1, sizeof(*sysctl),
239 			       GFP_KERNEL);
240 	if (!insns_sysctl)
241 		return;
242 
243 	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
244 	list_for_each_entry(insn, &insn_emulation, node) {
245 		sysctl = &insns_sysctl[i];
246 
247 		sysctl->mode = 0644;
248 		sysctl->maxlen = sizeof(int);
249 
250 		sysctl->procname = insn->ops->name;
251 		sysctl->data = &insn->current_mode;
252 		sysctl->extra1 = &insn->min;
253 		sysctl->extra2 = &insn->max;
254 		sysctl->proc_handler = emulation_proc_handler;
255 		i++;
256 	}
257 	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
258 
259 	register_sysctl("abi", insns_sysctl);
260 }
261 
262 /*
263  *  Implement emulation of the SWP/SWPB instructions using load-exclusive and
264  *  store-exclusive.
265  *
266  *  Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
267  *  Where: Rt  = destination
268  *	   Rt2 = source
269  *	   Rn  = address
270  */
271 
272 /*
273  * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
274  */
275 
276 /* Arbitrary constant to ensure forward-progress of the LL/SC loop */
277 #define __SWP_LL_SC_LOOPS	4
278 
279 #define __user_swpX_asm(data, addr, res, temp, temp2, B)	\
280 do {								\
281 	uaccess_enable_privileged();				\
282 	__asm__ __volatile__(					\
283 	"	mov		%w3, %w6\n"			\
284 	"0:	ldxr"B"		%w2, [%4]\n"			\
285 	"1:	stxr"B"		%w0, %w1, [%4]\n"		\
286 	"	cbz		%w0, 2f\n"			\
287 	"	sub		%w3, %w3, #1\n"			\
288 	"	cbnz		%w3, 0b\n"			\
289 	"	mov		%w0, %w5\n"			\
290 	"	b		3f\n"				\
291 	"2:\n"							\
292 	"	mov		%w1, %w2\n"			\
293 	"3:\n"							\
294 	_ASM_EXTABLE_UACCESS_ERR(0b, 3b, %w0)			\
295 	_ASM_EXTABLE_UACCESS_ERR(1b, 3b, %w0)			\
296 	: "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2)	\
297 	: "r" ((unsigned long)addr), "i" (-EAGAIN),		\
298 	  "i" (__SWP_LL_SC_LOOPS)				\
299 	: "memory");						\
300 	uaccess_disable_privileged();				\
301 } while (0)
302 
303 #define __user_swp_asm(data, addr, res, temp, temp2) \
304 	__user_swpX_asm(data, addr, res, temp, temp2, "")
305 #define __user_swpb_asm(data, addr, res, temp, temp2) \
306 	__user_swpX_asm(data, addr, res, temp, temp2, "b")
307 
308 /*
309  * Bit 22 of the instruction encoding distinguishes between
310  * the SWP and SWPB variants (bit set means SWPB).
311  */
312 #define TYPE_SWPB (1 << 22)
313 
314 static int emulate_swpX(unsigned int address, unsigned int *data,
315 			unsigned int type)
316 {
317 	unsigned int res = 0;
318 
319 	if ((type != TYPE_SWPB) && (address & 0x3)) {
320 		/* SWP to unaligned address not permitted */
321 		pr_debug("SWP instruction on unaligned pointer!\n");
322 		return -EFAULT;
323 	}
324 
325 	while (1) {
326 		unsigned long temp, temp2;
327 
328 		if (type == TYPE_SWPB)
329 			__user_swpb_asm(*data, address, res, temp, temp2);
330 		else
331 			__user_swp_asm(*data, address, res, temp, temp2);
332 
333 		if (likely(res != -EAGAIN) || signal_pending(current))
334 			break;
335 
336 		cond_resched();
337 	}
338 
339 	return res;
340 }
341 
342 #define ARM_OPCODE_CONDTEST_FAIL   0
343 #define ARM_OPCODE_CONDTEST_PASS   1
344 #define ARM_OPCODE_CONDTEST_UNCOND 2
345 
346 #define	ARM_OPCODE_CONDITION_UNCOND	0xf
347 
348 static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
349 {
350 	u32 cc_bits  = opcode >> 28;
351 
352 	if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
353 		if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
354 			return ARM_OPCODE_CONDTEST_PASS;
355 		else
356 			return ARM_OPCODE_CONDTEST_FAIL;
357 	}
358 	return ARM_OPCODE_CONDTEST_UNCOND;
359 }
360 
361 /*
362  * swp_handler logs the id of calling process, dissects the instruction, sanity
363  * checks the memory location, calls emulate_swpX for the actual operation and
364  * deals with fixup/error handling before returning
365  */
366 static int swp_handler(struct pt_regs *regs, u32 instr)
367 {
368 	u32 destreg, data, type, address = 0;
369 	const void __user *user_ptr;
370 	int rn, rt2, res = 0;
371 
372 	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
373 
374 	type = instr & TYPE_SWPB;
375 
376 	switch (aarch32_check_condition(instr, regs->pstate)) {
377 	case ARM_OPCODE_CONDTEST_PASS:
378 		break;
379 	case ARM_OPCODE_CONDTEST_FAIL:
380 		/* Condition failed - return to next instruction */
381 		goto ret;
382 	case ARM_OPCODE_CONDTEST_UNCOND:
383 		/* If unconditional encoding - not a SWP, undef */
384 		return -EFAULT;
385 	default:
386 		return -EINVAL;
387 	}
388 
389 	rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
390 	rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
391 
392 	address = (u32)regs->user_regs.regs[rn];
393 	data	= (u32)regs->user_regs.regs[rt2];
394 	destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
395 
396 	pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
397 		rn, address, destreg,
398 		aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
399 
400 	/* Check access in reasonable access range for both SWP and SWPB */
401 	user_ptr = (const void __user *)(unsigned long)(address & ~3);
402 	if (!access_ok(user_ptr, 4)) {
403 		pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
404 			address);
405 		goto fault;
406 	}
407 
408 	res = emulate_swpX(address, &data, type);
409 	if (res == -EFAULT)
410 		goto fault;
411 	else if (res == 0)
412 		regs->user_regs.regs[destreg] = data;
413 
414 ret:
415 	if (type == TYPE_SWPB)
416 		trace_instruction_emulation("swpb", regs->pc);
417 	else
418 		trace_instruction_emulation("swp", regs->pc);
419 
420 	pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
421 			current->comm, (unsigned long)current->pid, regs->pc);
422 
423 	arm64_skip_faulting_instruction(regs, 4);
424 	return 0;
425 
426 fault:
427 	pr_debug("SWP{B} emulation: access caused memory abort!\n");
428 	arm64_notify_segfault(address);
429 
430 	return 0;
431 }
432 
433 /*
434  * Only emulate SWP/SWPB executed in ARM state/User mode.
435  * The kernel must be SWP free and SWP{B} does not exist in Thumb.
436  */
437 static struct undef_hook swp_hooks[] = {
438 	{
439 		.instr_mask	= 0x0fb00ff0,
440 		.instr_val	= 0x01000090,
441 		.pstate_mask	= PSR_AA32_MODE_MASK,
442 		.pstate_val	= PSR_AA32_MODE_USR,
443 		.fn		= swp_handler
444 	},
445 	{ }
446 };
447 
448 static struct insn_emulation_ops swp_ops = {
449 	.name = "swp",
450 	.status = INSN_OBSOLETE,
451 	.hooks = swp_hooks,
452 	.set_hw_mode = NULL,
453 };
454 
455 static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
456 {
457 	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
458 
459 	switch (aarch32_check_condition(instr, regs->pstate)) {
460 	case ARM_OPCODE_CONDTEST_PASS:
461 		break;
462 	case ARM_OPCODE_CONDTEST_FAIL:
463 		/* Condition failed - return to next instruction */
464 		goto ret;
465 	case ARM_OPCODE_CONDTEST_UNCOND:
466 		/* If unconditional encoding - not a barrier instruction */
467 		return -EFAULT;
468 	default:
469 		return -EINVAL;
470 	}
471 
472 	switch (aarch32_insn_mcr_extract_crm(instr)) {
473 	case 10:
474 		/*
475 		 * dmb - mcr p15, 0, Rt, c7, c10, 5
476 		 * dsb - mcr p15, 0, Rt, c7, c10, 4
477 		 */
478 		if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
479 			dmb(sy);
480 			trace_instruction_emulation(
481 				"mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
482 		} else {
483 			dsb(sy);
484 			trace_instruction_emulation(
485 				"mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
486 		}
487 		break;
488 	case 5:
489 		/*
490 		 * isb - mcr p15, 0, Rt, c7, c5, 4
491 		 *
492 		 * Taking an exception or returning from one acts as an
493 		 * instruction barrier. So no explicit barrier needed here.
494 		 */
495 		trace_instruction_emulation(
496 			"mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
497 		break;
498 	}
499 
500 ret:
501 	pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
502 			current->comm, (unsigned long)current->pid, regs->pc);
503 
504 	arm64_skip_faulting_instruction(regs, 4);
505 	return 0;
506 }
507 
508 static int cp15_barrier_set_hw_mode(bool enable)
509 {
510 	if (enable)
511 		sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_CP15BEN);
512 	else
513 		sysreg_clear_set(sctlr_el1, SCTLR_EL1_CP15BEN, 0);
514 	return 0;
515 }
516 
517 static struct undef_hook cp15_barrier_hooks[] = {
518 	{
519 		.instr_mask	= 0x0fff0fdf,
520 		.instr_val	= 0x0e070f9a,
521 		.pstate_mask	= PSR_AA32_MODE_MASK,
522 		.pstate_val	= PSR_AA32_MODE_USR,
523 		.fn		= cp15barrier_handler,
524 	},
525 	{
526 		.instr_mask	= 0x0fff0fff,
527 		.instr_val	= 0x0e070f95,
528 		.pstate_mask	= PSR_AA32_MODE_MASK,
529 		.pstate_val	= PSR_AA32_MODE_USR,
530 		.fn		= cp15barrier_handler,
531 	},
532 	{ }
533 };
534 
535 static struct insn_emulation_ops cp15_barrier_ops = {
536 	.name = "cp15_barrier",
537 	.status = INSN_DEPRECATED,
538 	.hooks = cp15_barrier_hooks,
539 	.set_hw_mode = cp15_barrier_set_hw_mode,
540 };
541 
542 static int setend_set_hw_mode(bool enable)
543 {
544 	if (!cpu_supports_mixed_endian_el0())
545 		return -EINVAL;
546 
547 	if (enable)
548 		sysreg_clear_set(sctlr_el1, SCTLR_EL1_SED, 0);
549 	else
550 		sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_SED);
551 	return 0;
552 }
553 
554 static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
555 {
556 	char *insn;
557 
558 	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
559 
560 	if (big_endian) {
561 		insn = "setend be";
562 		regs->pstate |= PSR_AA32_E_BIT;
563 	} else {
564 		insn = "setend le";
565 		regs->pstate &= ~PSR_AA32_E_BIT;
566 	}
567 
568 	trace_instruction_emulation(insn, regs->pc);
569 	pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
570 			current->comm, (unsigned long)current->pid, regs->pc);
571 
572 	return 0;
573 }
574 
575 static int a32_setend_handler(struct pt_regs *regs, u32 instr)
576 {
577 	int rc = compat_setend_handler(regs, (instr >> 9) & 1);
578 	arm64_skip_faulting_instruction(regs, 4);
579 	return rc;
580 }
581 
582 static int t16_setend_handler(struct pt_regs *regs, u32 instr)
583 {
584 	int rc = compat_setend_handler(regs, (instr >> 3) & 1);
585 	arm64_skip_faulting_instruction(regs, 2);
586 	return rc;
587 }
588 
589 static struct undef_hook setend_hooks[] = {
590 	{
591 		.instr_mask	= 0xfffffdff,
592 		.instr_val	= 0xf1010000,
593 		.pstate_mask	= PSR_AA32_MODE_MASK,
594 		.pstate_val	= PSR_AA32_MODE_USR,
595 		.fn		= a32_setend_handler,
596 	},
597 	{
598 		/* Thumb mode */
599 		.instr_mask	= 0xfffffff7,
600 		.instr_val	= 0x0000b650,
601 		.pstate_mask	= (PSR_AA32_T_BIT | PSR_AA32_MODE_MASK),
602 		.pstate_val	= (PSR_AA32_T_BIT | PSR_AA32_MODE_USR),
603 		.fn		= t16_setend_handler,
604 	},
605 	{}
606 };
607 
608 static struct insn_emulation_ops setend_ops = {
609 	.name = "setend",
610 	.status = INSN_DEPRECATED,
611 	.hooks = setend_hooks,
612 	.set_hw_mode = setend_set_hw_mode,
613 };
614 
615 /*
616  * Invoked as core_initcall, which guarantees that the instruction
617  * emulation is ready for userspace.
618  */
619 static int __init armv8_deprecated_init(void)
620 {
621 	if (IS_ENABLED(CONFIG_SWP_EMULATION))
622 		register_insn_emulation(&swp_ops);
623 
624 	if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
625 		register_insn_emulation(&cp15_barrier_ops);
626 
627 	if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
628 		if (system_supports_mixed_endian_el0())
629 			register_insn_emulation(&setend_ops);
630 		else
631 			pr_info("setend instruction emulation is not supported on this system\n");
632 	}
633 
634 	cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
635 				  "arm64/isndep:starting",
636 				  run_all_insn_set_hw_mode, NULL);
637 	register_insn_emulation_sysctl();
638 
639 	return 0;
640 }
641 
642 core_initcall(armv8_deprecated_init);
643