1 /* 2 * Copyright (C) 2014 ARM Limited 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/cpu.h> 10 #include <linux/init.h> 11 #include <linux/list.h> 12 #include <linux/perf_event.h> 13 #include <linux/sched.h> 14 #include <linux/slab.h> 15 #include <linux/sysctl.h> 16 17 #include <asm/alternative.h> 18 #include <asm/cpufeature.h> 19 #include <asm/insn.h> 20 #include <asm/opcodes.h> 21 #include <asm/sysreg.h> 22 #include <asm/system_misc.h> 23 #include <asm/traps.h> 24 #include <asm/uaccess.h> 25 #include <asm/cpufeature.h> 26 27 #define CREATE_TRACE_POINTS 28 #include "trace-events-emulation.h" 29 30 /* 31 * The runtime support for deprecated instruction support can be in one of 32 * following three states - 33 * 34 * 0 = undef 35 * 1 = emulate (software emulation) 36 * 2 = hw (supported in hardware) 37 */ 38 enum insn_emulation_mode { 39 INSN_UNDEF, 40 INSN_EMULATE, 41 INSN_HW, 42 }; 43 44 enum legacy_insn_status { 45 INSN_DEPRECATED, 46 INSN_OBSOLETE, 47 }; 48 49 struct insn_emulation_ops { 50 const char *name; 51 enum legacy_insn_status status; 52 struct undef_hook *hooks; 53 int (*set_hw_mode)(bool enable); 54 }; 55 56 struct insn_emulation { 57 struct list_head node; 58 struct insn_emulation_ops *ops; 59 int current_mode; 60 int min; 61 int max; 62 }; 63 64 static LIST_HEAD(insn_emulation); 65 static int nr_insn_emulated __initdata; 66 static DEFINE_RAW_SPINLOCK(insn_emulation_lock); 67 68 static void register_emulation_hooks(struct insn_emulation_ops *ops) 69 { 70 struct undef_hook *hook; 71 72 BUG_ON(!ops->hooks); 73 74 for (hook = ops->hooks; hook->instr_mask; hook++) 75 register_undef_hook(hook); 76 77 pr_notice("Registered %s emulation handler\n", ops->name); 78 } 79 80 static void remove_emulation_hooks(struct insn_emulation_ops *ops) 81 { 82 struct undef_hook *hook; 83 84 BUG_ON(!ops->hooks); 85 86 for (hook = ops->hooks; hook->instr_mask; hook++) 87 unregister_undef_hook(hook); 88 89 pr_notice("Removed %s emulation handler\n", ops->name); 90 } 91 92 static void enable_insn_hw_mode(void *data) 93 { 94 struct insn_emulation *insn = (struct insn_emulation *)data; 95 if (insn->ops->set_hw_mode) 96 insn->ops->set_hw_mode(true); 97 } 98 99 static void disable_insn_hw_mode(void *data) 100 { 101 struct insn_emulation *insn = (struct insn_emulation *)data; 102 if (insn->ops->set_hw_mode) 103 insn->ops->set_hw_mode(false); 104 } 105 106 /* Run set_hw_mode(mode) on all active CPUs */ 107 static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable) 108 { 109 if (!insn->ops->set_hw_mode) 110 return -EINVAL; 111 if (enable) 112 on_each_cpu(enable_insn_hw_mode, (void *)insn, true); 113 else 114 on_each_cpu(disable_insn_hw_mode, (void *)insn, true); 115 return 0; 116 } 117 118 /* 119 * Run set_hw_mode for all insns on a starting CPU. 120 * Returns: 121 * 0 - If all the hooks ran successfully. 122 * -EINVAL - At least one hook is not supported by the CPU. 123 */ 124 static int run_all_insn_set_hw_mode(unsigned int cpu) 125 { 126 int rc = 0; 127 unsigned long flags; 128 struct insn_emulation *insn; 129 130 raw_spin_lock_irqsave(&insn_emulation_lock, flags); 131 list_for_each_entry(insn, &insn_emulation, node) { 132 bool enable = (insn->current_mode == INSN_HW); 133 if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) { 134 pr_warn("CPU[%u] cannot support the emulation of %s", 135 cpu, insn->ops->name); 136 rc = -EINVAL; 137 } 138 } 139 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags); 140 return rc; 141 } 142 143 static int update_insn_emulation_mode(struct insn_emulation *insn, 144 enum insn_emulation_mode prev) 145 { 146 int ret = 0; 147 148 switch (prev) { 149 case INSN_UNDEF: /* Nothing to be done */ 150 break; 151 case INSN_EMULATE: 152 remove_emulation_hooks(insn->ops); 153 break; 154 case INSN_HW: 155 if (!run_all_cpu_set_hw_mode(insn, false)) 156 pr_notice("Disabled %s support\n", insn->ops->name); 157 break; 158 } 159 160 switch (insn->current_mode) { 161 case INSN_UNDEF: 162 break; 163 case INSN_EMULATE: 164 register_emulation_hooks(insn->ops); 165 break; 166 case INSN_HW: 167 ret = run_all_cpu_set_hw_mode(insn, true); 168 if (!ret) 169 pr_notice("Enabled %s support\n", insn->ops->name); 170 break; 171 } 172 173 return ret; 174 } 175 176 static void __init register_insn_emulation(struct insn_emulation_ops *ops) 177 { 178 unsigned long flags; 179 struct insn_emulation *insn; 180 181 insn = kzalloc(sizeof(*insn), GFP_KERNEL); 182 insn->ops = ops; 183 insn->min = INSN_UNDEF; 184 185 switch (ops->status) { 186 case INSN_DEPRECATED: 187 insn->current_mode = INSN_EMULATE; 188 /* Disable the HW mode if it was turned on at early boot time */ 189 run_all_cpu_set_hw_mode(insn, false); 190 insn->max = INSN_HW; 191 break; 192 case INSN_OBSOLETE: 193 insn->current_mode = INSN_UNDEF; 194 insn->max = INSN_EMULATE; 195 break; 196 } 197 198 raw_spin_lock_irqsave(&insn_emulation_lock, flags); 199 list_add(&insn->node, &insn_emulation); 200 nr_insn_emulated++; 201 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags); 202 203 /* Register any handlers if required */ 204 update_insn_emulation_mode(insn, INSN_UNDEF); 205 } 206 207 static int emulation_proc_handler(struct ctl_table *table, int write, 208 void __user *buffer, size_t *lenp, 209 loff_t *ppos) 210 { 211 int ret = 0; 212 struct insn_emulation *insn = (struct insn_emulation *) table->data; 213 enum insn_emulation_mode prev_mode = insn->current_mode; 214 215 table->data = &insn->current_mode; 216 ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); 217 218 if (ret || !write || prev_mode == insn->current_mode) 219 goto ret; 220 221 ret = update_insn_emulation_mode(insn, prev_mode); 222 if (ret) { 223 /* Mode change failed, revert to previous mode. */ 224 insn->current_mode = prev_mode; 225 update_insn_emulation_mode(insn, INSN_UNDEF); 226 } 227 ret: 228 table->data = insn; 229 return ret; 230 } 231 232 static struct ctl_table ctl_abi[] = { 233 { 234 .procname = "abi", 235 .mode = 0555, 236 }, 237 { } 238 }; 239 240 static void __init register_insn_emulation_sysctl(struct ctl_table *table) 241 { 242 unsigned long flags; 243 int i = 0; 244 struct insn_emulation *insn; 245 struct ctl_table *insns_sysctl, *sysctl; 246 247 insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1), 248 GFP_KERNEL); 249 250 raw_spin_lock_irqsave(&insn_emulation_lock, flags); 251 list_for_each_entry(insn, &insn_emulation, node) { 252 sysctl = &insns_sysctl[i]; 253 254 sysctl->mode = 0644; 255 sysctl->maxlen = sizeof(int); 256 257 sysctl->procname = insn->ops->name; 258 sysctl->data = insn; 259 sysctl->extra1 = &insn->min; 260 sysctl->extra2 = &insn->max; 261 sysctl->proc_handler = emulation_proc_handler; 262 i++; 263 } 264 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags); 265 266 table->child = insns_sysctl; 267 register_sysctl_table(table); 268 } 269 270 /* 271 * Implement emulation of the SWP/SWPB instructions using load-exclusive and 272 * store-exclusive. 273 * 274 * Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>] 275 * Where: Rt = destination 276 * Rt2 = source 277 * Rn = address 278 */ 279 280 /* 281 * Error-checking SWP macros implemented using ldxr{b}/stxr{b} 282 */ 283 284 /* Arbitrary constant to ensure forward-progress of the LL/SC loop */ 285 #define __SWP_LL_SC_LOOPS 4 286 287 #define __user_swpX_asm(data, addr, res, temp, temp2, B) \ 288 __asm__ __volatile__( \ 289 " mov %w3, %w7\n" \ 290 ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \ 291 CONFIG_ARM64_PAN) \ 292 "0: ldxr"B" %w2, [%4]\n" \ 293 "1: stxr"B" %w0, %w1, [%4]\n" \ 294 " cbz %w0, 2f\n" \ 295 " sub %w3, %w3, #1\n" \ 296 " cbnz %w3, 0b\n" \ 297 " mov %w0, %w5\n" \ 298 " b 3f\n" \ 299 "2:\n" \ 300 " mov %w1, %w2\n" \ 301 "3:\n" \ 302 " .pushsection .fixup,\"ax\"\n" \ 303 " .align 2\n" \ 304 "4: mov %w0, %w6\n" \ 305 " b 3b\n" \ 306 " .popsection" \ 307 _ASM_EXTABLE(0b, 4b) \ 308 _ASM_EXTABLE(1b, 4b) \ 309 ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \ 310 CONFIG_ARM64_PAN) \ 311 : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \ 312 : "r" (addr), "i" (-EAGAIN), "i" (-EFAULT), \ 313 "i" (__SWP_LL_SC_LOOPS) \ 314 : "memory") 315 316 #define __user_swp_asm(data, addr, res, temp, temp2) \ 317 __user_swpX_asm(data, addr, res, temp, temp2, "") 318 #define __user_swpb_asm(data, addr, res, temp, temp2) \ 319 __user_swpX_asm(data, addr, res, temp, temp2, "b") 320 321 /* 322 * Bit 22 of the instruction encoding distinguishes between 323 * the SWP and SWPB variants (bit set means SWPB). 324 */ 325 #define TYPE_SWPB (1 << 22) 326 327 static int emulate_swpX(unsigned int address, unsigned int *data, 328 unsigned int type) 329 { 330 unsigned int res = 0; 331 332 if ((type != TYPE_SWPB) && (address & 0x3)) { 333 /* SWP to unaligned address not permitted */ 334 pr_debug("SWP instruction on unaligned pointer!\n"); 335 return -EFAULT; 336 } 337 338 while (1) { 339 unsigned long temp, temp2; 340 341 if (type == TYPE_SWPB) 342 __user_swpb_asm(*data, address, res, temp, temp2); 343 else 344 __user_swp_asm(*data, address, res, temp, temp2); 345 346 if (likely(res != -EAGAIN) || signal_pending(current)) 347 break; 348 349 cond_resched(); 350 } 351 352 return res; 353 } 354 355 #define ARM_OPCODE_CONDITION_UNCOND 0xf 356 357 static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr) 358 { 359 u32 cc_bits = opcode >> 28; 360 361 if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) { 362 if ((*aarch32_opcode_cond_checks[cc_bits])(psr)) 363 return ARM_OPCODE_CONDTEST_PASS; 364 else 365 return ARM_OPCODE_CONDTEST_FAIL; 366 } 367 return ARM_OPCODE_CONDTEST_UNCOND; 368 } 369 370 /* 371 * swp_handler logs the id of calling process, dissects the instruction, sanity 372 * checks the memory location, calls emulate_swpX for the actual operation and 373 * deals with fixup/error handling before returning 374 */ 375 static int swp_handler(struct pt_regs *regs, u32 instr) 376 { 377 u32 destreg, data, type, address = 0; 378 int rn, rt2, res = 0; 379 380 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc); 381 382 type = instr & TYPE_SWPB; 383 384 switch (aarch32_check_condition(instr, regs->pstate)) { 385 case ARM_OPCODE_CONDTEST_PASS: 386 break; 387 case ARM_OPCODE_CONDTEST_FAIL: 388 /* Condition failed - return to next instruction */ 389 goto ret; 390 case ARM_OPCODE_CONDTEST_UNCOND: 391 /* If unconditional encoding - not a SWP, undef */ 392 return -EFAULT; 393 default: 394 return -EINVAL; 395 } 396 397 rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET); 398 rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET); 399 400 address = (u32)regs->user_regs.regs[rn]; 401 data = (u32)regs->user_regs.regs[rt2]; 402 destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET); 403 404 pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n", 405 rn, address, destreg, 406 aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data); 407 408 /* Check access in reasonable access range for both SWP and SWPB */ 409 if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) { 410 pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n", 411 address); 412 goto fault; 413 } 414 415 res = emulate_swpX(address, &data, type); 416 if (res == -EFAULT) 417 goto fault; 418 else if (res == 0) 419 regs->user_regs.regs[destreg] = data; 420 421 ret: 422 if (type == TYPE_SWPB) 423 trace_instruction_emulation("swpb", regs->pc); 424 else 425 trace_instruction_emulation("swp", regs->pc); 426 427 pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n", 428 current->comm, (unsigned long)current->pid, regs->pc); 429 430 regs->pc += 4; 431 return 0; 432 433 fault: 434 pr_debug("SWP{B} emulation: access caused memory abort!\n"); 435 arm64_notify_segfault(regs, address); 436 437 return 0; 438 } 439 440 /* 441 * Only emulate SWP/SWPB executed in ARM state/User mode. 442 * The kernel must be SWP free and SWP{B} does not exist in Thumb. 443 */ 444 static struct undef_hook swp_hooks[] = { 445 { 446 .instr_mask = 0x0fb00ff0, 447 .instr_val = 0x01000090, 448 .pstate_mask = COMPAT_PSR_MODE_MASK, 449 .pstate_val = COMPAT_PSR_MODE_USR, 450 .fn = swp_handler 451 }, 452 { } 453 }; 454 455 static struct insn_emulation_ops swp_ops = { 456 .name = "swp", 457 .status = INSN_OBSOLETE, 458 .hooks = swp_hooks, 459 .set_hw_mode = NULL, 460 }; 461 462 static int cp15barrier_handler(struct pt_regs *regs, u32 instr) 463 { 464 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc); 465 466 switch (aarch32_check_condition(instr, regs->pstate)) { 467 case ARM_OPCODE_CONDTEST_PASS: 468 break; 469 case ARM_OPCODE_CONDTEST_FAIL: 470 /* Condition failed - return to next instruction */ 471 goto ret; 472 case ARM_OPCODE_CONDTEST_UNCOND: 473 /* If unconditional encoding - not a barrier instruction */ 474 return -EFAULT; 475 default: 476 return -EINVAL; 477 } 478 479 switch (aarch32_insn_mcr_extract_crm(instr)) { 480 case 10: 481 /* 482 * dmb - mcr p15, 0, Rt, c7, c10, 5 483 * dsb - mcr p15, 0, Rt, c7, c10, 4 484 */ 485 if (aarch32_insn_mcr_extract_opc2(instr) == 5) { 486 dmb(sy); 487 trace_instruction_emulation( 488 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc); 489 } else { 490 dsb(sy); 491 trace_instruction_emulation( 492 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc); 493 } 494 break; 495 case 5: 496 /* 497 * isb - mcr p15, 0, Rt, c7, c5, 4 498 * 499 * Taking an exception or returning from one acts as an 500 * instruction barrier. So no explicit barrier needed here. 501 */ 502 trace_instruction_emulation( 503 "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc); 504 break; 505 } 506 507 ret: 508 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n", 509 current->comm, (unsigned long)current->pid, regs->pc); 510 511 regs->pc += 4; 512 return 0; 513 } 514 515 static int cp15_barrier_set_hw_mode(bool enable) 516 { 517 if (enable) 518 config_sctlr_el1(0, SCTLR_EL1_CP15BEN); 519 else 520 config_sctlr_el1(SCTLR_EL1_CP15BEN, 0); 521 return 0; 522 } 523 524 static struct undef_hook cp15_barrier_hooks[] = { 525 { 526 .instr_mask = 0x0fff0fdf, 527 .instr_val = 0x0e070f9a, 528 .pstate_mask = COMPAT_PSR_MODE_MASK, 529 .pstate_val = COMPAT_PSR_MODE_USR, 530 .fn = cp15barrier_handler, 531 }, 532 { 533 .instr_mask = 0x0fff0fff, 534 .instr_val = 0x0e070f95, 535 .pstate_mask = COMPAT_PSR_MODE_MASK, 536 .pstate_val = COMPAT_PSR_MODE_USR, 537 .fn = cp15barrier_handler, 538 }, 539 { } 540 }; 541 542 static struct insn_emulation_ops cp15_barrier_ops = { 543 .name = "cp15_barrier", 544 .status = INSN_DEPRECATED, 545 .hooks = cp15_barrier_hooks, 546 .set_hw_mode = cp15_barrier_set_hw_mode, 547 }; 548 549 static int setend_set_hw_mode(bool enable) 550 { 551 if (!cpu_supports_mixed_endian_el0()) 552 return -EINVAL; 553 554 if (enable) 555 config_sctlr_el1(SCTLR_EL1_SED, 0); 556 else 557 config_sctlr_el1(0, SCTLR_EL1_SED); 558 return 0; 559 } 560 561 static int compat_setend_handler(struct pt_regs *regs, u32 big_endian) 562 { 563 char *insn; 564 565 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc); 566 567 if (big_endian) { 568 insn = "setend be"; 569 regs->pstate |= COMPAT_PSR_E_BIT; 570 } else { 571 insn = "setend le"; 572 regs->pstate &= ~COMPAT_PSR_E_BIT; 573 } 574 575 trace_instruction_emulation(insn, regs->pc); 576 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n", 577 current->comm, (unsigned long)current->pid, regs->pc); 578 579 return 0; 580 } 581 582 static int a32_setend_handler(struct pt_regs *regs, u32 instr) 583 { 584 int rc = compat_setend_handler(regs, (instr >> 9) & 1); 585 regs->pc += 4; 586 return rc; 587 } 588 589 static int t16_setend_handler(struct pt_regs *regs, u32 instr) 590 { 591 int rc = compat_setend_handler(regs, (instr >> 3) & 1); 592 regs->pc += 2; 593 return rc; 594 } 595 596 static struct undef_hook setend_hooks[] = { 597 { 598 .instr_mask = 0xfffffdff, 599 .instr_val = 0xf1010000, 600 .pstate_mask = COMPAT_PSR_MODE_MASK, 601 .pstate_val = COMPAT_PSR_MODE_USR, 602 .fn = a32_setend_handler, 603 }, 604 { 605 /* Thumb mode */ 606 .instr_mask = 0x0000fff7, 607 .instr_val = 0x0000b650, 608 .pstate_mask = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK), 609 .pstate_val = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR), 610 .fn = t16_setend_handler, 611 }, 612 {} 613 }; 614 615 static struct insn_emulation_ops setend_ops = { 616 .name = "setend", 617 .status = INSN_DEPRECATED, 618 .hooks = setend_hooks, 619 .set_hw_mode = setend_set_hw_mode, 620 }; 621 622 /* 623 * Invoked as late_initcall, since not needed before init spawned. 624 */ 625 static int __init armv8_deprecated_init(void) 626 { 627 if (IS_ENABLED(CONFIG_SWP_EMULATION)) 628 register_insn_emulation(&swp_ops); 629 630 if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION)) 631 register_insn_emulation(&cp15_barrier_ops); 632 633 if (IS_ENABLED(CONFIG_SETEND_EMULATION)) { 634 if(system_supports_mixed_endian_el0()) 635 register_insn_emulation(&setend_ops); 636 else 637 pr_info("setend instruction emulation is not supported on the system"); 638 } 639 640 cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING, 641 "AP_ARM64_ISNDEP_STARTING", 642 run_all_insn_set_hw_mode, NULL); 643 register_insn_emulation_sysctl(ctl_abi); 644 645 return 0; 646 } 647 648 late_initcall(armv8_deprecated_init); 649