1 /* 2 * Copyright (C) 2014 ARM Limited 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/cpu.h> 10 #include <linux/init.h> 11 #include <linux/list.h> 12 #include <linux/perf_event.h> 13 #include <linux/sched.h> 14 #include <linux/slab.h> 15 #include <linux/sysctl.h> 16 17 #include <asm/cpufeature.h> 18 #include <asm/insn.h> 19 #include <asm/sysreg.h> 20 #include <asm/system_misc.h> 21 #include <asm/traps.h> 22 #include <asm/kprobes.h> 23 #include <linux/uaccess.h> 24 #include <asm/cpufeature.h> 25 26 #define CREATE_TRACE_POINTS 27 #include "trace-events-emulation.h" 28 29 /* 30 * The runtime support for deprecated instruction support can be in one of 31 * following three states - 32 * 33 * 0 = undef 34 * 1 = emulate (software emulation) 35 * 2 = hw (supported in hardware) 36 */ 37 enum insn_emulation_mode { 38 INSN_UNDEF, 39 INSN_EMULATE, 40 INSN_HW, 41 }; 42 43 enum legacy_insn_status { 44 INSN_DEPRECATED, 45 INSN_OBSOLETE, 46 }; 47 48 struct insn_emulation_ops { 49 const char *name; 50 enum legacy_insn_status status; 51 struct undef_hook *hooks; 52 int (*set_hw_mode)(bool enable); 53 }; 54 55 struct insn_emulation { 56 struct list_head node; 57 struct insn_emulation_ops *ops; 58 int current_mode; 59 int min; 60 int max; 61 }; 62 63 static LIST_HEAD(insn_emulation); 64 static int nr_insn_emulated __initdata; 65 static DEFINE_RAW_SPINLOCK(insn_emulation_lock); 66 67 static void register_emulation_hooks(struct insn_emulation_ops *ops) 68 { 69 struct undef_hook *hook; 70 71 BUG_ON(!ops->hooks); 72 73 for (hook = ops->hooks; hook->instr_mask; hook++) 74 register_undef_hook(hook); 75 76 pr_notice("Registered %s emulation handler\n", ops->name); 77 } 78 79 static void remove_emulation_hooks(struct insn_emulation_ops *ops) 80 { 81 struct undef_hook *hook; 82 83 BUG_ON(!ops->hooks); 84 85 for (hook = ops->hooks; hook->instr_mask; hook++) 86 unregister_undef_hook(hook); 87 88 pr_notice("Removed %s emulation handler\n", ops->name); 89 } 90 91 static void enable_insn_hw_mode(void *data) 92 { 93 struct insn_emulation *insn = (struct insn_emulation *)data; 94 if (insn->ops->set_hw_mode) 95 insn->ops->set_hw_mode(true); 96 } 97 98 static void disable_insn_hw_mode(void *data) 99 { 100 struct insn_emulation *insn = (struct insn_emulation *)data; 101 if (insn->ops->set_hw_mode) 102 insn->ops->set_hw_mode(false); 103 } 104 105 /* Run set_hw_mode(mode) on all active CPUs */ 106 static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable) 107 { 108 if (!insn->ops->set_hw_mode) 109 return -EINVAL; 110 if (enable) 111 on_each_cpu(enable_insn_hw_mode, (void *)insn, true); 112 else 113 on_each_cpu(disable_insn_hw_mode, (void *)insn, true); 114 return 0; 115 } 116 117 /* 118 * Run set_hw_mode for all insns on a starting CPU. 119 * Returns: 120 * 0 - If all the hooks ran successfully. 121 * -EINVAL - At least one hook is not supported by the CPU. 122 */ 123 static int run_all_insn_set_hw_mode(unsigned int cpu) 124 { 125 int rc = 0; 126 unsigned long flags; 127 struct insn_emulation *insn; 128 129 raw_spin_lock_irqsave(&insn_emulation_lock, flags); 130 list_for_each_entry(insn, &insn_emulation, node) { 131 bool enable = (insn->current_mode == INSN_HW); 132 if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) { 133 pr_warn("CPU[%u] cannot support the emulation of %s", 134 cpu, insn->ops->name); 135 rc = -EINVAL; 136 } 137 } 138 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags); 139 return rc; 140 } 141 142 static int update_insn_emulation_mode(struct insn_emulation *insn, 143 enum insn_emulation_mode prev) 144 { 145 int ret = 0; 146 147 switch (prev) { 148 case INSN_UNDEF: /* Nothing to be done */ 149 break; 150 case INSN_EMULATE: 151 remove_emulation_hooks(insn->ops); 152 break; 153 case INSN_HW: 154 if (!run_all_cpu_set_hw_mode(insn, false)) 155 pr_notice("Disabled %s support\n", insn->ops->name); 156 break; 157 } 158 159 switch (insn->current_mode) { 160 case INSN_UNDEF: 161 break; 162 case INSN_EMULATE: 163 register_emulation_hooks(insn->ops); 164 break; 165 case INSN_HW: 166 ret = run_all_cpu_set_hw_mode(insn, true); 167 if (!ret) 168 pr_notice("Enabled %s support\n", insn->ops->name); 169 break; 170 } 171 172 return ret; 173 } 174 175 static void __init register_insn_emulation(struct insn_emulation_ops *ops) 176 { 177 unsigned long flags; 178 struct insn_emulation *insn; 179 180 insn = kzalloc(sizeof(*insn), GFP_KERNEL); 181 insn->ops = ops; 182 insn->min = INSN_UNDEF; 183 184 switch (ops->status) { 185 case INSN_DEPRECATED: 186 insn->current_mode = INSN_EMULATE; 187 /* Disable the HW mode if it was turned on at early boot time */ 188 run_all_cpu_set_hw_mode(insn, false); 189 insn->max = INSN_HW; 190 break; 191 case INSN_OBSOLETE: 192 insn->current_mode = INSN_UNDEF; 193 insn->max = INSN_EMULATE; 194 break; 195 } 196 197 raw_spin_lock_irqsave(&insn_emulation_lock, flags); 198 list_add(&insn->node, &insn_emulation); 199 nr_insn_emulated++; 200 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags); 201 202 /* Register any handlers if required */ 203 update_insn_emulation_mode(insn, INSN_UNDEF); 204 } 205 206 static int emulation_proc_handler(struct ctl_table *table, int write, 207 void __user *buffer, size_t *lenp, 208 loff_t *ppos) 209 { 210 int ret = 0; 211 struct insn_emulation *insn = (struct insn_emulation *) table->data; 212 enum insn_emulation_mode prev_mode = insn->current_mode; 213 214 table->data = &insn->current_mode; 215 ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); 216 217 if (ret || !write || prev_mode == insn->current_mode) 218 goto ret; 219 220 ret = update_insn_emulation_mode(insn, prev_mode); 221 if (ret) { 222 /* Mode change failed, revert to previous mode. */ 223 insn->current_mode = prev_mode; 224 update_insn_emulation_mode(insn, INSN_UNDEF); 225 } 226 ret: 227 table->data = insn; 228 return ret; 229 } 230 231 static struct ctl_table ctl_abi[] = { 232 { 233 .procname = "abi", 234 .mode = 0555, 235 }, 236 { } 237 }; 238 239 static void __init register_insn_emulation_sysctl(struct ctl_table *table) 240 { 241 unsigned long flags; 242 int i = 0; 243 struct insn_emulation *insn; 244 struct ctl_table *insns_sysctl, *sysctl; 245 246 insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1), 247 GFP_KERNEL); 248 249 raw_spin_lock_irqsave(&insn_emulation_lock, flags); 250 list_for_each_entry(insn, &insn_emulation, node) { 251 sysctl = &insns_sysctl[i]; 252 253 sysctl->mode = 0644; 254 sysctl->maxlen = sizeof(int); 255 256 sysctl->procname = insn->ops->name; 257 sysctl->data = insn; 258 sysctl->extra1 = &insn->min; 259 sysctl->extra2 = &insn->max; 260 sysctl->proc_handler = emulation_proc_handler; 261 i++; 262 } 263 raw_spin_unlock_irqrestore(&insn_emulation_lock, flags); 264 265 table->child = insns_sysctl; 266 register_sysctl_table(table); 267 } 268 269 /* 270 * Implement emulation of the SWP/SWPB instructions using load-exclusive and 271 * store-exclusive. 272 * 273 * Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>] 274 * Where: Rt = destination 275 * Rt2 = source 276 * Rn = address 277 */ 278 279 /* 280 * Error-checking SWP macros implemented using ldxr{b}/stxr{b} 281 */ 282 283 /* Arbitrary constant to ensure forward-progress of the LL/SC loop */ 284 #define __SWP_LL_SC_LOOPS 4 285 286 #define __user_swpX_asm(data, addr, res, temp, temp2, B) \ 287 do { \ 288 uaccess_enable(); \ 289 __asm__ __volatile__( \ 290 " mov %w3, %w7\n" \ 291 "0: ldxr"B" %w2, [%4]\n" \ 292 "1: stxr"B" %w0, %w1, [%4]\n" \ 293 " cbz %w0, 2f\n" \ 294 " sub %w3, %w3, #1\n" \ 295 " cbnz %w3, 0b\n" \ 296 " mov %w0, %w5\n" \ 297 " b 3f\n" \ 298 "2:\n" \ 299 " mov %w1, %w2\n" \ 300 "3:\n" \ 301 " .pushsection .fixup,\"ax\"\n" \ 302 " .align 2\n" \ 303 "4: mov %w0, %w6\n" \ 304 " b 3b\n" \ 305 " .popsection" \ 306 _ASM_EXTABLE(0b, 4b) \ 307 _ASM_EXTABLE(1b, 4b) \ 308 : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \ 309 : "r" (addr), "i" (-EAGAIN), "i" (-EFAULT), \ 310 "i" (__SWP_LL_SC_LOOPS) \ 311 : "memory"); \ 312 uaccess_disable(); \ 313 } while (0) 314 315 #define __user_swp_asm(data, addr, res, temp, temp2) \ 316 __user_swpX_asm(data, addr, res, temp, temp2, "") 317 #define __user_swpb_asm(data, addr, res, temp, temp2) \ 318 __user_swpX_asm(data, addr, res, temp, temp2, "b") 319 320 /* 321 * Bit 22 of the instruction encoding distinguishes between 322 * the SWP and SWPB variants (bit set means SWPB). 323 */ 324 #define TYPE_SWPB (1 << 22) 325 326 static int emulate_swpX(unsigned int address, unsigned int *data, 327 unsigned int type) 328 { 329 unsigned int res = 0; 330 331 if ((type != TYPE_SWPB) && (address & 0x3)) { 332 /* SWP to unaligned address not permitted */ 333 pr_debug("SWP instruction on unaligned pointer!\n"); 334 return -EFAULT; 335 } 336 337 while (1) { 338 unsigned long temp, temp2; 339 340 if (type == TYPE_SWPB) 341 __user_swpb_asm(*data, address, res, temp, temp2); 342 else 343 __user_swp_asm(*data, address, res, temp, temp2); 344 345 if (likely(res != -EAGAIN) || signal_pending(current)) 346 break; 347 348 cond_resched(); 349 } 350 351 return res; 352 } 353 354 #define ARM_OPCODE_CONDTEST_FAIL 0 355 #define ARM_OPCODE_CONDTEST_PASS 1 356 #define ARM_OPCODE_CONDTEST_UNCOND 2 357 358 #define ARM_OPCODE_CONDITION_UNCOND 0xf 359 360 static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr) 361 { 362 u32 cc_bits = opcode >> 28; 363 364 if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) { 365 if ((*aarch32_opcode_cond_checks[cc_bits])(psr)) 366 return ARM_OPCODE_CONDTEST_PASS; 367 else 368 return ARM_OPCODE_CONDTEST_FAIL; 369 } 370 return ARM_OPCODE_CONDTEST_UNCOND; 371 } 372 373 /* 374 * swp_handler logs the id of calling process, dissects the instruction, sanity 375 * checks the memory location, calls emulate_swpX for the actual operation and 376 * deals with fixup/error handling before returning 377 */ 378 static int swp_handler(struct pt_regs *regs, u32 instr) 379 { 380 u32 destreg, data, type, address = 0; 381 int rn, rt2, res = 0; 382 383 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc); 384 385 type = instr & TYPE_SWPB; 386 387 switch (aarch32_check_condition(instr, regs->pstate)) { 388 case ARM_OPCODE_CONDTEST_PASS: 389 break; 390 case ARM_OPCODE_CONDTEST_FAIL: 391 /* Condition failed - return to next instruction */ 392 goto ret; 393 case ARM_OPCODE_CONDTEST_UNCOND: 394 /* If unconditional encoding - not a SWP, undef */ 395 return -EFAULT; 396 default: 397 return -EINVAL; 398 } 399 400 rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET); 401 rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET); 402 403 address = (u32)regs->user_regs.regs[rn]; 404 data = (u32)regs->user_regs.regs[rt2]; 405 destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET); 406 407 pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n", 408 rn, address, destreg, 409 aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data); 410 411 /* Check access in reasonable access range for both SWP and SWPB */ 412 if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) { 413 pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n", 414 address); 415 goto fault; 416 } 417 418 res = emulate_swpX(address, &data, type); 419 if (res == -EFAULT) 420 goto fault; 421 else if (res == 0) 422 regs->user_regs.regs[destreg] = data; 423 424 ret: 425 if (type == TYPE_SWPB) 426 trace_instruction_emulation("swpb", regs->pc); 427 else 428 trace_instruction_emulation("swp", regs->pc); 429 430 pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n", 431 current->comm, (unsigned long)current->pid, regs->pc); 432 433 regs->pc += 4; 434 return 0; 435 436 fault: 437 pr_debug("SWP{B} emulation: access caused memory abort!\n"); 438 arm64_notify_segfault(regs, address); 439 440 return 0; 441 } 442 443 /* 444 * Only emulate SWP/SWPB executed in ARM state/User mode. 445 * The kernel must be SWP free and SWP{B} does not exist in Thumb. 446 */ 447 static struct undef_hook swp_hooks[] = { 448 { 449 .instr_mask = 0x0fb00ff0, 450 .instr_val = 0x01000090, 451 .pstate_mask = COMPAT_PSR_MODE_MASK, 452 .pstate_val = COMPAT_PSR_MODE_USR, 453 .fn = swp_handler 454 }, 455 { } 456 }; 457 458 static struct insn_emulation_ops swp_ops = { 459 .name = "swp", 460 .status = INSN_OBSOLETE, 461 .hooks = swp_hooks, 462 .set_hw_mode = NULL, 463 }; 464 465 static int cp15barrier_handler(struct pt_regs *regs, u32 instr) 466 { 467 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc); 468 469 switch (aarch32_check_condition(instr, regs->pstate)) { 470 case ARM_OPCODE_CONDTEST_PASS: 471 break; 472 case ARM_OPCODE_CONDTEST_FAIL: 473 /* Condition failed - return to next instruction */ 474 goto ret; 475 case ARM_OPCODE_CONDTEST_UNCOND: 476 /* If unconditional encoding - not a barrier instruction */ 477 return -EFAULT; 478 default: 479 return -EINVAL; 480 } 481 482 switch (aarch32_insn_mcr_extract_crm(instr)) { 483 case 10: 484 /* 485 * dmb - mcr p15, 0, Rt, c7, c10, 5 486 * dsb - mcr p15, 0, Rt, c7, c10, 4 487 */ 488 if (aarch32_insn_mcr_extract_opc2(instr) == 5) { 489 dmb(sy); 490 trace_instruction_emulation( 491 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc); 492 } else { 493 dsb(sy); 494 trace_instruction_emulation( 495 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc); 496 } 497 break; 498 case 5: 499 /* 500 * isb - mcr p15, 0, Rt, c7, c5, 4 501 * 502 * Taking an exception or returning from one acts as an 503 * instruction barrier. So no explicit barrier needed here. 504 */ 505 trace_instruction_emulation( 506 "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc); 507 break; 508 } 509 510 ret: 511 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n", 512 current->comm, (unsigned long)current->pid, regs->pc); 513 514 regs->pc += 4; 515 return 0; 516 } 517 518 static int cp15_barrier_set_hw_mode(bool enable) 519 { 520 if (enable) 521 config_sctlr_el1(0, SCTLR_EL1_CP15BEN); 522 else 523 config_sctlr_el1(SCTLR_EL1_CP15BEN, 0); 524 return 0; 525 } 526 527 static struct undef_hook cp15_barrier_hooks[] = { 528 { 529 .instr_mask = 0x0fff0fdf, 530 .instr_val = 0x0e070f9a, 531 .pstate_mask = COMPAT_PSR_MODE_MASK, 532 .pstate_val = COMPAT_PSR_MODE_USR, 533 .fn = cp15barrier_handler, 534 }, 535 { 536 .instr_mask = 0x0fff0fff, 537 .instr_val = 0x0e070f95, 538 .pstate_mask = COMPAT_PSR_MODE_MASK, 539 .pstate_val = COMPAT_PSR_MODE_USR, 540 .fn = cp15barrier_handler, 541 }, 542 { } 543 }; 544 545 static struct insn_emulation_ops cp15_barrier_ops = { 546 .name = "cp15_barrier", 547 .status = INSN_DEPRECATED, 548 .hooks = cp15_barrier_hooks, 549 .set_hw_mode = cp15_barrier_set_hw_mode, 550 }; 551 552 static int setend_set_hw_mode(bool enable) 553 { 554 if (!cpu_supports_mixed_endian_el0()) 555 return -EINVAL; 556 557 if (enable) 558 config_sctlr_el1(SCTLR_EL1_SED, 0); 559 else 560 config_sctlr_el1(0, SCTLR_EL1_SED); 561 return 0; 562 } 563 564 static int compat_setend_handler(struct pt_regs *regs, u32 big_endian) 565 { 566 char *insn; 567 568 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc); 569 570 if (big_endian) { 571 insn = "setend be"; 572 regs->pstate |= COMPAT_PSR_E_BIT; 573 } else { 574 insn = "setend le"; 575 regs->pstate &= ~COMPAT_PSR_E_BIT; 576 } 577 578 trace_instruction_emulation(insn, regs->pc); 579 pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n", 580 current->comm, (unsigned long)current->pid, regs->pc); 581 582 return 0; 583 } 584 585 static int a32_setend_handler(struct pt_regs *regs, u32 instr) 586 { 587 int rc = compat_setend_handler(regs, (instr >> 9) & 1); 588 regs->pc += 4; 589 return rc; 590 } 591 592 static int t16_setend_handler(struct pt_regs *regs, u32 instr) 593 { 594 int rc = compat_setend_handler(regs, (instr >> 3) & 1); 595 regs->pc += 2; 596 return rc; 597 } 598 599 static struct undef_hook setend_hooks[] = { 600 { 601 .instr_mask = 0xfffffdff, 602 .instr_val = 0xf1010000, 603 .pstate_mask = COMPAT_PSR_MODE_MASK, 604 .pstate_val = COMPAT_PSR_MODE_USR, 605 .fn = a32_setend_handler, 606 }, 607 { 608 /* Thumb mode */ 609 .instr_mask = 0x0000fff7, 610 .instr_val = 0x0000b650, 611 .pstate_mask = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK), 612 .pstate_val = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR), 613 .fn = t16_setend_handler, 614 }, 615 {} 616 }; 617 618 static struct insn_emulation_ops setend_ops = { 619 .name = "setend", 620 .status = INSN_DEPRECATED, 621 .hooks = setend_hooks, 622 .set_hw_mode = setend_set_hw_mode, 623 }; 624 625 /* 626 * Invoked as late_initcall, since not needed before init spawned. 627 */ 628 static int __init armv8_deprecated_init(void) 629 { 630 if (IS_ENABLED(CONFIG_SWP_EMULATION)) 631 register_insn_emulation(&swp_ops); 632 633 if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION)) 634 register_insn_emulation(&cp15_barrier_ops); 635 636 if (IS_ENABLED(CONFIG_SETEND_EMULATION)) { 637 if(system_supports_mixed_endian_el0()) 638 register_insn_emulation(&setend_ops); 639 else 640 pr_info("setend instruction emulation is not supported on this system\n"); 641 } 642 643 cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING, 644 "arm64/isndep:starting", 645 run_all_insn_set_hw_mode, NULL); 646 register_insn_emulation_sysctl(ctl_abi); 647 648 return 0; 649 } 650 651 late_initcall(armv8_deprecated_init); 652