1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Based on arch/arm/include/asm/ptrace.h 4 * 5 * Copyright (C) 1996-2003 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 #ifndef _UAPI__ASM_PTRACE_H 21 #define _UAPI__ASM_PTRACE_H 22 23 #include <linux/types.h> 24 25 #include <asm/hwcap.h> 26 #include <asm/sve_context.h> 27 28 29 /* 30 * PSR bits 31 */ 32 #define PSR_MODE_EL0t 0x00000000 33 #define PSR_MODE_EL1t 0x00000004 34 #define PSR_MODE_EL1h 0x00000005 35 #define PSR_MODE_EL2t 0x00000008 36 #define PSR_MODE_EL2h 0x00000009 37 #define PSR_MODE_EL3t 0x0000000c 38 #define PSR_MODE_EL3h 0x0000000d 39 #define PSR_MODE_MASK 0x0000000f 40 41 /* AArch32 CPSR bits */ 42 #define PSR_MODE32_BIT 0x00000010 43 44 /* AArch64 SPSR bits */ 45 #define PSR_F_BIT 0x00000040 46 #define PSR_I_BIT 0x00000080 47 #define PSR_A_BIT 0x00000100 48 #define PSR_D_BIT 0x00000200 49 #define PSR_SSBS_BIT 0x00001000 50 #define PSR_PAN_BIT 0x00400000 51 #define PSR_UAO_BIT 0x00800000 52 #define PSR_V_BIT 0x10000000 53 #define PSR_C_BIT 0x20000000 54 #define PSR_Z_BIT 0x40000000 55 #define PSR_N_BIT 0x80000000 56 57 /* 58 * Groups of PSR bits 59 */ 60 #define PSR_f 0xff000000 /* Flags */ 61 #define PSR_s 0x00ff0000 /* Status */ 62 #define PSR_x 0x0000ff00 /* Extension */ 63 #define PSR_c 0x000000ff /* Control */ 64 65 /* syscall emulation path in ptrace */ 66 #define PTRACE_SYSEMU 31 67 #define PTRACE_SYSEMU_SINGLESTEP 32 68 69 #ifndef __ASSEMBLY__ 70 71 /* 72 * User structures for general purpose, floating point and debug registers. 73 */ 74 struct user_pt_regs { 75 __u64 regs[31]; 76 __u64 sp; 77 __u64 pc; 78 __u64 pstate; 79 }; 80 81 struct user_fpsimd_state { 82 __uint128_t vregs[32]; 83 __u32 fpsr; 84 __u32 fpcr; 85 __u32 __reserved[2]; 86 }; 87 88 struct user_hwdebug_state { 89 __u32 dbg_info; 90 __u32 pad; 91 struct { 92 __u64 addr; 93 __u32 ctrl; 94 __u32 pad; 95 } dbg_regs[16]; 96 }; 97 98 /* SVE/FP/SIMD state (NT_ARM_SVE) */ 99 100 struct user_sve_header { 101 __u32 size; /* total meaningful regset content in bytes */ 102 __u32 max_size; /* maxmium possible size for this thread */ 103 __u16 vl; /* current vector length */ 104 __u16 max_vl; /* maximum possible vector length */ 105 __u16 flags; 106 __u16 __reserved; 107 }; 108 109 /* Definitions for user_sve_header.flags: */ 110 #define SVE_PT_REGS_MASK (1 << 0) 111 112 #define SVE_PT_REGS_FPSIMD 0 113 #define SVE_PT_REGS_SVE SVE_PT_REGS_MASK 114 115 /* 116 * Common SVE_PT_* flags: 117 * These must be kept in sync with prctl interface in <linux/prctl.h> 118 */ 119 #define SVE_PT_VL_INHERIT ((1 << 17) /* PR_SVE_VL_INHERIT */ >> 16) 120 #define SVE_PT_VL_ONEXEC ((1 << 18) /* PR_SVE_SET_VL_ONEXEC */ >> 16) 121 122 123 /* 124 * The remainder of the SVE state follows struct user_sve_header. The 125 * total size of the SVE state (including header) depends on the 126 * metadata in the header: SVE_PT_SIZE(vq, flags) gives the total size 127 * of the state in bytes, including the header. 128 * 129 * Refer to <asm/sigcontext.h> for details of how to pass the correct 130 * "vq" argument to these macros. 131 */ 132 133 /* Offset from the start of struct user_sve_header to the register data */ 134 #define SVE_PT_REGS_OFFSET \ 135 ((sizeof(struct user_sve_header) + (__SVE_VQ_BYTES - 1)) \ 136 / __SVE_VQ_BYTES * __SVE_VQ_BYTES) 137 138 /* 139 * The register data content and layout depends on the value of the 140 * flags field. 141 */ 142 143 /* 144 * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD case: 145 * 146 * The payload starts at offset SVE_PT_FPSIMD_OFFSET, and is of type 147 * struct user_fpsimd_state. Additional data might be appended in the 148 * future: use SVE_PT_FPSIMD_SIZE(vq, flags) to compute the total size. 149 * SVE_PT_FPSIMD_SIZE(vq, flags) will never be less than 150 * sizeof(struct user_fpsimd_state). 151 */ 152 153 #define SVE_PT_FPSIMD_OFFSET SVE_PT_REGS_OFFSET 154 155 #define SVE_PT_FPSIMD_SIZE(vq, flags) (sizeof(struct user_fpsimd_state)) 156 157 /* 158 * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE case: 159 * 160 * The payload starts at offset SVE_PT_SVE_OFFSET, and is of size 161 * SVE_PT_SVE_SIZE(vq, flags). 162 * 163 * Additional macros describe the contents and layout of the payload. 164 * For each, SVE_PT_SVE_x_OFFSET(args) is the start offset relative to 165 * the start of struct user_sve_header, and SVE_PT_SVE_x_SIZE(args) is 166 * the size in bytes: 167 * 168 * x type description 169 * - ---- ----------- 170 * ZREGS \ 171 * ZREG | 172 * PREGS | refer to <asm/sigcontext.h> 173 * PREG | 174 * FFR / 175 * 176 * FPSR uint32_t FPSR 177 * FPCR uint32_t FPCR 178 * 179 * Additional data might be appended in the future. 180 * 181 * The Z-, P- and FFR registers are represented in memory in an endianness- 182 * invariant layout which differs from the layout used for the FPSIMD 183 * V-registers on big-endian systems: see sigcontext.h for more explanation. 184 */ 185 186 #define SVE_PT_SVE_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq) 187 #define SVE_PT_SVE_PREG_SIZE(vq) __SVE_PREG_SIZE(vq) 188 #define SVE_PT_SVE_FFR_SIZE(vq) __SVE_FFR_SIZE(vq) 189 #define SVE_PT_SVE_FPSR_SIZE sizeof(__u32) 190 #define SVE_PT_SVE_FPCR_SIZE sizeof(__u32) 191 192 #define SVE_PT_SVE_OFFSET SVE_PT_REGS_OFFSET 193 194 #define SVE_PT_SVE_ZREGS_OFFSET \ 195 (SVE_PT_REGS_OFFSET + __SVE_ZREGS_OFFSET) 196 #define SVE_PT_SVE_ZREG_OFFSET(vq, n) \ 197 (SVE_PT_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n)) 198 #define SVE_PT_SVE_ZREGS_SIZE(vq) \ 199 (SVE_PT_SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET) 200 201 #define SVE_PT_SVE_PREGS_OFFSET(vq) \ 202 (SVE_PT_REGS_OFFSET + __SVE_PREGS_OFFSET(vq)) 203 #define SVE_PT_SVE_PREG_OFFSET(vq, n) \ 204 (SVE_PT_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n)) 205 #define SVE_PT_SVE_PREGS_SIZE(vq) \ 206 (SVE_PT_SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - \ 207 SVE_PT_SVE_PREGS_OFFSET(vq)) 208 209 #define SVE_PT_SVE_FFR_OFFSET(vq) \ 210 (SVE_PT_REGS_OFFSET + __SVE_FFR_OFFSET(vq)) 211 212 #define SVE_PT_SVE_FPSR_OFFSET(vq) \ 213 ((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) + \ 214 (__SVE_VQ_BYTES - 1)) \ 215 / __SVE_VQ_BYTES * __SVE_VQ_BYTES) 216 #define SVE_PT_SVE_FPCR_OFFSET(vq) \ 217 (SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE) 218 219 /* 220 * Any future extension appended after FPCR must be aligned to the next 221 * 128-bit boundary. 222 */ 223 224 #define SVE_PT_SVE_SIZE(vq, flags) \ 225 ((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE \ 226 - SVE_PT_SVE_OFFSET + (__SVE_VQ_BYTES - 1)) \ 227 / __SVE_VQ_BYTES * __SVE_VQ_BYTES) 228 229 #define SVE_PT_SIZE(vq, flags) \ 230 (((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ? \ 231 SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) \ 232 : SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags)) 233 234 /* pointer authentication masks (NT_ARM_PAC_MASK) */ 235 236 struct user_pac_mask { 237 __u64 data_mask; 238 __u64 insn_mask; 239 }; 240 241 /* pointer authentication keys (NT_ARM_PACA_KEYS, NT_ARM_PACG_KEYS) */ 242 243 struct user_pac_address_keys { 244 __uint128_t apiakey; 245 __uint128_t apibkey; 246 __uint128_t apdakey; 247 __uint128_t apdbkey; 248 }; 249 250 struct user_pac_generic_keys { 251 __uint128_t apgakey; 252 }; 253 254 #endif /* __ASSEMBLY__ */ 255 256 #endif /* _UAPI__ASM_PTRACE_H */ 257