154f81d0eSMarc Zyngier /* 254f81d0eSMarc Zyngier * Copyright (C) 2012,2013 - ARM Ltd 354f81d0eSMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 454f81d0eSMarc Zyngier * 554f81d0eSMarc Zyngier * Derived from arch/arm/include/uapi/asm/kvm.h: 654f81d0eSMarc Zyngier * Copyright (C) 2012 - Virtual Open Systems and Columbia University 754f81d0eSMarc Zyngier * Author: Christoffer Dall <c.dall@virtualopensystems.com> 854f81d0eSMarc Zyngier * 954f81d0eSMarc Zyngier * This program is free software; you can redistribute it and/or modify 1054f81d0eSMarc Zyngier * it under the terms of the GNU General Public License version 2 as 1154f81d0eSMarc Zyngier * published by the Free Software Foundation. 1254f81d0eSMarc Zyngier * 1354f81d0eSMarc Zyngier * This program is distributed in the hope that it will be useful, 1454f81d0eSMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 1554f81d0eSMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1654f81d0eSMarc Zyngier * GNU General Public License for more details. 1754f81d0eSMarc Zyngier * 1854f81d0eSMarc Zyngier * You should have received a copy of the GNU General Public License 1954f81d0eSMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 2054f81d0eSMarc Zyngier */ 2154f81d0eSMarc Zyngier 2254f81d0eSMarc Zyngier #ifndef __ARM_KVM_H__ 2354f81d0eSMarc Zyngier #define __ARM_KVM_H__ 2454f81d0eSMarc Zyngier 2554f81d0eSMarc Zyngier #define KVM_SPSR_EL1 0 2640033a61SMarc Zyngier #define KVM_SPSR_SVC KVM_SPSR_EL1 2740033a61SMarc Zyngier #define KVM_SPSR_ABT 1 2840033a61SMarc Zyngier #define KVM_SPSR_UND 2 2940033a61SMarc Zyngier #define KVM_SPSR_IRQ 3 3040033a61SMarc Zyngier #define KVM_SPSR_FIQ 4 3140033a61SMarc Zyngier #define KVM_NR_SPSR 5 3254f81d0eSMarc Zyngier 3354f81d0eSMarc Zyngier #ifndef __ASSEMBLY__ 347d0f84aaSAnup Patel #include <linux/psci.h> 3554f81d0eSMarc Zyngier #include <asm/types.h> 3654f81d0eSMarc Zyngier #include <asm/ptrace.h> 3754f81d0eSMarc Zyngier 3854f81d0eSMarc Zyngier #define __KVM_HAVE_GUEST_DEBUG 3954f81d0eSMarc Zyngier #define __KVM_HAVE_IRQ_LINE 4098047888SChristoffer Dall #define __KVM_HAVE_READONLY_MEM 4154f81d0eSMarc Zyngier 4254f81d0eSMarc Zyngier #define KVM_REG_SIZE(id) \ 4354f81d0eSMarc Zyngier (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 4454f81d0eSMarc Zyngier 4554f81d0eSMarc Zyngier struct kvm_regs { 4654f81d0eSMarc Zyngier struct user_pt_regs regs; /* sp = sp_el0 */ 4754f81d0eSMarc Zyngier 4854f81d0eSMarc Zyngier __u64 sp_el1; 4954f81d0eSMarc Zyngier __u64 elr_el1; 5054f81d0eSMarc Zyngier 5154f81d0eSMarc Zyngier __u64 spsr[KVM_NR_SPSR]; 5254f81d0eSMarc Zyngier 5354f81d0eSMarc Zyngier struct user_fpsimd_state fp_regs; 5454f81d0eSMarc Zyngier }; 5554f81d0eSMarc Zyngier 5654f81d0eSMarc Zyngier /* Supported Processor Types */ 5754f81d0eSMarc Zyngier #define KVM_ARM_TARGET_AEM_V8 0 5854f81d0eSMarc Zyngier #define KVM_ARM_TARGET_FOUNDATION_V8 1 5954f81d0eSMarc Zyngier #define KVM_ARM_TARGET_CORTEX_A57 2 60e28100bdSAnup Patel #define KVM_ARM_TARGET_XGENE_POTENZA 3 611252b331SMarc Zyngier #define KVM_ARM_TARGET_CORTEX_A53 4 6254f81d0eSMarc Zyngier 631252b331SMarc Zyngier #define KVM_ARM_NUM_TARGETS 5 6454f81d0eSMarc Zyngier 6554f81d0eSMarc Zyngier /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 6654f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_TYPE_SHIFT 0 6754f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 6854f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_ID_SHIFT 16 6954f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 7054f81d0eSMarc Zyngier 7154f81d0eSMarc Zyngier /* Supported device IDs */ 7254f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_VGIC_V2 0 7354f81d0eSMarc Zyngier 7454f81d0eSMarc Zyngier /* Supported VGIC address types */ 7554f81d0eSMarc Zyngier #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 7654f81d0eSMarc Zyngier #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 7754f81d0eSMarc Zyngier 7854f81d0eSMarc Zyngier #define KVM_VGIC_V2_DIST_SIZE 0x1000 7954f81d0eSMarc Zyngier #define KVM_VGIC_V2_CPU_SIZE 0x2000 8054f81d0eSMarc Zyngier 81ac3d3735SAndre Przywara /* Supported VGICv3 address types */ 82ac3d3735SAndre Przywara #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 83ac3d3735SAndre Przywara #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 84ac3d3735SAndre Przywara 85ac3d3735SAndre Przywara #define KVM_VGIC_V3_DIST_SIZE SZ_64K 86ac3d3735SAndre Przywara #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 87ac3d3735SAndre Przywara 88dcd2e40cSMarc Zyngier #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 890d854a60SMarc Zyngier #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 907d0f84aaSAnup Patel #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 91dcd2e40cSMarc Zyngier 9254f81d0eSMarc Zyngier struct kvm_vcpu_init { 9354f81d0eSMarc Zyngier __u32 target; 9454f81d0eSMarc Zyngier __u32 features[7]; 9554f81d0eSMarc Zyngier }; 9654f81d0eSMarc Zyngier 9754f81d0eSMarc Zyngier struct kvm_sregs { 9854f81d0eSMarc Zyngier }; 9954f81d0eSMarc Zyngier 10054f81d0eSMarc Zyngier struct kvm_fpu { 10154f81d0eSMarc Zyngier }; 10254f81d0eSMarc Zyngier 10354f81d0eSMarc Zyngier struct kvm_guest_debug_arch { 10454f81d0eSMarc Zyngier }; 10554f81d0eSMarc Zyngier 10654f81d0eSMarc Zyngier struct kvm_debug_exit_arch { 10754f81d0eSMarc Zyngier }; 10854f81d0eSMarc Zyngier 10954f81d0eSMarc Zyngier struct kvm_sync_regs { 11054f81d0eSMarc Zyngier }; 11154f81d0eSMarc Zyngier 11254f81d0eSMarc Zyngier struct kvm_arch_memory_slot { 11354f81d0eSMarc Zyngier }; 11454f81d0eSMarc Zyngier 1157c8c5e6aSMarc Zyngier /* If you need to interpret the index values, here is the key: */ 1167c8c5e6aSMarc Zyngier #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 1177c8c5e6aSMarc Zyngier #define KVM_REG_ARM_COPROC_SHIFT 16 1187c8c5e6aSMarc Zyngier 1197c8c5e6aSMarc Zyngier /* Normal registers are mapped as coprocessor 16. */ 1207c8c5e6aSMarc Zyngier #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 1217c8c5e6aSMarc Zyngier #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 1227c8c5e6aSMarc Zyngier 1237c8c5e6aSMarc Zyngier /* Some registers need more space to represent values. */ 1247c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 1257c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 1267c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 1277c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 1287c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 1297c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 1307c8c5e6aSMarc Zyngier 1317c8c5e6aSMarc Zyngier /* AArch64 system registers */ 1327c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 1337c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 1347c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 1357c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 1367c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 1377c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 1387c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 1397c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 1407c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 1417c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 1427c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 1437c8c5e6aSMarc Zyngier 14439735a3aSAndre Przywara #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 14539735a3aSAndre Przywara (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 14639735a3aSAndre Przywara KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 14739735a3aSAndre Przywara 14839735a3aSAndre Przywara #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 14939735a3aSAndre Przywara (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 15039735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 15139735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 15239735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 15339735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 15439735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 15539735a3aSAndre Przywara 15639735a3aSAndre Przywara #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 15739735a3aSAndre Przywara 15839735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 15939735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 16039735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 16139735a3aSAndre Przywara 1622a2f3e26SChristoffer Dall /* Device Control API: ARM VGIC */ 1632a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 1642a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 1652a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 1662a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 1672a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 1682a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 1692a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 170a98f26f1SMarc Zyngier #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 171065c0034SEric Auger #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 172065c0034SEric Auger #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 1732a2f3e26SChristoffer Dall 17454f81d0eSMarc Zyngier /* KVM_IRQ_LINE irq field index values */ 17554f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_SHIFT 24 17654f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_MASK 0xff 17754f81d0eSMarc Zyngier #define KVM_ARM_IRQ_VCPU_SHIFT 16 17854f81d0eSMarc Zyngier #define KVM_ARM_IRQ_VCPU_MASK 0xff 17954f81d0eSMarc Zyngier #define KVM_ARM_IRQ_NUM_SHIFT 0 18054f81d0eSMarc Zyngier #define KVM_ARM_IRQ_NUM_MASK 0xffff 18154f81d0eSMarc Zyngier 18254f81d0eSMarc Zyngier /* irq_type field */ 18354f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_CPU 0 18454f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_SPI 1 18554f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_PPI 2 18654f81d0eSMarc Zyngier 18754f81d0eSMarc Zyngier /* out-of-kernel GIC cpu interrupt injection irq_number field */ 18854f81d0eSMarc Zyngier #define KVM_ARM_IRQ_CPU_IRQ 0 18954f81d0eSMarc Zyngier #define KVM_ARM_IRQ_CPU_FIQ 1 19054f81d0eSMarc Zyngier 19154f81d0eSMarc Zyngier /* Highest supported SPI, from VGIC_NR_IRQS */ 19254f81d0eSMarc Zyngier #define KVM_ARM_IRQ_GIC_MAX 127 19354f81d0eSMarc Zyngier 194dcd2e40cSMarc Zyngier /* PSCI interface */ 195dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_BASE 0x95c1ba5e 196dcd2e40cSMarc Zyngier #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 197dcd2e40cSMarc Zyngier 198dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 199dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 200dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 201dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 202dcd2e40cSMarc Zyngier 2037d0f84aaSAnup Patel #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 2047d0f84aaSAnup Patel #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 2057d0f84aaSAnup Patel #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 2067d0f84aaSAnup Patel #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 207dcd2e40cSMarc Zyngier 20854f81d0eSMarc Zyngier #endif 20954f81d0eSMarc Zyngier 21054f81d0eSMarc Zyngier #endif /* __ARM_KVM_H__ */ 211