1e2be04c7SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 254f81d0eSMarc Zyngier /* 354f81d0eSMarc Zyngier * Copyright (C) 2012,2013 - ARM Ltd 454f81d0eSMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 554f81d0eSMarc Zyngier * 654f81d0eSMarc Zyngier * Derived from arch/arm/include/uapi/asm/kvm.h: 754f81d0eSMarc Zyngier * Copyright (C) 2012 - Virtual Open Systems and Columbia University 854f81d0eSMarc Zyngier * Author: Christoffer Dall <c.dall@virtualopensystems.com> 954f81d0eSMarc Zyngier * 1054f81d0eSMarc Zyngier * This program is free software; you can redistribute it and/or modify 1154f81d0eSMarc Zyngier * it under the terms of the GNU General Public License version 2 as 1254f81d0eSMarc Zyngier * published by the Free Software Foundation. 1354f81d0eSMarc Zyngier * 1454f81d0eSMarc Zyngier * This program is distributed in the hope that it will be useful, 1554f81d0eSMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 1654f81d0eSMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1754f81d0eSMarc Zyngier * GNU General Public License for more details. 1854f81d0eSMarc Zyngier * 1954f81d0eSMarc Zyngier * You should have received a copy of the GNU General Public License 2054f81d0eSMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 2154f81d0eSMarc Zyngier */ 2254f81d0eSMarc Zyngier 2354f81d0eSMarc Zyngier #ifndef __ARM_KVM_H__ 2454f81d0eSMarc Zyngier #define __ARM_KVM_H__ 2554f81d0eSMarc Zyngier 2654f81d0eSMarc Zyngier #define KVM_SPSR_EL1 0 2740033a61SMarc Zyngier #define KVM_SPSR_SVC KVM_SPSR_EL1 2840033a61SMarc Zyngier #define KVM_SPSR_ABT 1 2940033a61SMarc Zyngier #define KVM_SPSR_UND 2 3040033a61SMarc Zyngier #define KVM_SPSR_IRQ 3 3140033a61SMarc Zyngier #define KVM_SPSR_FIQ 4 3240033a61SMarc Zyngier #define KVM_NR_SPSR 5 3354f81d0eSMarc Zyngier 3454f81d0eSMarc Zyngier #ifndef __ASSEMBLY__ 357d0f84aaSAnup Patel #include <linux/psci.h> 36d1927915SArnd Bergmann #include <linux/types.h> 3754f81d0eSMarc Zyngier #include <asm/ptrace.h> 388ae6efddSDave Martin #include <asm/sve_context.h> 3954f81d0eSMarc Zyngier 4054f81d0eSMarc Zyngier #define __KVM_HAVE_GUEST_DEBUG 4154f81d0eSMarc Zyngier #define __KVM_HAVE_IRQ_LINE 4298047888SChristoffer Dall #define __KVM_HAVE_READONLY_MEM 43b7b27facSDongjiu Geng #define __KVM_HAVE_VCPU_EVENTS 4454f81d0eSMarc Zyngier 454b4357e0SPaolo Bonzini #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 469cb1096fSGavin Shan #define KVM_DIRTY_LOG_PAGE_OFFSET 64 474b4357e0SPaolo Bonzini 4854f81d0eSMarc Zyngier #define KVM_REG_SIZE(id) \ 4954f81d0eSMarc Zyngier (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 5054f81d0eSMarc Zyngier 5154f81d0eSMarc Zyngier struct kvm_regs { 5254f81d0eSMarc Zyngier struct user_pt_regs regs; /* sp = sp_el0 */ 5354f81d0eSMarc Zyngier 5454f81d0eSMarc Zyngier __u64 sp_el1; 5554f81d0eSMarc Zyngier __u64 elr_el1; 5654f81d0eSMarc Zyngier 5754f81d0eSMarc Zyngier __u64 spsr[KVM_NR_SPSR]; 5854f81d0eSMarc Zyngier 5954f81d0eSMarc Zyngier struct user_fpsimd_state fp_regs; 6054f81d0eSMarc Zyngier }; 6154f81d0eSMarc Zyngier 62bca556acSSuzuki K. Poulose /* 63bca556acSSuzuki K. Poulose * Supported CPU Targets - Adding a new target type is not recommended, 64bca556acSSuzuki K. Poulose * unless there are some special registers not supported by the 65bca556acSSuzuki K. Poulose * genericv8 syreg table. 66bca556acSSuzuki K. Poulose */ 6754f81d0eSMarc Zyngier #define KVM_ARM_TARGET_AEM_V8 0 6854f81d0eSMarc Zyngier #define KVM_ARM_TARGET_FOUNDATION_V8 1 6954f81d0eSMarc Zyngier #define KVM_ARM_TARGET_CORTEX_A57 2 70e28100bdSAnup Patel #define KVM_ARM_TARGET_XGENE_POTENZA 3 711252b331SMarc Zyngier #define KVM_ARM_TARGET_CORTEX_A53 4 72bca556acSSuzuki K. Poulose /* Generic ARM v8 target */ 73bca556acSSuzuki K. Poulose #define KVM_ARM_TARGET_GENERIC_V8 5 7454f81d0eSMarc Zyngier 75bca556acSSuzuki K. Poulose #define KVM_ARM_NUM_TARGETS 6 7654f81d0eSMarc Zyngier 7754f81d0eSMarc Zyngier /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 7854f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_TYPE_SHIFT 0 79ae3b1da9SYang Yingliang #define KVM_ARM_DEVICE_TYPE_MASK GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, \ 80ae3b1da9SYang Yingliang KVM_ARM_DEVICE_TYPE_SHIFT) 8154f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_ID_SHIFT 16 82ae3b1da9SYang Yingliang #define KVM_ARM_DEVICE_ID_MASK GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, \ 83ae3b1da9SYang Yingliang KVM_ARM_DEVICE_ID_SHIFT) 8454f81d0eSMarc Zyngier 8554f81d0eSMarc Zyngier /* Supported device IDs */ 8654f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_VGIC_V2 0 8754f81d0eSMarc Zyngier 8854f81d0eSMarc Zyngier /* Supported VGIC address types */ 8954f81d0eSMarc Zyngier #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 9054f81d0eSMarc Zyngier #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 9154f81d0eSMarc Zyngier 9254f81d0eSMarc Zyngier #define KVM_VGIC_V2_DIST_SIZE 0x1000 9354f81d0eSMarc Zyngier #define KVM_VGIC_V2_CPU_SIZE 0x2000 9454f81d0eSMarc Zyngier 95ac3d3735SAndre Przywara /* Supported VGICv3 address types */ 96ac3d3735SAndre Przywara #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 97ac3d3735SAndre Przywara #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 981085fdc6SAndre Przywara #define KVM_VGIC_ITS_ADDR_TYPE 4 996e407673SEric Auger #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 100ac3d3735SAndre Przywara 101ac3d3735SAndre Przywara #define KVM_VGIC_V3_DIST_SIZE SZ_64K 102ac3d3735SAndre Przywara #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 1031085fdc6SAndre Przywara #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 104ac3d3735SAndre Przywara 105dcd2e40cSMarc Zyngier #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 1060d854a60SMarc Zyngier #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 1077d0f84aaSAnup Patel #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 108808e7381SShannon Zhao #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ 1099033bba4SDave Martin #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ 110a22fa321SAmit Daniel Kachhap #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ 111a22fa321SAmit Daniel Kachhap #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ 11289b0e7deSChristoffer Dall #define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */ 113dcd2e40cSMarc Zyngier 11454f81d0eSMarc Zyngier struct kvm_vcpu_init { 11554f81d0eSMarc Zyngier __u32 target; 11654f81d0eSMarc Zyngier __u32 features[7]; 11754f81d0eSMarc Zyngier }; 11854f81d0eSMarc Zyngier 11954f81d0eSMarc Zyngier struct kvm_sregs { 12054f81d0eSMarc Zyngier }; 12154f81d0eSMarc Zyngier 12254f81d0eSMarc Zyngier struct kvm_fpu { 12354f81d0eSMarc Zyngier }; 12454f81d0eSMarc Zyngier 12521b6f32fSAlex Bennée /* 12621b6f32fSAlex Bennée * See v8 ARM ARM D7.3: Debug Registers 12721b6f32fSAlex Bennée * 12821b6f32fSAlex Bennée * The architectural limit is 16 debug registers of each type although 12921b6f32fSAlex Bennée * in practice there are usually less (see ID_AA64DFR0_EL1). 13021b6f32fSAlex Bennée * 13121b6f32fSAlex Bennée * Although the control registers are architecturally defined as 32 13221b6f32fSAlex Bennée * bits wide we use a 64 bit structure here to keep parity with 13321b6f32fSAlex Bennée * KVM_GET/SET_ONE_REG behaviour which treats all system registers as 13421b6f32fSAlex Bennée * 64 bit values. It also allows for the possibility of the 13521b6f32fSAlex Bennée * architecture expanding the control registers without having to 13621b6f32fSAlex Bennée * change the userspace ABI. 13721b6f32fSAlex Bennée */ 13821b6f32fSAlex Bennée #define KVM_ARM_MAX_DBG_REGS 16 13954f81d0eSMarc Zyngier struct kvm_guest_debug_arch { 14021b6f32fSAlex Bennée __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 14121b6f32fSAlex Bennée __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 14221b6f32fSAlex Bennée __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 14321b6f32fSAlex Bennée __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 14454f81d0eSMarc Zyngier }; 14554f81d0eSMarc Zyngier 14618f3976fSAlexandru Elisei #define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0) 14754f81d0eSMarc Zyngier struct kvm_debug_exit_arch { 14821b6f32fSAlex Bennée __u32 hsr; 14918f3976fSAlexandru Elisei __u32 hsr_high; /* ESR_EL2[61:32] */ 15021b6f32fSAlex Bennée __u64 far; /* used for watchpoints */ 15154f81d0eSMarc Zyngier }; 15254f81d0eSMarc Zyngier 15321b6f32fSAlex Bennée /* 15421b6f32fSAlex Bennée * Architecture specific defines for kvm_guest_debug->control 15521b6f32fSAlex Bennée */ 15621b6f32fSAlex Bennée 15721b6f32fSAlex Bennée #define KVM_GUESTDBG_USE_SW_BP (1 << 16) 15821b6f32fSAlex Bennée #define KVM_GUESTDBG_USE_HW (1 << 17) 15921b6f32fSAlex Bennée 16054f81d0eSMarc Zyngier struct kvm_sync_regs { 1613fe17e68SAlexander Graf /* Used with KVM_CAP_ARM_USER_IRQ */ 1623fe17e68SAlexander Graf __u64 device_irq_level; 16354f81d0eSMarc Zyngier }; 16454f81d0eSMarc Zyngier 165d7eec236SMarc Zyngier /* 166d7eec236SMarc Zyngier * PMU filter structure. Describe a range of events with a particular 167d7eec236SMarc Zyngier * action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER. 168d7eec236SMarc Zyngier */ 169d7eec236SMarc Zyngier struct kvm_pmu_event_filter { 170d7eec236SMarc Zyngier __u16 base_event; 171d7eec236SMarc Zyngier __u16 nevents; 172d7eec236SMarc Zyngier 173d7eec236SMarc Zyngier #define KVM_PMU_EVENT_ALLOW 0 174d7eec236SMarc Zyngier #define KVM_PMU_EVENT_DENY 1 175d7eec236SMarc Zyngier 176d7eec236SMarc Zyngier __u8 action; 177d7eec236SMarc Zyngier __u8 pad[3]; 178d7eec236SMarc Zyngier }; 179d7eec236SMarc Zyngier 180b7b27facSDongjiu Geng /* for KVM_GET/SET_VCPU_EVENTS */ 181b7b27facSDongjiu Geng struct kvm_vcpu_events { 182b7b27facSDongjiu Geng struct { 183b7b27facSDongjiu Geng __u8 serror_pending; 184b7b27facSDongjiu Geng __u8 serror_has_esr; 185da345174SChristoffer Dall __u8 ext_dabt_pending; 186b7b27facSDongjiu Geng /* Align it to 8 bytes */ 187da345174SChristoffer Dall __u8 pad[5]; 188b7b27facSDongjiu Geng __u64 serror_esr; 189b7b27facSDongjiu Geng } exception; 190b7b27facSDongjiu Geng __u32 reserved[12]; 191b7b27facSDongjiu Geng }; 192b7b27facSDongjiu Geng 193f0376edbSSteven Price struct kvm_arm_copy_mte_tags { 194f0376edbSSteven Price __u64 guest_ipa; 195f0376edbSSteven Price __u64 length; 196f0376edbSSteven Price void __user *addr; 197f0376edbSSteven Price __u64 flags; 198f0376edbSSteven Price __u64 reserved[2]; 199f0376edbSSteven Price }; 200f0376edbSSteven Price 201f0376edbSSteven Price #define KVM_ARM_TAGS_TO_GUEST 0 202f0376edbSSteven Price #define KVM_ARM_TAGS_FROM_GUEST 1 203f0376edbSSteven Price 2047c8c5e6aSMarc Zyngier /* If you need to interpret the index values, here is the key: */ 2057c8c5e6aSMarc Zyngier #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 2067c8c5e6aSMarc Zyngier #define KVM_REG_ARM_COPROC_SHIFT 16 2077c8c5e6aSMarc Zyngier 2087c8c5e6aSMarc Zyngier /* Normal registers are mapped as coprocessor 16. */ 2097c8c5e6aSMarc Zyngier #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 2107c8c5e6aSMarc Zyngier #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 2117c8c5e6aSMarc Zyngier 2127c8c5e6aSMarc Zyngier /* Some registers need more space to represent values. */ 2137c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 2147c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 2157c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 2167c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 2177c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 2187c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 2197c8c5e6aSMarc Zyngier 2207c8c5e6aSMarc Zyngier /* AArch64 system registers */ 2217c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 2227c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 2237c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 2247c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 2257c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 2267c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 2277c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 2287c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 2297c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 2307c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 2317c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 2327c8c5e6aSMarc Zyngier 23339735a3aSAndre Przywara #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 23439735a3aSAndre Przywara (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 23539735a3aSAndre Przywara KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 23639735a3aSAndre Przywara 23739735a3aSAndre Przywara #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 23839735a3aSAndre Przywara (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 23939735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 24039735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 24139735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 24239735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 24339735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 24439735a3aSAndre Przywara 24539735a3aSAndre Przywara #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 24639735a3aSAndre Przywara 2475c5196daSChristoffer Dall /* Physical Timer EL0 Registers */ 2485c5196daSChristoffer Dall #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 2495c5196daSChristoffer Dall #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 2505c5196daSChristoffer Dall #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 2515c5196daSChristoffer Dall 252290a6bb0SAndrew Jones /* 253290a6bb0SAndrew Jones * EL0 Virtual Timer Registers 254290a6bb0SAndrew Jones * 255290a6bb0SAndrew Jones * WARNING: 256290a6bb0SAndrew Jones * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined 257290a6bb0SAndrew Jones * with the appropriate register encodings. Their values have been 258290a6bb0SAndrew Jones * accidentally swapped. As this is set API, the definitions here 259290a6bb0SAndrew Jones * must be used, rather than ones derived from the encodings. 260290a6bb0SAndrew Jones */ 26139735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 26239735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 263290a6bb0SAndrew Jones #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 26439735a3aSAndre Przywara 26585bd0ba1SMarc Zyngier /* KVM-as-firmware specific pseudo-registers */ 26685bd0ba1SMarc Zyngier #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) 26785bd0ba1SMarc Zyngier #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 26885bd0ba1SMarc Zyngier KVM_REG_ARM_FW | ((r) & 0xffff)) 26985bd0ba1SMarc Zyngier #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) 27099adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) 27199adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 27299adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 27399adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 27429e8910aSMarc Zyngier 27529e8910aSMarc Zyngier /* 27629e8910aSMarc Zyngier * Only two states can be presented by the host kernel: 27729e8910aSMarc Zyngier * - NOT_REQUIRED: the guest doesn't need to do anything 27829e8910aSMarc Zyngier * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available) 27929e8910aSMarc Zyngier * 28029e8910aSMarc Zyngier * All the other values are deprecated. The host still accepts all 28129e8910aSMarc Zyngier * values (they are ABI), but will narrow them to the above two. 28229e8910aSMarc Zyngier */ 28399adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) 28499adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 28599adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 28699adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 28799adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 28899adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) 28985bd0ba1SMarc Zyngier 290a5905d6aSJames Morse #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 KVM_REG_ARM_FW_REG(3) 291a5905d6aSJames Morse #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL 0 292a5905d6aSJames Morse #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL 1 293a5905d6aSJames Morse #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED 2 294a5905d6aSJames Morse 295e1c9c983SDave Martin /* SVE registers */ 296e1c9c983SDave Martin #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) 297e1c9c983SDave Martin 298e1c9c983SDave Martin /* Z- and P-regs occupy blocks at the following offsets within this range: */ 299e1c9c983SDave Martin #define KVM_REG_ARM64_SVE_ZREG_BASE 0 300e1c9c983SDave Martin #define KVM_REG_ARM64_SVE_PREG_BASE 0x400 3018ae6efddSDave Martin #define KVM_REG_ARM64_SVE_FFR_BASE 0x600 302e1c9c983SDave Martin 3038ae6efddSDave Martin #define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS 3048ae6efddSDave Martin #define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS 3058ae6efddSDave Martin 3068ae6efddSDave Martin #define KVM_ARM64_SVE_MAX_SLICES 32 3078ae6efddSDave Martin 3088ae6efddSDave Martin #define KVM_REG_ARM64_SVE_ZREG(n, i) \ 3098ae6efddSDave Martin (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \ 310e1c9c983SDave Martin KVM_REG_SIZE_U2048 | \ 3118ae6efddSDave Martin (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | \ 3128ae6efddSDave Martin ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 3138ae6efddSDave Martin 3148ae6efddSDave Martin #define KVM_REG_ARM64_SVE_PREG(n, i) \ 3158ae6efddSDave Martin (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \ 316e1c9c983SDave Martin KVM_REG_SIZE_U256 | \ 3178ae6efddSDave Martin (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | \ 3188ae6efddSDave Martin ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 3198ae6efddSDave Martin 3208ae6efddSDave Martin #define KVM_REG_ARM64_SVE_FFR(i) \ 3218ae6efddSDave Martin (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \ 3228ae6efddSDave Martin KVM_REG_SIZE_U256 | \ 3238ae6efddSDave Martin ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 324e1c9c983SDave Martin 32541040cf7SDave Martin /* 32641040cf7SDave Martin * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and 32741040cf7SDave Martin * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness- 32841040cf7SDave Martin * invariant layout which differs from the layout used for the FPSIMD 32941040cf7SDave Martin * V-registers on big-endian systems: see sigcontext.h for more explanation. 33041040cf7SDave Martin */ 33141040cf7SDave Martin 3324bd774e5SDave Martin #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN 3334bd774e5SDave Martin #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX 3344bd774e5SDave Martin 3359033bba4SDave Martin /* Vector lengths pseudo-register: */ 3369033bba4SDave Martin #define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \ 3379033bba4SDave Martin KVM_REG_SIZE_U512 | 0xffff) 3384bd774e5SDave Martin #define KVM_ARM64_SVE_VLS_WORDS \ 3394bd774e5SDave Martin ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1) 3409033bba4SDave Martin 34105714cabSRaghavendra Rao Ananta /* Bitmap feature firmware registers */ 34205714cabSRaghavendra Rao Ananta #define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT) 34305714cabSRaghavendra Rao Ananta #define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 34405714cabSRaghavendra Rao Ananta KVM_REG_ARM_FW_FEAT_BMAP | \ 34505714cabSRaghavendra Rao Ananta ((r) & 0xffff)) 34605714cabSRaghavendra Rao Ananta 34705714cabSRaghavendra Rao Ananta #define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(0) 34805714cabSRaghavendra Rao Ananta 34905714cabSRaghavendra Rao Ananta enum { 35005714cabSRaghavendra Rao Ananta KVM_REG_ARM_STD_BIT_TRNG_V1_0 = 0, 3512cde51f1SMarc Zyngier #ifdef __KERNEL__ 35205714cabSRaghavendra Rao Ananta KVM_REG_ARM_STD_BMAP_BIT_COUNT, 3532cde51f1SMarc Zyngier #endif 35405714cabSRaghavendra Rao Ananta }; 35505714cabSRaghavendra Rao Ananta 356428fd678SRaghavendra Rao Ananta #define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(1) 357428fd678SRaghavendra Rao Ananta 358428fd678SRaghavendra Rao Ananta enum { 359428fd678SRaghavendra Rao Ananta KVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0, 3602cde51f1SMarc Zyngier #ifdef __KERNEL__ 361428fd678SRaghavendra Rao Ananta KVM_REG_ARM_STD_HYP_BMAP_BIT_COUNT, 3622cde51f1SMarc Zyngier #endif 363428fd678SRaghavendra Rao Ananta }; 364428fd678SRaghavendra Rao Ananta 365b22216e1SRaghavendra Rao Ananta #define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(2) 366b22216e1SRaghavendra Rao Ananta 367b22216e1SRaghavendra Rao Ananta enum { 368b22216e1SRaghavendra Rao Ananta KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0, 369b22216e1SRaghavendra Rao Ananta KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1, 3702cde51f1SMarc Zyngier #ifdef __KERNEL__ 371b22216e1SRaghavendra Rao Ananta KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT, 3722cde51f1SMarc Zyngier #endif 373b22216e1SRaghavendra Rao Ananta }; 374b22216e1SRaghavendra Rao Ananta 375*821d935cSOliver Upton /* Device Control API on vm fd */ 376*821d935cSOliver Upton #define KVM_ARM_VM_SMCCC_CTRL 0 377*821d935cSOliver Upton #define KVM_ARM_VM_SMCCC_FILTER 0 378*821d935cSOliver Upton 3792a2f3e26SChristoffer Dall /* Device Control API: ARM VGIC */ 3802a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 3812a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 3822a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 3832a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 3842a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 38594574c94SVijaya Kumar K #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 38694574c94SVijaya Kumar K #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 38794574c94SVijaya Kumar K (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 3882a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 3892a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 390d017d7b0SVijaya Kumar K #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 391a98f26f1SMarc Zyngier #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 392065c0034SEric Auger #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 39394574c94SVijaya Kumar K #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 394d017d7b0SVijaya Kumar K #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 395e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 396876ae234SEric Auger #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 397e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 398e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 399e96a006cSVijaya Kumar K (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 400e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 401e96a006cSVijaya Kumar K #define VGIC_LEVEL_INFO_LINE_LEVEL 0 402d017d7b0SVijaya Kumar K 403065c0034SEric Auger #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 4043b65808fSEric Auger #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 4053b65808fSEric Auger #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 40628077125SEric Auger #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 4073eb4271bSEric Auger #define KVM_DEV_ARM_ITS_CTRL_RESET 4 4082a2f3e26SChristoffer Dall 409bb0c70bcSShannon Zhao /* Device Control API on vcpu fd */ 410bb0c70bcSShannon Zhao #define KVM_ARM_VCPU_PMU_V3_CTRL 0 411bb0c70bcSShannon Zhao #define KVM_ARM_VCPU_PMU_V3_IRQ 0 412bb0c70bcSShannon Zhao #define KVM_ARM_VCPU_PMU_V3_INIT 1 413d7eec236SMarc Zyngier #define KVM_ARM_VCPU_PMU_V3_FILTER 2 4146ee7fca2SAlexandru Elisei #define KVM_ARM_VCPU_PMU_V3_SET_PMU 3 41599a1db7aSChristoffer Dall #define KVM_ARM_VCPU_TIMER_CTRL 1 41699a1db7aSChristoffer Dall #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 41799a1db7aSChristoffer Dall #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 41858772e9aSSteven Price #define KVM_ARM_VCPU_PVTIME_CTRL 2 41958772e9aSSteven Price #define KVM_ARM_VCPU_PVTIME_IPA 0 420bb0c70bcSShannon Zhao 42154f81d0eSMarc Zyngier /* KVM_IRQ_LINE irq field index values */ 42292f35b75SMarc Zyngier #define KVM_ARM_IRQ_VCPU2_SHIFT 28 42392f35b75SMarc Zyngier #define KVM_ARM_IRQ_VCPU2_MASK 0xf 42454f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_SHIFT 24 42592f35b75SMarc Zyngier #define KVM_ARM_IRQ_TYPE_MASK 0xf 42654f81d0eSMarc Zyngier #define KVM_ARM_IRQ_VCPU_SHIFT 16 42754f81d0eSMarc Zyngier #define KVM_ARM_IRQ_VCPU_MASK 0xff 42854f81d0eSMarc Zyngier #define KVM_ARM_IRQ_NUM_SHIFT 0 42954f81d0eSMarc Zyngier #define KVM_ARM_IRQ_NUM_MASK 0xffff 43054f81d0eSMarc Zyngier 43154f81d0eSMarc Zyngier /* irq_type field */ 43254f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_CPU 0 43354f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_SPI 1 43454f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_PPI 2 43554f81d0eSMarc Zyngier 43654f81d0eSMarc Zyngier /* out-of-kernel GIC cpu interrupt injection irq_number field */ 43754f81d0eSMarc Zyngier #define KVM_ARM_IRQ_CPU_IRQ 0 43854f81d0eSMarc Zyngier #define KVM_ARM_IRQ_CPU_FIQ 1 43954f81d0eSMarc Zyngier 440fd1d0ddfSAndre Przywara /* 441fd1d0ddfSAndre Przywara * This used to hold the highest supported SPI, but it is now obsolete 442fd1d0ddfSAndre Przywara * and only here to provide source code level compatibility with older 443fd1d0ddfSAndre Przywara * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. 444fd1d0ddfSAndre Przywara */ 445fd1d0ddfSAndre Przywara #ifndef __KERNEL__ 44654f81d0eSMarc Zyngier #define KVM_ARM_IRQ_GIC_MAX 127 447fd1d0ddfSAndre Przywara #endif 44854f81d0eSMarc Zyngier 449174178feSEric Auger /* One single KVM irqchip, ie. the VGIC */ 450174178feSEric Auger #define KVM_NR_IRQCHIPS 1 451174178feSEric Auger 452dcd2e40cSMarc Zyngier /* PSCI interface */ 453dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_BASE 0x95c1ba5e 454dcd2e40cSMarc Zyngier #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 455dcd2e40cSMarc Zyngier 456dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 457dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 458dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 459dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 460dcd2e40cSMarc Zyngier 4617d0f84aaSAnup Patel #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 4627d0f84aaSAnup Patel #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 4637d0f84aaSAnup Patel #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 4647d0f84aaSAnup Patel #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 465dcd2e40cSMarc Zyngier 46634739fd9SWill Deacon /* arm64-specific kvm_run::system_event flags */ 46734739fd9SWill Deacon /* 46834739fd9SWill Deacon * Reset caused by a PSCI v1.1 SYSTEM_RESET2 call. 46934739fd9SWill Deacon * Valid only when the system event has a type of KVM_SYSTEM_EVENT_RESET. 47034739fd9SWill Deacon */ 47134739fd9SWill Deacon #define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (1ULL << 0) 47234739fd9SWill Deacon 473583cda1bSAlexandru Elisei /* run->fail_entry.hardware_entry_failure_reason codes. */ 474583cda1bSAlexandru Elisei #define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0) 475583cda1bSAlexandru Elisei 476a8308b3fSOliver Upton enum kvm_smccc_filter_action { 477a8308b3fSOliver Upton KVM_SMCCC_FILTER_HANDLE = 0, 478a8308b3fSOliver Upton KVM_SMCCC_FILTER_DENY, 479d824dff1SOliver Upton KVM_SMCCC_FILTER_FWD_TO_USER, 480a8308b3fSOliver Upton 481a8308b3fSOliver Upton #ifdef __KERNEL__ 482a8308b3fSOliver Upton NR_SMCCC_FILTER_ACTIONS 483a8308b3fSOliver Upton #endif 484a8308b3fSOliver Upton }; 485a8308b3fSOliver Upton 486*821d935cSOliver Upton struct kvm_smccc_filter { 487*821d935cSOliver Upton __u32 base; 488*821d935cSOliver Upton __u32 nr_functions; 489*821d935cSOliver Upton __u8 action; 490*821d935cSOliver Upton __u8 pad[15]; 491*821d935cSOliver Upton }; 492*821d935cSOliver Upton 493d824dff1SOliver Upton /* arm64-specific KVM_EXIT_HYPERCALL flags */ 494d824dff1SOliver Upton #define KVM_HYPERCALL_EXIT_SMC (1U << 0) 495d824dff1SOliver Upton 49654f81d0eSMarc Zyngier #endif 49754f81d0eSMarc Zyngier 49854f81d0eSMarc Zyngier #endif /* __ARM_KVM_H__ */ 499