1e2be04c7SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 254f81d0eSMarc Zyngier /* 354f81d0eSMarc Zyngier * Copyright (C) 2012,2013 - ARM Ltd 454f81d0eSMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 554f81d0eSMarc Zyngier * 654f81d0eSMarc Zyngier * Derived from arch/arm/include/uapi/asm/kvm.h: 754f81d0eSMarc Zyngier * Copyright (C) 2012 - Virtual Open Systems and Columbia University 854f81d0eSMarc Zyngier * Author: Christoffer Dall <c.dall@virtualopensystems.com> 954f81d0eSMarc Zyngier * 1054f81d0eSMarc Zyngier * This program is free software; you can redistribute it and/or modify 1154f81d0eSMarc Zyngier * it under the terms of the GNU General Public License version 2 as 1254f81d0eSMarc Zyngier * published by the Free Software Foundation. 1354f81d0eSMarc Zyngier * 1454f81d0eSMarc Zyngier * This program is distributed in the hope that it will be useful, 1554f81d0eSMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 1654f81d0eSMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1754f81d0eSMarc Zyngier * GNU General Public License for more details. 1854f81d0eSMarc Zyngier * 1954f81d0eSMarc Zyngier * You should have received a copy of the GNU General Public License 2054f81d0eSMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 2154f81d0eSMarc Zyngier */ 2254f81d0eSMarc Zyngier 2354f81d0eSMarc Zyngier #ifndef __ARM_KVM_H__ 2454f81d0eSMarc Zyngier #define __ARM_KVM_H__ 2554f81d0eSMarc Zyngier 2654f81d0eSMarc Zyngier #define KVM_SPSR_EL1 0 2740033a61SMarc Zyngier #define KVM_SPSR_SVC KVM_SPSR_EL1 2840033a61SMarc Zyngier #define KVM_SPSR_ABT 1 2940033a61SMarc Zyngier #define KVM_SPSR_UND 2 3040033a61SMarc Zyngier #define KVM_SPSR_IRQ 3 3140033a61SMarc Zyngier #define KVM_SPSR_FIQ 4 3240033a61SMarc Zyngier #define KVM_NR_SPSR 5 3354f81d0eSMarc Zyngier 3454f81d0eSMarc Zyngier #ifndef __ASSEMBLY__ 357d0f84aaSAnup Patel #include <linux/psci.h> 36d1927915SArnd Bergmann #include <linux/types.h> 3754f81d0eSMarc Zyngier #include <asm/ptrace.h> 388ae6efddSDave Martin #include <asm/sve_context.h> 3954f81d0eSMarc Zyngier 4054f81d0eSMarc Zyngier #define __KVM_HAVE_GUEST_DEBUG 4154f81d0eSMarc Zyngier #define __KVM_HAVE_IRQ_LINE 4298047888SChristoffer Dall #define __KVM_HAVE_READONLY_MEM 43b7b27facSDongjiu Geng #define __KVM_HAVE_VCPU_EVENTS 4454f81d0eSMarc Zyngier 454b4357e0SPaolo Bonzini #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 464b4357e0SPaolo Bonzini 4754f81d0eSMarc Zyngier #define KVM_REG_SIZE(id) \ 4854f81d0eSMarc Zyngier (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 4954f81d0eSMarc Zyngier 5054f81d0eSMarc Zyngier struct kvm_regs { 5154f81d0eSMarc Zyngier struct user_pt_regs regs; /* sp = sp_el0 */ 5254f81d0eSMarc Zyngier 5354f81d0eSMarc Zyngier __u64 sp_el1; 5454f81d0eSMarc Zyngier __u64 elr_el1; 5554f81d0eSMarc Zyngier 5654f81d0eSMarc Zyngier __u64 spsr[KVM_NR_SPSR]; 5754f81d0eSMarc Zyngier 5854f81d0eSMarc Zyngier struct user_fpsimd_state fp_regs; 5954f81d0eSMarc Zyngier }; 6054f81d0eSMarc Zyngier 61bca556acSSuzuki K. Poulose /* 62bca556acSSuzuki K. Poulose * Supported CPU Targets - Adding a new target type is not recommended, 63bca556acSSuzuki K. Poulose * unless there are some special registers not supported by the 64bca556acSSuzuki K. Poulose * genericv8 syreg table. 65bca556acSSuzuki K. Poulose */ 6654f81d0eSMarc Zyngier #define KVM_ARM_TARGET_AEM_V8 0 6754f81d0eSMarc Zyngier #define KVM_ARM_TARGET_FOUNDATION_V8 1 6854f81d0eSMarc Zyngier #define KVM_ARM_TARGET_CORTEX_A57 2 69e28100bdSAnup Patel #define KVM_ARM_TARGET_XGENE_POTENZA 3 701252b331SMarc Zyngier #define KVM_ARM_TARGET_CORTEX_A53 4 71bca556acSSuzuki K. Poulose /* Generic ARM v8 target */ 72bca556acSSuzuki K. Poulose #define KVM_ARM_TARGET_GENERIC_V8 5 7354f81d0eSMarc Zyngier 74bca556acSSuzuki K. Poulose #define KVM_ARM_NUM_TARGETS 6 7554f81d0eSMarc Zyngier 7654f81d0eSMarc Zyngier /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 7754f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_TYPE_SHIFT 0 7854f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 7954f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_ID_SHIFT 16 8054f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 8154f81d0eSMarc Zyngier 8254f81d0eSMarc Zyngier /* Supported device IDs */ 8354f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_VGIC_V2 0 8454f81d0eSMarc Zyngier 8554f81d0eSMarc Zyngier /* Supported VGIC address types */ 8654f81d0eSMarc Zyngier #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 8754f81d0eSMarc Zyngier #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 8854f81d0eSMarc Zyngier 8954f81d0eSMarc Zyngier #define KVM_VGIC_V2_DIST_SIZE 0x1000 9054f81d0eSMarc Zyngier #define KVM_VGIC_V2_CPU_SIZE 0x2000 9154f81d0eSMarc Zyngier 92ac3d3735SAndre Przywara /* Supported VGICv3 address types */ 93ac3d3735SAndre Przywara #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 94ac3d3735SAndre Przywara #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 951085fdc6SAndre Przywara #define KVM_VGIC_ITS_ADDR_TYPE 4 966e407673SEric Auger #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 97ac3d3735SAndre Przywara 98ac3d3735SAndre Przywara #define KVM_VGIC_V3_DIST_SIZE SZ_64K 99ac3d3735SAndre Przywara #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 1001085fdc6SAndre Przywara #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 101ac3d3735SAndre Przywara 102dcd2e40cSMarc Zyngier #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 1030d854a60SMarc Zyngier #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 1047d0f84aaSAnup Patel #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 105808e7381SShannon Zhao #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ 1069033bba4SDave Martin #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ 107a22fa321SAmit Daniel Kachhap #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ 108a22fa321SAmit Daniel Kachhap #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ 109dcd2e40cSMarc Zyngier 11054f81d0eSMarc Zyngier struct kvm_vcpu_init { 11154f81d0eSMarc Zyngier __u32 target; 11254f81d0eSMarc Zyngier __u32 features[7]; 11354f81d0eSMarc Zyngier }; 11454f81d0eSMarc Zyngier 11554f81d0eSMarc Zyngier struct kvm_sregs { 11654f81d0eSMarc Zyngier }; 11754f81d0eSMarc Zyngier 11854f81d0eSMarc Zyngier struct kvm_fpu { 11954f81d0eSMarc Zyngier }; 12054f81d0eSMarc Zyngier 12121b6f32fSAlex Bennée /* 12221b6f32fSAlex Bennée * See v8 ARM ARM D7.3: Debug Registers 12321b6f32fSAlex Bennée * 12421b6f32fSAlex Bennée * The architectural limit is 16 debug registers of each type although 12521b6f32fSAlex Bennée * in practice there are usually less (see ID_AA64DFR0_EL1). 12621b6f32fSAlex Bennée * 12721b6f32fSAlex Bennée * Although the control registers are architecturally defined as 32 12821b6f32fSAlex Bennée * bits wide we use a 64 bit structure here to keep parity with 12921b6f32fSAlex Bennée * KVM_GET/SET_ONE_REG behaviour which treats all system registers as 13021b6f32fSAlex Bennée * 64 bit values. It also allows for the possibility of the 13121b6f32fSAlex Bennée * architecture expanding the control registers without having to 13221b6f32fSAlex Bennée * change the userspace ABI. 13321b6f32fSAlex Bennée */ 13421b6f32fSAlex Bennée #define KVM_ARM_MAX_DBG_REGS 16 13554f81d0eSMarc Zyngier struct kvm_guest_debug_arch { 13621b6f32fSAlex Bennée __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 13721b6f32fSAlex Bennée __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 13821b6f32fSAlex Bennée __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 13921b6f32fSAlex Bennée __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 14054f81d0eSMarc Zyngier }; 14154f81d0eSMarc Zyngier 14254f81d0eSMarc Zyngier struct kvm_debug_exit_arch { 14321b6f32fSAlex Bennée __u32 hsr; 14421b6f32fSAlex Bennée __u64 far; /* used for watchpoints */ 14554f81d0eSMarc Zyngier }; 14654f81d0eSMarc Zyngier 14721b6f32fSAlex Bennée /* 14821b6f32fSAlex Bennée * Architecture specific defines for kvm_guest_debug->control 14921b6f32fSAlex Bennée */ 15021b6f32fSAlex Bennée 15121b6f32fSAlex Bennée #define KVM_GUESTDBG_USE_SW_BP (1 << 16) 15221b6f32fSAlex Bennée #define KVM_GUESTDBG_USE_HW (1 << 17) 15321b6f32fSAlex Bennée 15454f81d0eSMarc Zyngier struct kvm_sync_regs { 1553fe17e68SAlexander Graf /* Used with KVM_CAP_ARM_USER_IRQ */ 1563fe17e68SAlexander Graf __u64 device_irq_level; 15754f81d0eSMarc Zyngier }; 15854f81d0eSMarc Zyngier 15954f81d0eSMarc Zyngier struct kvm_arch_memory_slot { 16054f81d0eSMarc Zyngier }; 16154f81d0eSMarc Zyngier 162b7b27facSDongjiu Geng /* for KVM_GET/SET_VCPU_EVENTS */ 163b7b27facSDongjiu Geng struct kvm_vcpu_events { 164b7b27facSDongjiu Geng struct { 165b7b27facSDongjiu Geng __u8 serror_pending; 166b7b27facSDongjiu Geng __u8 serror_has_esr; 167b7b27facSDongjiu Geng /* Align it to 8 bytes */ 168b7b27facSDongjiu Geng __u8 pad[6]; 169b7b27facSDongjiu Geng __u64 serror_esr; 170b7b27facSDongjiu Geng } exception; 171b7b27facSDongjiu Geng __u32 reserved[12]; 172b7b27facSDongjiu Geng }; 173b7b27facSDongjiu Geng 1747c8c5e6aSMarc Zyngier /* If you need to interpret the index values, here is the key: */ 1757c8c5e6aSMarc Zyngier #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 1767c8c5e6aSMarc Zyngier #define KVM_REG_ARM_COPROC_SHIFT 16 1777c8c5e6aSMarc Zyngier 1787c8c5e6aSMarc Zyngier /* Normal registers are mapped as coprocessor 16. */ 1797c8c5e6aSMarc Zyngier #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 1807c8c5e6aSMarc Zyngier #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 1817c8c5e6aSMarc Zyngier 1827c8c5e6aSMarc Zyngier /* Some registers need more space to represent values. */ 1837c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 1847c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 1857c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 1867c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 1877c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 1887c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 1897c8c5e6aSMarc Zyngier 1907c8c5e6aSMarc Zyngier /* AArch64 system registers */ 1917c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 1927c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 1937c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 1947c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 1957c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 1967c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 1977c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 1987c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 1997c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 2007c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 2017c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 2027c8c5e6aSMarc Zyngier 20339735a3aSAndre Przywara #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 20439735a3aSAndre Przywara (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 20539735a3aSAndre Przywara KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 20639735a3aSAndre Przywara 20739735a3aSAndre Przywara #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 20839735a3aSAndre Przywara (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 20939735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 21039735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 21139735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 21239735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 21339735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 21439735a3aSAndre Przywara 21539735a3aSAndre Przywara #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 21639735a3aSAndre Przywara 2175c5196daSChristoffer Dall /* Physical Timer EL0 Registers */ 2185c5196daSChristoffer Dall #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 2195c5196daSChristoffer Dall #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 2205c5196daSChristoffer Dall #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 2215c5196daSChristoffer Dall 2225c5196daSChristoffer Dall /* EL0 Virtual Timer Registers */ 22339735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 22439735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 22539735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 22639735a3aSAndre Przywara 22785bd0ba1SMarc Zyngier /* KVM-as-firmware specific pseudo-registers */ 22885bd0ba1SMarc Zyngier #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) 22985bd0ba1SMarc Zyngier #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 23085bd0ba1SMarc Zyngier KVM_REG_ARM_FW | ((r) & 0xffff)) 23185bd0ba1SMarc Zyngier #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) 23285bd0ba1SMarc Zyngier 233e1c9c983SDave Martin /* SVE registers */ 234e1c9c983SDave Martin #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) 235e1c9c983SDave Martin 236e1c9c983SDave Martin /* Z- and P-regs occupy blocks at the following offsets within this range: */ 237e1c9c983SDave Martin #define KVM_REG_ARM64_SVE_ZREG_BASE 0 238e1c9c983SDave Martin #define KVM_REG_ARM64_SVE_PREG_BASE 0x400 2398ae6efddSDave Martin #define KVM_REG_ARM64_SVE_FFR_BASE 0x600 240e1c9c983SDave Martin 2418ae6efddSDave Martin #define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS 2428ae6efddSDave Martin #define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS 2438ae6efddSDave Martin 2448ae6efddSDave Martin #define KVM_ARM64_SVE_MAX_SLICES 32 2458ae6efddSDave Martin 2468ae6efddSDave Martin #define KVM_REG_ARM64_SVE_ZREG(n, i) \ 2478ae6efddSDave Martin (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \ 248e1c9c983SDave Martin KVM_REG_SIZE_U2048 | \ 2498ae6efddSDave Martin (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | \ 2508ae6efddSDave Martin ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 2518ae6efddSDave Martin 2528ae6efddSDave Martin #define KVM_REG_ARM64_SVE_PREG(n, i) \ 2538ae6efddSDave Martin (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \ 254e1c9c983SDave Martin KVM_REG_SIZE_U256 | \ 2558ae6efddSDave Martin (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | \ 2568ae6efddSDave Martin ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 2578ae6efddSDave Martin 2588ae6efddSDave Martin #define KVM_REG_ARM64_SVE_FFR(i) \ 2598ae6efddSDave Martin (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \ 2608ae6efddSDave Martin KVM_REG_SIZE_U256 | \ 2618ae6efddSDave Martin ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 262e1c9c983SDave Martin 26341040cf7SDave Martin /* 26441040cf7SDave Martin * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and 26541040cf7SDave Martin * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness- 26641040cf7SDave Martin * invariant layout which differs from the layout used for the FPSIMD 26741040cf7SDave Martin * V-registers on big-endian systems: see sigcontext.h for more explanation. 26841040cf7SDave Martin */ 26941040cf7SDave Martin 2704bd774e5SDave Martin #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN 2714bd774e5SDave Martin #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX 2724bd774e5SDave Martin 2739033bba4SDave Martin /* Vector lengths pseudo-register: */ 2749033bba4SDave Martin #define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \ 2759033bba4SDave Martin KVM_REG_SIZE_U512 | 0xffff) 2764bd774e5SDave Martin #define KVM_ARM64_SVE_VLS_WORDS \ 2774bd774e5SDave Martin ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1) 2789033bba4SDave Martin 2792a2f3e26SChristoffer Dall /* Device Control API: ARM VGIC */ 2802a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 2812a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 2822a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 2832a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 2842a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 28594574c94SVijaya Kumar K #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 28694574c94SVijaya Kumar K #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 28794574c94SVijaya Kumar K (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 2882a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 2892a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 290d017d7b0SVijaya Kumar K #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 291a98f26f1SMarc Zyngier #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 292065c0034SEric Auger #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 29394574c94SVijaya Kumar K #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 294d017d7b0SVijaya Kumar K #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 295e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 296876ae234SEric Auger #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 297e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 298e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 299e96a006cSVijaya Kumar K (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 300e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 301e96a006cSVijaya Kumar K #define VGIC_LEVEL_INFO_LINE_LEVEL 0 302d017d7b0SVijaya Kumar K 303065c0034SEric Auger #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 3043b65808fSEric Auger #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 3053b65808fSEric Auger #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 30628077125SEric Auger #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 3073eb4271bSEric Auger #define KVM_DEV_ARM_ITS_CTRL_RESET 4 3082a2f3e26SChristoffer Dall 309bb0c70bcSShannon Zhao /* Device Control API on vcpu fd */ 310bb0c70bcSShannon Zhao #define KVM_ARM_VCPU_PMU_V3_CTRL 0 311bb0c70bcSShannon Zhao #define KVM_ARM_VCPU_PMU_V3_IRQ 0 312bb0c70bcSShannon Zhao #define KVM_ARM_VCPU_PMU_V3_INIT 1 31399a1db7aSChristoffer Dall #define KVM_ARM_VCPU_TIMER_CTRL 1 31499a1db7aSChristoffer Dall #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 31599a1db7aSChristoffer Dall #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 316bb0c70bcSShannon Zhao 31754f81d0eSMarc Zyngier /* KVM_IRQ_LINE irq field index values */ 31854f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_SHIFT 24 31954f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_MASK 0xff 32054f81d0eSMarc Zyngier #define KVM_ARM_IRQ_VCPU_SHIFT 16 32154f81d0eSMarc Zyngier #define KVM_ARM_IRQ_VCPU_MASK 0xff 32254f81d0eSMarc Zyngier #define KVM_ARM_IRQ_NUM_SHIFT 0 32354f81d0eSMarc Zyngier #define KVM_ARM_IRQ_NUM_MASK 0xffff 32454f81d0eSMarc Zyngier 32554f81d0eSMarc Zyngier /* irq_type field */ 32654f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_CPU 0 32754f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_SPI 1 32854f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_PPI 2 32954f81d0eSMarc Zyngier 33054f81d0eSMarc Zyngier /* out-of-kernel GIC cpu interrupt injection irq_number field */ 33154f81d0eSMarc Zyngier #define KVM_ARM_IRQ_CPU_IRQ 0 33254f81d0eSMarc Zyngier #define KVM_ARM_IRQ_CPU_FIQ 1 33354f81d0eSMarc Zyngier 334fd1d0ddfSAndre Przywara /* 335fd1d0ddfSAndre Przywara * This used to hold the highest supported SPI, but it is now obsolete 336fd1d0ddfSAndre Przywara * and only here to provide source code level compatibility with older 337fd1d0ddfSAndre Przywara * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. 338fd1d0ddfSAndre Przywara */ 339fd1d0ddfSAndre Przywara #ifndef __KERNEL__ 34054f81d0eSMarc Zyngier #define KVM_ARM_IRQ_GIC_MAX 127 341fd1d0ddfSAndre Przywara #endif 34254f81d0eSMarc Zyngier 343174178feSEric Auger /* One single KVM irqchip, ie. the VGIC */ 344174178feSEric Auger #define KVM_NR_IRQCHIPS 1 345174178feSEric Auger 346dcd2e40cSMarc Zyngier /* PSCI interface */ 347dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_BASE 0x95c1ba5e 348dcd2e40cSMarc Zyngier #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 349dcd2e40cSMarc Zyngier 350dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 351dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 352dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 353dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 354dcd2e40cSMarc Zyngier 3557d0f84aaSAnup Patel #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 3567d0f84aaSAnup Patel #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 3577d0f84aaSAnup Patel #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 3587d0f84aaSAnup Patel #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 359dcd2e40cSMarc Zyngier 36054f81d0eSMarc Zyngier #endif 36154f81d0eSMarc Zyngier 36254f81d0eSMarc Zyngier #endif /* __ARM_KVM_H__ */ 363