154f81d0eSMarc Zyngier /* 254f81d0eSMarc Zyngier * Copyright (C) 2012,2013 - ARM Ltd 354f81d0eSMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 454f81d0eSMarc Zyngier * 554f81d0eSMarc Zyngier * Derived from arch/arm/include/uapi/asm/kvm.h: 654f81d0eSMarc Zyngier * Copyright (C) 2012 - Virtual Open Systems and Columbia University 754f81d0eSMarc Zyngier * Author: Christoffer Dall <c.dall@virtualopensystems.com> 854f81d0eSMarc Zyngier * 954f81d0eSMarc Zyngier * This program is free software; you can redistribute it and/or modify 1054f81d0eSMarc Zyngier * it under the terms of the GNU General Public License version 2 as 1154f81d0eSMarc Zyngier * published by the Free Software Foundation. 1254f81d0eSMarc Zyngier * 1354f81d0eSMarc Zyngier * This program is distributed in the hope that it will be useful, 1454f81d0eSMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 1554f81d0eSMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1654f81d0eSMarc Zyngier * GNU General Public License for more details. 1754f81d0eSMarc Zyngier * 1854f81d0eSMarc Zyngier * You should have received a copy of the GNU General Public License 1954f81d0eSMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 2054f81d0eSMarc Zyngier */ 2154f81d0eSMarc Zyngier 2254f81d0eSMarc Zyngier #ifndef __ARM_KVM_H__ 2354f81d0eSMarc Zyngier #define __ARM_KVM_H__ 2454f81d0eSMarc Zyngier 2554f81d0eSMarc Zyngier #define KVM_SPSR_EL1 0 2640033a61SMarc Zyngier #define KVM_SPSR_SVC KVM_SPSR_EL1 2740033a61SMarc Zyngier #define KVM_SPSR_ABT 1 2840033a61SMarc Zyngier #define KVM_SPSR_UND 2 2940033a61SMarc Zyngier #define KVM_SPSR_IRQ 3 3040033a61SMarc Zyngier #define KVM_SPSR_FIQ 4 3140033a61SMarc Zyngier #define KVM_NR_SPSR 5 3254f81d0eSMarc Zyngier 3354f81d0eSMarc Zyngier #ifndef __ASSEMBLY__ 347d0f84aaSAnup Patel #include <linux/psci.h> 35d1927915SArnd Bergmann #include <linux/types.h> 3654f81d0eSMarc Zyngier #include <asm/ptrace.h> 3754f81d0eSMarc Zyngier 3854f81d0eSMarc Zyngier #define __KVM_HAVE_GUEST_DEBUG 3954f81d0eSMarc Zyngier #define __KVM_HAVE_IRQ_LINE 4098047888SChristoffer Dall #define __KVM_HAVE_READONLY_MEM 4154f81d0eSMarc Zyngier 424b4357e0SPaolo Bonzini #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 434b4357e0SPaolo Bonzini 4454f81d0eSMarc Zyngier #define KVM_REG_SIZE(id) \ 4554f81d0eSMarc Zyngier (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 4654f81d0eSMarc Zyngier 4754f81d0eSMarc Zyngier struct kvm_regs { 4854f81d0eSMarc Zyngier struct user_pt_regs regs; /* sp = sp_el0 */ 4954f81d0eSMarc Zyngier 5054f81d0eSMarc Zyngier __u64 sp_el1; 5154f81d0eSMarc Zyngier __u64 elr_el1; 5254f81d0eSMarc Zyngier 5354f81d0eSMarc Zyngier __u64 spsr[KVM_NR_SPSR]; 5454f81d0eSMarc Zyngier 5554f81d0eSMarc Zyngier struct user_fpsimd_state fp_regs; 5654f81d0eSMarc Zyngier }; 5754f81d0eSMarc Zyngier 58bca556acSSuzuki K. Poulose /* 59bca556acSSuzuki K. Poulose * Supported CPU Targets - Adding a new target type is not recommended, 60bca556acSSuzuki K. Poulose * unless there are some special registers not supported by the 61bca556acSSuzuki K. Poulose * genericv8 syreg table. 62bca556acSSuzuki K. Poulose */ 6354f81d0eSMarc Zyngier #define KVM_ARM_TARGET_AEM_V8 0 6454f81d0eSMarc Zyngier #define KVM_ARM_TARGET_FOUNDATION_V8 1 6554f81d0eSMarc Zyngier #define KVM_ARM_TARGET_CORTEX_A57 2 66e28100bdSAnup Patel #define KVM_ARM_TARGET_XGENE_POTENZA 3 671252b331SMarc Zyngier #define KVM_ARM_TARGET_CORTEX_A53 4 68bca556acSSuzuki K. Poulose /* Generic ARM v8 target */ 69bca556acSSuzuki K. Poulose #define KVM_ARM_TARGET_GENERIC_V8 5 7054f81d0eSMarc Zyngier 71bca556acSSuzuki K. Poulose #define KVM_ARM_NUM_TARGETS 6 7254f81d0eSMarc Zyngier 7354f81d0eSMarc Zyngier /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 7454f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_TYPE_SHIFT 0 7554f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 7654f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_ID_SHIFT 16 7754f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 7854f81d0eSMarc Zyngier 7954f81d0eSMarc Zyngier /* Supported device IDs */ 8054f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_VGIC_V2 0 8154f81d0eSMarc Zyngier 8254f81d0eSMarc Zyngier /* Supported VGIC address types */ 8354f81d0eSMarc Zyngier #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 8454f81d0eSMarc Zyngier #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 8554f81d0eSMarc Zyngier 8654f81d0eSMarc Zyngier #define KVM_VGIC_V2_DIST_SIZE 0x1000 8754f81d0eSMarc Zyngier #define KVM_VGIC_V2_CPU_SIZE 0x2000 8854f81d0eSMarc Zyngier 89ac3d3735SAndre Przywara /* Supported VGICv3 address types */ 90ac3d3735SAndre Przywara #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 91ac3d3735SAndre Przywara #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 921085fdc6SAndre Przywara #define KVM_VGIC_ITS_ADDR_TYPE 4 93ac3d3735SAndre Przywara 94ac3d3735SAndre Przywara #define KVM_VGIC_V3_DIST_SIZE SZ_64K 95ac3d3735SAndre Przywara #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 961085fdc6SAndre Przywara #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 97ac3d3735SAndre Przywara 98dcd2e40cSMarc Zyngier #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 990d854a60SMarc Zyngier #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 1007d0f84aaSAnup Patel #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 101808e7381SShannon Zhao #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ 102dcd2e40cSMarc Zyngier 10354f81d0eSMarc Zyngier struct kvm_vcpu_init { 10454f81d0eSMarc Zyngier __u32 target; 10554f81d0eSMarc Zyngier __u32 features[7]; 10654f81d0eSMarc Zyngier }; 10754f81d0eSMarc Zyngier 10854f81d0eSMarc Zyngier struct kvm_sregs { 10954f81d0eSMarc Zyngier }; 11054f81d0eSMarc Zyngier 11154f81d0eSMarc Zyngier struct kvm_fpu { 11254f81d0eSMarc Zyngier }; 11354f81d0eSMarc Zyngier 11421b6f32fSAlex Bennée /* 11521b6f32fSAlex Bennée * See v8 ARM ARM D7.3: Debug Registers 11621b6f32fSAlex Bennée * 11721b6f32fSAlex Bennée * The architectural limit is 16 debug registers of each type although 11821b6f32fSAlex Bennée * in practice there are usually less (see ID_AA64DFR0_EL1). 11921b6f32fSAlex Bennée * 12021b6f32fSAlex Bennée * Although the control registers are architecturally defined as 32 12121b6f32fSAlex Bennée * bits wide we use a 64 bit structure here to keep parity with 12221b6f32fSAlex Bennée * KVM_GET/SET_ONE_REG behaviour which treats all system registers as 12321b6f32fSAlex Bennée * 64 bit values. It also allows for the possibility of the 12421b6f32fSAlex Bennée * architecture expanding the control registers without having to 12521b6f32fSAlex Bennée * change the userspace ABI. 12621b6f32fSAlex Bennée */ 12721b6f32fSAlex Bennée #define KVM_ARM_MAX_DBG_REGS 16 12854f81d0eSMarc Zyngier struct kvm_guest_debug_arch { 12921b6f32fSAlex Bennée __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 13021b6f32fSAlex Bennée __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 13121b6f32fSAlex Bennée __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 13221b6f32fSAlex Bennée __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 13354f81d0eSMarc Zyngier }; 13454f81d0eSMarc Zyngier 13554f81d0eSMarc Zyngier struct kvm_debug_exit_arch { 13621b6f32fSAlex Bennée __u32 hsr; 13721b6f32fSAlex Bennée __u64 far; /* used for watchpoints */ 13854f81d0eSMarc Zyngier }; 13954f81d0eSMarc Zyngier 14021b6f32fSAlex Bennée /* 14121b6f32fSAlex Bennée * Architecture specific defines for kvm_guest_debug->control 14221b6f32fSAlex Bennée */ 14321b6f32fSAlex Bennée 14421b6f32fSAlex Bennée #define KVM_GUESTDBG_USE_SW_BP (1 << 16) 14521b6f32fSAlex Bennée #define KVM_GUESTDBG_USE_HW (1 << 17) 14621b6f32fSAlex Bennée 14754f81d0eSMarc Zyngier struct kvm_sync_regs { 1483fe17e68SAlexander Graf /* Used with KVM_CAP_ARM_USER_IRQ */ 1493fe17e68SAlexander Graf __u64 device_irq_level; 15054f81d0eSMarc Zyngier }; 15154f81d0eSMarc Zyngier 15254f81d0eSMarc Zyngier struct kvm_arch_memory_slot { 15354f81d0eSMarc Zyngier }; 15454f81d0eSMarc Zyngier 1557c8c5e6aSMarc Zyngier /* If you need to interpret the index values, here is the key: */ 1567c8c5e6aSMarc Zyngier #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 1577c8c5e6aSMarc Zyngier #define KVM_REG_ARM_COPROC_SHIFT 16 1587c8c5e6aSMarc Zyngier 1597c8c5e6aSMarc Zyngier /* Normal registers are mapped as coprocessor 16. */ 1607c8c5e6aSMarc Zyngier #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 1617c8c5e6aSMarc Zyngier #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 1627c8c5e6aSMarc Zyngier 1637c8c5e6aSMarc Zyngier /* Some registers need more space to represent values. */ 1647c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 1657c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 1667c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 1677c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 1687c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 1697c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 1707c8c5e6aSMarc Zyngier 1717c8c5e6aSMarc Zyngier /* AArch64 system registers */ 1727c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 1737c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 1747c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 1757c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 1767c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 1777c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 1787c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 1797c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 1807c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 1817c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 1827c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 1837c8c5e6aSMarc Zyngier 18439735a3aSAndre Przywara #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 18539735a3aSAndre Przywara (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 18639735a3aSAndre Przywara KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 18739735a3aSAndre Przywara 18839735a3aSAndre Przywara #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 18939735a3aSAndre Przywara (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 19039735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 19139735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 19239735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 19339735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 19439735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 19539735a3aSAndre Przywara 19639735a3aSAndre Przywara #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 19739735a3aSAndre Przywara 1985c5196daSChristoffer Dall /* Physical Timer EL0 Registers */ 1995c5196daSChristoffer Dall #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 2005c5196daSChristoffer Dall #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 2015c5196daSChristoffer Dall #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 2025c5196daSChristoffer Dall 2035c5196daSChristoffer Dall /* EL0 Virtual Timer Registers */ 20439735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 20539735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 20639735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 20739735a3aSAndre Przywara 2082a2f3e26SChristoffer Dall /* Device Control API: ARM VGIC */ 2092a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 2102a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 2112a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 2122a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 2132a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 21494574c94SVijaya Kumar K #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 21594574c94SVijaya Kumar K #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 21694574c94SVijaya Kumar K (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 2172a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 2182a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 219d017d7b0SVijaya Kumar K #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 220a98f26f1SMarc Zyngier #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 221065c0034SEric Auger #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 22294574c94SVijaya Kumar K #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 223d017d7b0SVijaya Kumar K #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 224e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 225876ae234SEric Auger #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 226e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 227e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 228e96a006cSVijaya Kumar K (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 229e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 230e96a006cSVijaya Kumar K #define VGIC_LEVEL_INFO_LINE_LEVEL 0 231d017d7b0SVijaya Kumar K 232065c0034SEric Auger #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 2333b65808fSEric Auger #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 2343b65808fSEric Auger #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 23528077125SEric Auger #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 2363eb4271bSEric Auger #define KVM_DEV_ARM_ITS_CTRL_RESET 4 2372a2f3e26SChristoffer Dall 238bb0c70bcSShannon Zhao /* Device Control API on vcpu fd */ 239bb0c70bcSShannon Zhao #define KVM_ARM_VCPU_PMU_V3_CTRL 0 240bb0c70bcSShannon Zhao #define KVM_ARM_VCPU_PMU_V3_IRQ 0 241bb0c70bcSShannon Zhao #define KVM_ARM_VCPU_PMU_V3_INIT 1 24299a1db7aSChristoffer Dall #define KVM_ARM_VCPU_TIMER_CTRL 1 24399a1db7aSChristoffer Dall #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 24499a1db7aSChristoffer Dall #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 245bb0c70bcSShannon Zhao 24654f81d0eSMarc Zyngier /* KVM_IRQ_LINE irq field index values */ 24754f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_SHIFT 24 24854f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_MASK 0xff 24954f81d0eSMarc Zyngier #define KVM_ARM_IRQ_VCPU_SHIFT 16 25054f81d0eSMarc Zyngier #define KVM_ARM_IRQ_VCPU_MASK 0xff 25154f81d0eSMarc Zyngier #define KVM_ARM_IRQ_NUM_SHIFT 0 25254f81d0eSMarc Zyngier #define KVM_ARM_IRQ_NUM_MASK 0xffff 25354f81d0eSMarc Zyngier 25454f81d0eSMarc Zyngier /* irq_type field */ 25554f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_CPU 0 25654f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_SPI 1 25754f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_PPI 2 25854f81d0eSMarc Zyngier 25954f81d0eSMarc Zyngier /* out-of-kernel GIC cpu interrupt injection irq_number field */ 26054f81d0eSMarc Zyngier #define KVM_ARM_IRQ_CPU_IRQ 0 26154f81d0eSMarc Zyngier #define KVM_ARM_IRQ_CPU_FIQ 1 26254f81d0eSMarc Zyngier 263fd1d0ddfSAndre Przywara /* 264fd1d0ddfSAndre Przywara * This used to hold the highest supported SPI, but it is now obsolete 265fd1d0ddfSAndre Przywara * and only here to provide source code level compatibility with older 266fd1d0ddfSAndre Przywara * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. 267fd1d0ddfSAndre Przywara */ 268fd1d0ddfSAndre Przywara #ifndef __KERNEL__ 26954f81d0eSMarc Zyngier #define KVM_ARM_IRQ_GIC_MAX 127 270fd1d0ddfSAndre Przywara #endif 27154f81d0eSMarc Zyngier 272174178feSEric Auger /* One single KVM irqchip, ie. the VGIC */ 273174178feSEric Auger #define KVM_NR_IRQCHIPS 1 274174178feSEric Auger 275dcd2e40cSMarc Zyngier /* PSCI interface */ 276dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_BASE 0x95c1ba5e 277dcd2e40cSMarc Zyngier #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 278dcd2e40cSMarc Zyngier 279dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 280dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 281dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 282dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 283dcd2e40cSMarc Zyngier 2847d0f84aaSAnup Patel #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 2857d0f84aaSAnup Patel #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 2867d0f84aaSAnup Patel #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 2877d0f84aaSAnup Patel #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 288dcd2e40cSMarc Zyngier 28954f81d0eSMarc Zyngier #endif 29054f81d0eSMarc Zyngier 29154f81d0eSMarc Zyngier #endif /* __ARM_KVM_H__ */ 292