1e2be04c7SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 254f81d0eSMarc Zyngier /* 354f81d0eSMarc Zyngier * Copyright (C) 2012,2013 - ARM Ltd 454f81d0eSMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 554f81d0eSMarc Zyngier * 654f81d0eSMarc Zyngier * Derived from arch/arm/include/uapi/asm/kvm.h: 754f81d0eSMarc Zyngier * Copyright (C) 2012 - Virtual Open Systems and Columbia University 854f81d0eSMarc Zyngier * Author: Christoffer Dall <c.dall@virtualopensystems.com> 954f81d0eSMarc Zyngier * 1054f81d0eSMarc Zyngier * This program is free software; you can redistribute it and/or modify 1154f81d0eSMarc Zyngier * it under the terms of the GNU General Public License version 2 as 1254f81d0eSMarc Zyngier * published by the Free Software Foundation. 1354f81d0eSMarc Zyngier * 1454f81d0eSMarc Zyngier * This program is distributed in the hope that it will be useful, 1554f81d0eSMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 1654f81d0eSMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1754f81d0eSMarc Zyngier * GNU General Public License for more details. 1854f81d0eSMarc Zyngier * 1954f81d0eSMarc Zyngier * You should have received a copy of the GNU General Public License 2054f81d0eSMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 2154f81d0eSMarc Zyngier */ 2254f81d0eSMarc Zyngier 2354f81d0eSMarc Zyngier #ifndef __ARM_KVM_H__ 2454f81d0eSMarc Zyngier #define __ARM_KVM_H__ 2554f81d0eSMarc Zyngier 2654f81d0eSMarc Zyngier #define KVM_SPSR_EL1 0 2740033a61SMarc Zyngier #define KVM_SPSR_SVC KVM_SPSR_EL1 2840033a61SMarc Zyngier #define KVM_SPSR_ABT 1 2940033a61SMarc Zyngier #define KVM_SPSR_UND 2 3040033a61SMarc Zyngier #define KVM_SPSR_IRQ 3 3140033a61SMarc Zyngier #define KVM_SPSR_FIQ 4 3240033a61SMarc Zyngier #define KVM_NR_SPSR 5 3354f81d0eSMarc Zyngier 3454f81d0eSMarc Zyngier #ifndef __ASSEMBLY__ 357d0f84aaSAnup Patel #include <linux/psci.h> 36d1927915SArnd Bergmann #include <linux/types.h> 3754f81d0eSMarc Zyngier #include <asm/ptrace.h> 388ae6efddSDave Martin #include <asm/sve_context.h> 3954f81d0eSMarc Zyngier 4054f81d0eSMarc Zyngier #define __KVM_HAVE_GUEST_DEBUG 4154f81d0eSMarc Zyngier #define __KVM_HAVE_IRQ_LINE 4298047888SChristoffer Dall #define __KVM_HAVE_READONLY_MEM 43b7b27facSDongjiu Geng #define __KVM_HAVE_VCPU_EVENTS 4454f81d0eSMarc Zyngier 454b4357e0SPaolo Bonzini #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 464b4357e0SPaolo Bonzini 4754f81d0eSMarc Zyngier #define KVM_REG_SIZE(id) \ 4854f81d0eSMarc Zyngier (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 4954f81d0eSMarc Zyngier 5054f81d0eSMarc Zyngier struct kvm_regs { 5154f81d0eSMarc Zyngier struct user_pt_regs regs; /* sp = sp_el0 */ 5254f81d0eSMarc Zyngier 5354f81d0eSMarc Zyngier __u64 sp_el1; 5454f81d0eSMarc Zyngier __u64 elr_el1; 5554f81d0eSMarc Zyngier 5654f81d0eSMarc Zyngier __u64 spsr[KVM_NR_SPSR]; 5754f81d0eSMarc Zyngier 5854f81d0eSMarc Zyngier struct user_fpsimd_state fp_regs; 5954f81d0eSMarc Zyngier }; 6054f81d0eSMarc Zyngier 61bca556acSSuzuki K. Poulose /* 62bca556acSSuzuki K. Poulose * Supported CPU Targets - Adding a new target type is not recommended, 63bca556acSSuzuki K. Poulose * unless there are some special registers not supported by the 64bca556acSSuzuki K. Poulose * genericv8 syreg table. 65bca556acSSuzuki K. Poulose */ 6654f81d0eSMarc Zyngier #define KVM_ARM_TARGET_AEM_V8 0 6754f81d0eSMarc Zyngier #define KVM_ARM_TARGET_FOUNDATION_V8 1 6854f81d0eSMarc Zyngier #define KVM_ARM_TARGET_CORTEX_A57 2 69e28100bdSAnup Patel #define KVM_ARM_TARGET_XGENE_POTENZA 3 701252b331SMarc Zyngier #define KVM_ARM_TARGET_CORTEX_A53 4 71bca556acSSuzuki K. Poulose /* Generic ARM v8 target */ 72bca556acSSuzuki K. Poulose #define KVM_ARM_TARGET_GENERIC_V8 5 7354f81d0eSMarc Zyngier 74bca556acSSuzuki K. Poulose #define KVM_ARM_NUM_TARGETS 6 7554f81d0eSMarc Zyngier 7654f81d0eSMarc Zyngier /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 7754f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_TYPE_SHIFT 0 7854f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 7954f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_ID_SHIFT 16 8054f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 8154f81d0eSMarc Zyngier 8254f81d0eSMarc Zyngier /* Supported device IDs */ 8354f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_VGIC_V2 0 8454f81d0eSMarc Zyngier 8554f81d0eSMarc Zyngier /* Supported VGIC address types */ 8654f81d0eSMarc Zyngier #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 8754f81d0eSMarc Zyngier #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 8854f81d0eSMarc Zyngier 8954f81d0eSMarc Zyngier #define KVM_VGIC_V2_DIST_SIZE 0x1000 9054f81d0eSMarc Zyngier #define KVM_VGIC_V2_CPU_SIZE 0x2000 9154f81d0eSMarc Zyngier 92ac3d3735SAndre Przywara /* Supported VGICv3 address types */ 93ac3d3735SAndre Przywara #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 94ac3d3735SAndre Przywara #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 951085fdc6SAndre Przywara #define KVM_VGIC_ITS_ADDR_TYPE 4 966e407673SEric Auger #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 97ac3d3735SAndre Przywara 98ac3d3735SAndre Przywara #define KVM_VGIC_V3_DIST_SIZE SZ_64K 99ac3d3735SAndre Przywara #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 1001085fdc6SAndre Przywara #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 101ac3d3735SAndre Przywara 102dcd2e40cSMarc Zyngier #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 1030d854a60SMarc Zyngier #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 1047d0f84aaSAnup Patel #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 105808e7381SShannon Zhao #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ 1069033bba4SDave Martin #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ 107a22fa321SAmit Daniel Kachhap #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ 108a22fa321SAmit Daniel Kachhap #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ 109dcd2e40cSMarc Zyngier 11054f81d0eSMarc Zyngier struct kvm_vcpu_init { 11154f81d0eSMarc Zyngier __u32 target; 11254f81d0eSMarc Zyngier __u32 features[7]; 11354f81d0eSMarc Zyngier }; 11454f81d0eSMarc Zyngier 11554f81d0eSMarc Zyngier struct kvm_sregs { 11654f81d0eSMarc Zyngier }; 11754f81d0eSMarc Zyngier 11854f81d0eSMarc Zyngier struct kvm_fpu { 11954f81d0eSMarc Zyngier }; 12054f81d0eSMarc Zyngier 12121b6f32fSAlex Bennée /* 12221b6f32fSAlex Bennée * See v8 ARM ARM D7.3: Debug Registers 12321b6f32fSAlex Bennée * 12421b6f32fSAlex Bennée * The architectural limit is 16 debug registers of each type although 12521b6f32fSAlex Bennée * in practice there are usually less (see ID_AA64DFR0_EL1). 12621b6f32fSAlex Bennée * 12721b6f32fSAlex Bennée * Although the control registers are architecturally defined as 32 12821b6f32fSAlex Bennée * bits wide we use a 64 bit structure here to keep parity with 12921b6f32fSAlex Bennée * KVM_GET/SET_ONE_REG behaviour which treats all system registers as 13021b6f32fSAlex Bennée * 64 bit values. It also allows for the possibility of the 13121b6f32fSAlex Bennée * architecture expanding the control registers without having to 13221b6f32fSAlex Bennée * change the userspace ABI. 13321b6f32fSAlex Bennée */ 13421b6f32fSAlex Bennée #define KVM_ARM_MAX_DBG_REGS 16 13554f81d0eSMarc Zyngier struct kvm_guest_debug_arch { 13621b6f32fSAlex Bennée __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 13721b6f32fSAlex Bennée __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 13821b6f32fSAlex Bennée __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 13921b6f32fSAlex Bennée __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 14054f81d0eSMarc Zyngier }; 14154f81d0eSMarc Zyngier 14254f81d0eSMarc Zyngier struct kvm_debug_exit_arch { 14321b6f32fSAlex Bennée __u32 hsr; 14421b6f32fSAlex Bennée __u64 far; /* used for watchpoints */ 14554f81d0eSMarc Zyngier }; 14654f81d0eSMarc Zyngier 14721b6f32fSAlex Bennée /* 14821b6f32fSAlex Bennée * Architecture specific defines for kvm_guest_debug->control 14921b6f32fSAlex Bennée */ 15021b6f32fSAlex Bennée 15121b6f32fSAlex Bennée #define KVM_GUESTDBG_USE_SW_BP (1 << 16) 15221b6f32fSAlex Bennée #define KVM_GUESTDBG_USE_HW (1 << 17) 15321b6f32fSAlex Bennée 15454f81d0eSMarc Zyngier struct kvm_sync_regs { 1553fe17e68SAlexander Graf /* Used with KVM_CAP_ARM_USER_IRQ */ 1563fe17e68SAlexander Graf __u64 device_irq_level; 15754f81d0eSMarc Zyngier }; 15854f81d0eSMarc Zyngier 15954f81d0eSMarc Zyngier struct kvm_arch_memory_slot { 16054f81d0eSMarc Zyngier }; 16154f81d0eSMarc Zyngier 162b7b27facSDongjiu Geng /* for KVM_GET/SET_VCPU_EVENTS */ 163b7b27facSDongjiu Geng struct kvm_vcpu_events { 164b7b27facSDongjiu Geng struct { 165b7b27facSDongjiu Geng __u8 serror_pending; 166b7b27facSDongjiu Geng __u8 serror_has_esr; 167da345174SChristoffer Dall __u8 ext_dabt_pending; 168b7b27facSDongjiu Geng /* Align it to 8 bytes */ 169da345174SChristoffer Dall __u8 pad[5]; 170b7b27facSDongjiu Geng __u64 serror_esr; 171b7b27facSDongjiu Geng } exception; 172b7b27facSDongjiu Geng __u32 reserved[12]; 173b7b27facSDongjiu Geng }; 174b7b27facSDongjiu Geng 1757c8c5e6aSMarc Zyngier /* If you need to interpret the index values, here is the key: */ 1767c8c5e6aSMarc Zyngier #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 1777c8c5e6aSMarc Zyngier #define KVM_REG_ARM_COPROC_SHIFT 16 1787c8c5e6aSMarc Zyngier 1797c8c5e6aSMarc Zyngier /* Normal registers are mapped as coprocessor 16. */ 1807c8c5e6aSMarc Zyngier #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 1817c8c5e6aSMarc Zyngier #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 1827c8c5e6aSMarc Zyngier 1837c8c5e6aSMarc Zyngier /* Some registers need more space to represent values. */ 1847c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 1857c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 1867c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 1877c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 1887c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 1897c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 1907c8c5e6aSMarc Zyngier 1917c8c5e6aSMarc Zyngier /* AArch64 system registers */ 1927c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 1937c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 1947c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 1957c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 1967c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 1977c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 1987c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 1997c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 2007c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 2017c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 2027c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 2037c8c5e6aSMarc Zyngier 20439735a3aSAndre Przywara #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 20539735a3aSAndre Przywara (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 20639735a3aSAndre Przywara KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 20739735a3aSAndre Przywara 20839735a3aSAndre Przywara #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 20939735a3aSAndre Przywara (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 21039735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 21139735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 21239735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 21339735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 21439735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 21539735a3aSAndre Przywara 21639735a3aSAndre Przywara #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 21739735a3aSAndre Przywara 2185c5196daSChristoffer Dall /* Physical Timer EL0 Registers */ 2195c5196daSChristoffer Dall #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 2205c5196daSChristoffer Dall #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 2215c5196daSChristoffer Dall #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 2225c5196daSChristoffer Dall 223290a6bb0SAndrew Jones /* 224290a6bb0SAndrew Jones * EL0 Virtual Timer Registers 225290a6bb0SAndrew Jones * 226290a6bb0SAndrew Jones * WARNING: 227290a6bb0SAndrew Jones * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined 228290a6bb0SAndrew Jones * with the appropriate register encodings. Their values have been 229290a6bb0SAndrew Jones * accidentally swapped. As this is set API, the definitions here 230290a6bb0SAndrew Jones * must be used, rather than ones derived from the encodings. 231290a6bb0SAndrew Jones */ 23239735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 23339735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 234290a6bb0SAndrew Jones #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 23539735a3aSAndre Przywara 23685bd0ba1SMarc Zyngier /* KVM-as-firmware specific pseudo-registers */ 23785bd0ba1SMarc Zyngier #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) 23885bd0ba1SMarc Zyngier #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 23985bd0ba1SMarc Zyngier KVM_REG_ARM_FW | ((r) & 0xffff)) 24085bd0ba1SMarc Zyngier #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) 24199adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) 24299adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 24399adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 24499adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 24599adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) 24699adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 24799adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 24899adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 24999adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 25099adb567SAndre Przywara #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) 25185bd0ba1SMarc Zyngier 252e1c9c983SDave Martin /* SVE registers */ 253e1c9c983SDave Martin #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) 254e1c9c983SDave Martin 255e1c9c983SDave Martin /* Z- and P-regs occupy blocks at the following offsets within this range: */ 256e1c9c983SDave Martin #define KVM_REG_ARM64_SVE_ZREG_BASE 0 257e1c9c983SDave Martin #define KVM_REG_ARM64_SVE_PREG_BASE 0x400 2588ae6efddSDave Martin #define KVM_REG_ARM64_SVE_FFR_BASE 0x600 259e1c9c983SDave Martin 2608ae6efddSDave Martin #define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS 2618ae6efddSDave Martin #define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS 2628ae6efddSDave Martin 2638ae6efddSDave Martin #define KVM_ARM64_SVE_MAX_SLICES 32 2648ae6efddSDave Martin 2658ae6efddSDave Martin #define KVM_REG_ARM64_SVE_ZREG(n, i) \ 2668ae6efddSDave Martin (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \ 267e1c9c983SDave Martin KVM_REG_SIZE_U2048 | \ 2688ae6efddSDave Martin (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | \ 2698ae6efddSDave Martin ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 2708ae6efddSDave Martin 2718ae6efddSDave Martin #define KVM_REG_ARM64_SVE_PREG(n, i) \ 2728ae6efddSDave Martin (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \ 273e1c9c983SDave Martin KVM_REG_SIZE_U256 | \ 2748ae6efddSDave Martin (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | \ 2758ae6efddSDave Martin ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 2768ae6efddSDave Martin 2778ae6efddSDave Martin #define KVM_REG_ARM64_SVE_FFR(i) \ 2788ae6efddSDave Martin (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \ 2798ae6efddSDave Martin KVM_REG_SIZE_U256 | \ 2808ae6efddSDave Martin ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 281e1c9c983SDave Martin 28241040cf7SDave Martin /* 28341040cf7SDave Martin * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and 28441040cf7SDave Martin * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness- 28541040cf7SDave Martin * invariant layout which differs from the layout used for the FPSIMD 28641040cf7SDave Martin * V-registers on big-endian systems: see sigcontext.h for more explanation. 28741040cf7SDave Martin */ 28841040cf7SDave Martin 2894bd774e5SDave Martin #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN 2904bd774e5SDave Martin #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX 2914bd774e5SDave Martin 2929033bba4SDave Martin /* Vector lengths pseudo-register: */ 2939033bba4SDave Martin #define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \ 2949033bba4SDave Martin KVM_REG_SIZE_U512 | 0xffff) 2954bd774e5SDave Martin #define KVM_ARM64_SVE_VLS_WORDS \ 2964bd774e5SDave Martin ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1) 2979033bba4SDave Martin 2982a2f3e26SChristoffer Dall /* Device Control API: ARM VGIC */ 2992a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 3002a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 3012a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 3022a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 3032a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 30494574c94SVijaya Kumar K #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 30594574c94SVijaya Kumar K #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 30694574c94SVijaya Kumar K (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 3072a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 3082a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 309d017d7b0SVijaya Kumar K #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 310a98f26f1SMarc Zyngier #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 311065c0034SEric Auger #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 31294574c94SVijaya Kumar K #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 313d017d7b0SVijaya Kumar K #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 314e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 315876ae234SEric Auger #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 316e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 317e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 318e96a006cSVijaya Kumar K (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 319e96a006cSVijaya Kumar K #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 320e96a006cSVijaya Kumar K #define VGIC_LEVEL_INFO_LINE_LEVEL 0 321d017d7b0SVijaya Kumar K 322065c0034SEric Auger #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 3233b65808fSEric Auger #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 3243b65808fSEric Auger #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 32528077125SEric Auger #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 3263eb4271bSEric Auger #define KVM_DEV_ARM_ITS_CTRL_RESET 4 3272a2f3e26SChristoffer Dall 328bb0c70bcSShannon Zhao /* Device Control API on vcpu fd */ 329bb0c70bcSShannon Zhao #define KVM_ARM_VCPU_PMU_V3_CTRL 0 330bb0c70bcSShannon Zhao #define KVM_ARM_VCPU_PMU_V3_IRQ 0 331bb0c70bcSShannon Zhao #define KVM_ARM_VCPU_PMU_V3_INIT 1 33299a1db7aSChristoffer Dall #define KVM_ARM_VCPU_TIMER_CTRL 1 33399a1db7aSChristoffer Dall #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 33499a1db7aSChristoffer Dall #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 33558772e9aSSteven Price #define KVM_ARM_VCPU_PVTIME_CTRL 2 33658772e9aSSteven Price #define KVM_ARM_VCPU_PVTIME_IPA 0 337bb0c70bcSShannon Zhao 33854f81d0eSMarc Zyngier /* KVM_IRQ_LINE irq field index values */ 33992f35b75SMarc Zyngier #define KVM_ARM_IRQ_VCPU2_SHIFT 28 34092f35b75SMarc Zyngier #define KVM_ARM_IRQ_VCPU2_MASK 0xf 34154f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_SHIFT 24 34292f35b75SMarc Zyngier #define KVM_ARM_IRQ_TYPE_MASK 0xf 34354f81d0eSMarc Zyngier #define KVM_ARM_IRQ_VCPU_SHIFT 16 34454f81d0eSMarc Zyngier #define KVM_ARM_IRQ_VCPU_MASK 0xff 34554f81d0eSMarc Zyngier #define KVM_ARM_IRQ_NUM_SHIFT 0 34654f81d0eSMarc Zyngier #define KVM_ARM_IRQ_NUM_MASK 0xffff 34754f81d0eSMarc Zyngier 34854f81d0eSMarc Zyngier /* irq_type field */ 34954f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_CPU 0 35054f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_SPI 1 35154f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_PPI 2 35254f81d0eSMarc Zyngier 35354f81d0eSMarc Zyngier /* out-of-kernel GIC cpu interrupt injection irq_number field */ 35454f81d0eSMarc Zyngier #define KVM_ARM_IRQ_CPU_IRQ 0 35554f81d0eSMarc Zyngier #define KVM_ARM_IRQ_CPU_FIQ 1 35654f81d0eSMarc Zyngier 357fd1d0ddfSAndre Przywara /* 358fd1d0ddfSAndre Przywara * This used to hold the highest supported SPI, but it is now obsolete 359fd1d0ddfSAndre Przywara * and only here to provide source code level compatibility with older 360fd1d0ddfSAndre Przywara * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. 361fd1d0ddfSAndre Przywara */ 362fd1d0ddfSAndre Przywara #ifndef __KERNEL__ 36354f81d0eSMarc Zyngier #define KVM_ARM_IRQ_GIC_MAX 127 364fd1d0ddfSAndre Przywara #endif 36554f81d0eSMarc Zyngier 366174178feSEric Auger /* One single KVM irqchip, ie. the VGIC */ 367174178feSEric Auger #define KVM_NR_IRQCHIPS 1 368174178feSEric Auger 369dcd2e40cSMarc Zyngier /* PSCI interface */ 370dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_BASE 0x95c1ba5e 371dcd2e40cSMarc Zyngier #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 372dcd2e40cSMarc Zyngier 373dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 374dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 375dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 376dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 377dcd2e40cSMarc Zyngier 3787d0f84aaSAnup Patel #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 3797d0f84aaSAnup Patel #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 3807d0f84aaSAnup Patel #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 3817d0f84aaSAnup Patel #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 382dcd2e40cSMarc Zyngier 38354f81d0eSMarc Zyngier #endif 38454f81d0eSMarc Zyngier 38554f81d0eSMarc Zyngier #endif /* __ARM_KVM_H__ */ 386