154f81d0eSMarc Zyngier /* 254f81d0eSMarc Zyngier * Copyright (C) 2012,2013 - ARM Ltd 354f81d0eSMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 454f81d0eSMarc Zyngier * 554f81d0eSMarc Zyngier * Derived from arch/arm/include/uapi/asm/kvm.h: 654f81d0eSMarc Zyngier * Copyright (C) 2012 - Virtual Open Systems and Columbia University 754f81d0eSMarc Zyngier * Author: Christoffer Dall <c.dall@virtualopensystems.com> 854f81d0eSMarc Zyngier * 954f81d0eSMarc Zyngier * This program is free software; you can redistribute it and/or modify 1054f81d0eSMarc Zyngier * it under the terms of the GNU General Public License version 2 as 1154f81d0eSMarc Zyngier * published by the Free Software Foundation. 1254f81d0eSMarc Zyngier * 1354f81d0eSMarc Zyngier * This program is distributed in the hope that it will be useful, 1454f81d0eSMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 1554f81d0eSMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1654f81d0eSMarc Zyngier * GNU General Public License for more details. 1754f81d0eSMarc Zyngier * 1854f81d0eSMarc Zyngier * You should have received a copy of the GNU General Public License 1954f81d0eSMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 2054f81d0eSMarc Zyngier */ 2154f81d0eSMarc Zyngier 2254f81d0eSMarc Zyngier #ifndef __ARM_KVM_H__ 2354f81d0eSMarc Zyngier #define __ARM_KVM_H__ 2454f81d0eSMarc Zyngier 2554f81d0eSMarc Zyngier #define KVM_SPSR_EL1 0 2640033a61SMarc Zyngier #define KVM_SPSR_SVC KVM_SPSR_EL1 2740033a61SMarc Zyngier #define KVM_SPSR_ABT 1 2840033a61SMarc Zyngier #define KVM_SPSR_UND 2 2940033a61SMarc Zyngier #define KVM_SPSR_IRQ 3 3040033a61SMarc Zyngier #define KVM_SPSR_FIQ 4 3140033a61SMarc Zyngier #define KVM_NR_SPSR 5 3254f81d0eSMarc Zyngier 3354f81d0eSMarc Zyngier #ifndef __ASSEMBLY__ 347d0f84aaSAnup Patel #include <linux/psci.h> 3554f81d0eSMarc Zyngier #include <asm/types.h> 3654f81d0eSMarc Zyngier #include <asm/ptrace.h> 3754f81d0eSMarc Zyngier 3854f81d0eSMarc Zyngier #define __KVM_HAVE_GUEST_DEBUG 3954f81d0eSMarc Zyngier #define __KVM_HAVE_IRQ_LINE 4098047888SChristoffer Dall #define __KVM_HAVE_READONLY_MEM 4154f81d0eSMarc Zyngier 4254f81d0eSMarc Zyngier #define KVM_REG_SIZE(id) \ 4354f81d0eSMarc Zyngier (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 4454f81d0eSMarc Zyngier 4554f81d0eSMarc Zyngier struct kvm_regs { 4654f81d0eSMarc Zyngier struct user_pt_regs regs; /* sp = sp_el0 */ 4754f81d0eSMarc Zyngier 4854f81d0eSMarc Zyngier __u64 sp_el1; 4954f81d0eSMarc Zyngier __u64 elr_el1; 5054f81d0eSMarc Zyngier 5154f81d0eSMarc Zyngier __u64 spsr[KVM_NR_SPSR]; 5254f81d0eSMarc Zyngier 5354f81d0eSMarc Zyngier struct user_fpsimd_state fp_regs; 5454f81d0eSMarc Zyngier }; 5554f81d0eSMarc Zyngier 5654f81d0eSMarc Zyngier /* Supported Processor Types */ 5754f81d0eSMarc Zyngier #define KVM_ARM_TARGET_AEM_V8 0 5854f81d0eSMarc Zyngier #define KVM_ARM_TARGET_FOUNDATION_V8 1 5954f81d0eSMarc Zyngier #define KVM_ARM_TARGET_CORTEX_A57 2 60e28100bdSAnup Patel #define KVM_ARM_TARGET_XGENE_POTENZA 3 611252b331SMarc Zyngier #define KVM_ARM_TARGET_CORTEX_A53 4 6254f81d0eSMarc Zyngier 631252b331SMarc Zyngier #define KVM_ARM_NUM_TARGETS 5 6454f81d0eSMarc Zyngier 6554f81d0eSMarc Zyngier /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 6654f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_TYPE_SHIFT 0 6754f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 6854f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_ID_SHIFT 16 6954f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 7054f81d0eSMarc Zyngier 7154f81d0eSMarc Zyngier /* Supported device IDs */ 7254f81d0eSMarc Zyngier #define KVM_ARM_DEVICE_VGIC_V2 0 7354f81d0eSMarc Zyngier 7454f81d0eSMarc Zyngier /* Supported VGIC address types */ 7554f81d0eSMarc Zyngier #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 7654f81d0eSMarc Zyngier #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 7754f81d0eSMarc Zyngier 7854f81d0eSMarc Zyngier #define KVM_VGIC_V2_DIST_SIZE 0x1000 7954f81d0eSMarc Zyngier #define KVM_VGIC_V2_CPU_SIZE 0x2000 8054f81d0eSMarc Zyngier 81dcd2e40cSMarc Zyngier #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 820d854a60SMarc Zyngier #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 837d0f84aaSAnup Patel #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 84dcd2e40cSMarc Zyngier 8554f81d0eSMarc Zyngier struct kvm_vcpu_init { 8654f81d0eSMarc Zyngier __u32 target; 8754f81d0eSMarc Zyngier __u32 features[7]; 8854f81d0eSMarc Zyngier }; 8954f81d0eSMarc Zyngier 9054f81d0eSMarc Zyngier struct kvm_sregs { 9154f81d0eSMarc Zyngier }; 9254f81d0eSMarc Zyngier 9354f81d0eSMarc Zyngier struct kvm_fpu { 9454f81d0eSMarc Zyngier }; 9554f81d0eSMarc Zyngier 9654f81d0eSMarc Zyngier struct kvm_guest_debug_arch { 9754f81d0eSMarc Zyngier }; 9854f81d0eSMarc Zyngier 9954f81d0eSMarc Zyngier struct kvm_debug_exit_arch { 10054f81d0eSMarc Zyngier }; 10154f81d0eSMarc Zyngier 10254f81d0eSMarc Zyngier struct kvm_sync_regs { 10354f81d0eSMarc Zyngier }; 10454f81d0eSMarc Zyngier 10554f81d0eSMarc Zyngier struct kvm_arch_memory_slot { 10654f81d0eSMarc Zyngier }; 10754f81d0eSMarc Zyngier 1087c8c5e6aSMarc Zyngier /* If you need to interpret the index values, here is the key: */ 1097c8c5e6aSMarc Zyngier #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 1107c8c5e6aSMarc Zyngier #define KVM_REG_ARM_COPROC_SHIFT 16 1117c8c5e6aSMarc Zyngier 1127c8c5e6aSMarc Zyngier /* Normal registers are mapped as coprocessor 16. */ 1137c8c5e6aSMarc Zyngier #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 1147c8c5e6aSMarc Zyngier #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 1157c8c5e6aSMarc Zyngier 1167c8c5e6aSMarc Zyngier /* Some registers need more space to represent values. */ 1177c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 1187c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 1197c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 1207c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 1217c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 1227c8c5e6aSMarc Zyngier #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 1237c8c5e6aSMarc Zyngier 1247c8c5e6aSMarc Zyngier /* AArch64 system registers */ 1257c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 1267c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 1277c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 1287c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 1297c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 1307c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 1317c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 1327c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 1337c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 1347c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 1357c8c5e6aSMarc Zyngier #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 1367c8c5e6aSMarc Zyngier 13739735a3aSAndre Przywara #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 13839735a3aSAndre Przywara (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 13939735a3aSAndre Przywara KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 14039735a3aSAndre Przywara 14139735a3aSAndre Przywara #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 14239735a3aSAndre Przywara (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 14339735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 14439735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 14539735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 14639735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 14739735a3aSAndre Przywara ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 14839735a3aSAndre Przywara 14939735a3aSAndre Przywara #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 15039735a3aSAndre Przywara 15139735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 15239735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 15339735a3aSAndre Przywara #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 15439735a3aSAndre Przywara 1552a2f3e26SChristoffer Dall /* Device Control API: ARM VGIC */ 1562a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 1572a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 1582a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 1592a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 1602a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 1612a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 1622a2f3e26SChristoffer Dall #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 163a98f26f1SMarc Zyngier #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 164065c0034SEric Auger #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 165065c0034SEric Auger #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 1662a2f3e26SChristoffer Dall 16754f81d0eSMarc Zyngier /* KVM_IRQ_LINE irq field index values */ 16854f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_SHIFT 24 16954f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_MASK 0xff 17054f81d0eSMarc Zyngier #define KVM_ARM_IRQ_VCPU_SHIFT 16 17154f81d0eSMarc Zyngier #define KVM_ARM_IRQ_VCPU_MASK 0xff 17254f81d0eSMarc Zyngier #define KVM_ARM_IRQ_NUM_SHIFT 0 17354f81d0eSMarc Zyngier #define KVM_ARM_IRQ_NUM_MASK 0xffff 17454f81d0eSMarc Zyngier 17554f81d0eSMarc Zyngier /* irq_type field */ 17654f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_CPU 0 17754f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_SPI 1 17854f81d0eSMarc Zyngier #define KVM_ARM_IRQ_TYPE_PPI 2 17954f81d0eSMarc Zyngier 18054f81d0eSMarc Zyngier /* out-of-kernel GIC cpu interrupt injection irq_number field */ 18154f81d0eSMarc Zyngier #define KVM_ARM_IRQ_CPU_IRQ 0 18254f81d0eSMarc Zyngier #define KVM_ARM_IRQ_CPU_FIQ 1 18354f81d0eSMarc Zyngier 18454f81d0eSMarc Zyngier /* Highest supported SPI, from VGIC_NR_IRQS */ 18554f81d0eSMarc Zyngier #define KVM_ARM_IRQ_GIC_MAX 127 18654f81d0eSMarc Zyngier 187dcd2e40cSMarc Zyngier /* PSCI interface */ 188dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_BASE 0x95c1ba5e 189dcd2e40cSMarc Zyngier #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 190dcd2e40cSMarc Zyngier 191dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 192dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 193dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 194dcd2e40cSMarc Zyngier #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 195dcd2e40cSMarc Zyngier 1967d0f84aaSAnup Patel #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 1977d0f84aaSAnup Patel #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 1987d0f84aaSAnup Patel #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 1997d0f84aaSAnup Patel #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 200dcd2e40cSMarc Zyngier 20154f81d0eSMarc Zyngier #endif 20254f81d0eSMarc Zyngier 20354f81d0eSMarc Zyngier #endif /* __ARM_KVM_H__ */ 204