1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/traps.h 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 */ 7 #ifndef __ASM_TRAP_H 8 #define __ASM_TRAP_H 9 10 #include <linux/list.h> 11 #include <asm/esr.h> 12 #include <asm/sections.h> 13 14 struct pt_regs; 15 16 struct undef_hook { 17 struct list_head node; 18 u32 instr_mask; 19 u32 instr_val; 20 u64 pstate_mask; 21 u64 pstate_val; 22 int (*fn)(struct pt_regs *regs, u32 instr); 23 }; 24 25 void register_undef_hook(struct undef_hook *hook); 26 void unregister_undef_hook(struct undef_hook *hook); 27 void force_signal_inject(int signal, int code, unsigned long address); 28 void arm64_notify_segfault(unsigned long addr); 29 void arm64_force_sig_fault(int signo, int code, void __user *addr, const char *str); 30 void arm64_force_sig_mceerr(int code, void __user *addr, short lsb, const char *str); 31 void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr, const char *str); 32 33 /* 34 * Move regs->pc to next instruction and do necessary setup before it 35 * is executed. 36 */ 37 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size); 38 39 static inline int __in_irqentry_text(unsigned long ptr) 40 { 41 return ptr >= (unsigned long)&__irqentry_text_start && 42 ptr < (unsigned long)&__irqentry_text_end; 43 } 44 45 static inline int in_exception_text(unsigned long ptr) 46 { 47 int in; 48 49 in = ptr >= (unsigned long)&__exception_text_start && 50 ptr < (unsigned long)&__exception_text_end; 51 52 return in ? : __in_irqentry_text(ptr); 53 } 54 55 static inline int in_entry_text(unsigned long ptr) 56 { 57 return ptr >= (unsigned long)&__entry_text_start && 58 ptr < (unsigned long)&__entry_text_end; 59 } 60 61 /* 62 * CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit 63 * to indicate whether this ESR has a RAS encoding. CPUs without this feature 64 * have a ISS-Valid bit in the same position. 65 * If this bit is set, we know its not a RAS SError. 66 * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS 67 * errors share the same encoding as an all-zeros encoding from a CPU that 68 * doesn't support RAS. 69 */ 70 static inline bool arm64_is_ras_serror(u32 esr) 71 { 72 WARN_ON(preemptible()); 73 74 if (esr & ESR_ELx_IDS) 75 return false; 76 77 if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN)) 78 return true; 79 else 80 return false; 81 } 82 83 /* 84 * Return the AET bits from a RAS SError's ESR. 85 * 86 * It is implementation defined whether Uncategorized errors are containable. 87 * We treat them as Uncontainable. 88 * Non-RAS SError's are reported as Uncontained/Uncategorized. 89 */ 90 static inline u32 arm64_ras_serror_get_severity(u32 esr) 91 { 92 u32 aet = esr & ESR_ELx_AET; 93 94 if (!arm64_is_ras_serror(esr)) { 95 /* Not a RAS error, we can't interpret the ESR. */ 96 return ESR_ELx_AET_UC; 97 } 98 99 /* 100 * AET is RES0 if 'the value returned in the DFSC field is not 101 * [ESR_ELx_FSC_SERROR]' 102 */ 103 if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) { 104 /* No severity information : Uncategorized */ 105 return ESR_ELx_AET_UC; 106 } 107 108 return aet; 109 } 110 111 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr); 112 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr); 113 #endif 114