1 /* 2 * Based on arch/arm/include/asm/traps.h 3 * 4 * Copyright (C) 2012 ARM Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 #ifndef __ASM_TRAP_H 19 #define __ASM_TRAP_H 20 21 #include <linux/list.h> 22 #include <asm/esr.h> 23 #include <asm/sections.h> 24 25 struct pt_regs; 26 27 struct undef_hook { 28 struct list_head node; 29 u32 instr_mask; 30 u32 instr_val; 31 u64 pstate_mask; 32 u64 pstate_val; 33 int (*fn)(struct pt_regs *regs, u32 instr); 34 }; 35 36 void register_undef_hook(struct undef_hook *hook); 37 void unregister_undef_hook(struct undef_hook *hook); 38 void force_signal_inject(int signal, int code, unsigned long address); 39 void arm64_notify_segfault(unsigned long addr); 40 41 /* 42 * Move regs->pc to next instruction and do necessary setup before it 43 * is executed. 44 */ 45 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size); 46 47 static inline int __in_irqentry_text(unsigned long ptr) 48 { 49 return ptr >= (unsigned long)&__irqentry_text_start && 50 ptr < (unsigned long)&__irqentry_text_end; 51 } 52 53 static inline int in_exception_text(unsigned long ptr) 54 { 55 int in; 56 57 in = ptr >= (unsigned long)&__exception_text_start && 58 ptr < (unsigned long)&__exception_text_end; 59 60 return in ? : __in_irqentry_text(ptr); 61 } 62 63 static inline int in_entry_text(unsigned long ptr) 64 { 65 return ptr >= (unsigned long)&__entry_text_start && 66 ptr < (unsigned long)&__entry_text_end; 67 } 68 69 /* 70 * CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit 71 * to indicate whether this ESR has a RAS encoding. CPUs without this feature 72 * have a ISS-Valid bit in the same position. 73 * If this bit is set, we know its not a RAS SError. 74 * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS 75 * errors share the same encoding as an all-zeros encoding from a CPU that 76 * doesn't support RAS. 77 */ 78 static inline bool arm64_is_ras_serror(u32 esr) 79 { 80 WARN_ON(preemptible()); 81 82 if (esr & ESR_ELx_IDS) 83 return false; 84 85 if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN)) 86 return true; 87 else 88 return false; 89 } 90 91 /* 92 * Return the AET bits from a RAS SError's ESR. 93 * 94 * It is implementation defined whether Uncategorized errors are containable. 95 * We treat them as Uncontainable. 96 * Non-RAS SError's are reported as Uncontained/Uncategorized. 97 */ 98 static inline u32 arm64_ras_serror_get_severity(u32 esr) 99 { 100 u32 aet = esr & ESR_ELx_AET; 101 102 if (!arm64_is_ras_serror(esr)) { 103 /* Not a RAS error, we can't interpret the ESR. */ 104 return ESR_ELx_AET_UC; 105 } 106 107 /* 108 * AET is RES0 if 'the value returned in the DFSC field is not 109 * [ESR_ELx_FSC_SERROR]' 110 */ 111 if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) { 112 /* No severity information : Uncategorized */ 113 return ESR_ELx_AET_UC; 114 } 115 116 return aet; 117 } 118 119 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr); 120 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr); 121 #endif 122