1 /* 2 * Macros for accessing system registers with older binutils. 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * Author: Catalin Marinas <catalin.marinas@arm.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __ASM_SYSREG_H 21 #define __ASM_SYSREG_H 22 23 #include <linux/stringify.h> 24 25 /* 26 * ARMv8 ARM reserves the following encoding for system registers: 27 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 28 * C5.2, version:ARM DDI 0487A.f) 29 * [20-19] : Op0 30 * [18-16] : Op1 31 * [15-12] : CRn 32 * [11-8] : CRm 33 * [7-5] : Op2 34 */ 35 #define Op0_shift 19 36 #define Op0_mask 0x3 37 #define Op1_shift 16 38 #define Op1_mask 0x7 39 #define CRn_shift 12 40 #define CRn_mask 0xf 41 #define CRm_shift 8 42 #define CRm_mask 0xf 43 #define Op2_shift 5 44 #define Op2_mask 0x7 45 46 #define sys_reg(op0, op1, crn, crm, op2) \ 47 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 48 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 49 ((op2) << Op2_shift)) 50 51 #define sys_insn sys_reg 52 53 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 54 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 55 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 56 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 57 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 58 59 #ifndef CONFIG_BROKEN_GAS_INST 60 61 #ifdef __ASSEMBLY__ 62 #define __emit_inst(x) .inst (x) 63 #else 64 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 65 #endif 66 67 #else /* CONFIG_BROKEN_GAS_INST */ 68 69 #ifndef CONFIG_CPU_BIG_ENDIAN 70 #define __INSTR_BSWAP(x) (x) 71 #else /* CONFIG_CPU_BIG_ENDIAN */ 72 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 73 (((x) << 8) & 0x00ff0000) | \ 74 (((x) >> 8) & 0x0000ff00) | \ 75 (((x) >> 24) & 0x000000ff)) 76 #endif /* CONFIG_CPU_BIG_ENDIAN */ 77 78 #ifdef __ASSEMBLY__ 79 #define __emit_inst(x) .long __INSTR_BSWAP(x) 80 #else /* __ASSEMBLY__ */ 81 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 82 #endif /* __ASSEMBLY__ */ 83 84 #endif /* CONFIG_BROKEN_GAS_INST */ 85 86 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4) 87 #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3) 88 89 #define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \ 90 (!!x)<<8 | 0x1f) 91 #define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \ 92 (!!x)<<8 | 0x1f) 93 94 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 95 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 96 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 97 98 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 99 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 100 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 101 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 102 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 103 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 104 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 105 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 106 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 107 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 108 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 109 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 110 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 111 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 112 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 113 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 114 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 115 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 116 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 117 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 118 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 119 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 120 121 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 122 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 123 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 124 125 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 126 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 127 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 128 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 129 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 130 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 131 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 132 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 133 134 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 135 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 136 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 137 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 138 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 139 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 140 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 141 142 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 143 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 144 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 145 146 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 147 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 148 149 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 150 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 151 152 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 153 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 154 155 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 156 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 157 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 158 159 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 160 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 161 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 162 163 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 164 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 165 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 166 167 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 168 169 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 170 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 171 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 172 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 173 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 174 175 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 176 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 177 178 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 179 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 180 181 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 182 183 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 184 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 185 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 186 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 187 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 188 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 189 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 190 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 191 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 192 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 193 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 194 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 195 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 196 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 197 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 198 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 199 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 200 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 201 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 202 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 203 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 204 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 205 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 206 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 207 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 208 209 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 210 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 211 212 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 213 214 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 215 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 216 217 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 218 219 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 220 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 221 222 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 223 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 224 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 225 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 226 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 227 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 228 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 229 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 230 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 231 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 232 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 233 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 234 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 235 236 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 237 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 238 239 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 240 241 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 242 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 243 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 244 245 #define __PMEV_op2(n) ((n) & 0x7) 246 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 247 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 248 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 249 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 250 251 #define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7) 252 253 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 254 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 255 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 256 257 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 258 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 259 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 260 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 261 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 262 263 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 264 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 265 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 266 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 267 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 268 269 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 270 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 271 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 272 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 273 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 274 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 275 #define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5) 276 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 277 278 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 279 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 280 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 281 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 282 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 283 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 284 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 285 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 286 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 287 288 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 289 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 290 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 291 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 292 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 293 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 294 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 295 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 296 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 297 298 /* Common SCTLR_ELx flags. */ 299 #define SCTLR_ELx_EE (1 << 25) 300 #define SCTLR_ELx_I (1 << 12) 301 #define SCTLR_ELx_SA (1 << 3) 302 #define SCTLR_ELx_C (1 << 2) 303 #define SCTLR_ELx_A (1 << 1) 304 #define SCTLR_ELx_M 1 305 306 #define SCTLR_EL2_RES1 ((1 << 4) | (1 << 5) | (1 << 11) | (1 << 16) | \ 307 (1 << 18) | (1 << 22) | (1 << 23) | (1 << 28) | \ 308 (1 << 29)) 309 310 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 311 SCTLR_ELx_SA | SCTLR_ELx_I) 312 313 /* SCTLR_EL1 specific flags. */ 314 #define SCTLR_EL1_UCI (1 << 26) 315 #define SCTLR_EL1_SPAN (1 << 23) 316 #define SCTLR_EL1_UCT (1 << 15) 317 #define SCTLR_EL1_SED (1 << 8) 318 #define SCTLR_EL1_CP15BEN (1 << 5) 319 320 /* id_aa64isar0 */ 321 #define ID_AA64ISAR0_RDM_SHIFT 28 322 #define ID_AA64ISAR0_ATOMICS_SHIFT 20 323 #define ID_AA64ISAR0_CRC32_SHIFT 16 324 #define ID_AA64ISAR0_SHA2_SHIFT 12 325 #define ID_AA64ISAR0_SHA1_SHIFT 8 326 #define ID_AA64ISAR0_AES_SHIFT 4 327 328 /* id_aa64isar1 */ 329 #define ID_AA64ISAR1_LRCPC_SHIFT 20 330 #define ID_AA64ISAR1_FCMA_SHIFT 16 331 #define ID_AA64ISAR1_JSCVT_SHIFT 12 332 #define ID_AA64ISAR1_DPB_SHIFT 0 333 334 /* id_aa64pfr0 */ 335 #define ID_AA64PFR0_GIC_SHIFT 24 336 #define ID_AA64PFR0_ASIMD_SHIFT 20 337 #define ID_AA64PFR0_FP_SHIFT 16 338 #define ID_AA64PFR0_EL3_SHIFT 12 339 #define ID_AA64PFR0_EL2_SHIFT 8 340 #define ID_AA64PFR0_EL1_SHIFT 4 341 #define ID_AA64PFR0_EL0_SHIFT 0 342 343 #define ID_AA64PFR0_FP_NI 0xf 344 #define ID_AA64PFR0_FP_SUPPORTED 0x0 345 #define ID_AA64PFR0_ASIMD_NI 0xf 346 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 347 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 348 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 349 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 350 351 /* id_aa64mmfr0 */ 352 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 353 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 354 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 355 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 356 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 357 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 358 #define ID_AA64MMFR0_ASID_SHIFT 4 359 #define ID_AA64MMFR0_PARANGE_SHIFT 0 360 361 #define ID_AA64MMFR0_TGRAN4_NI 0xf 362 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 363 #define ID_AA64MMFR0_TGRAN64_NI 0xf 364 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 365 #define ID_AA64MMFR0_TGRAN16_NI 0x0 366 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 367 368 /* id_aa64mmfr1 */ 369 #define ID_AA64MMFR1_PAN_SHIFT 20 370 #define ID_AA64MMFR1_LOR_SHIFT 16 371 #define ID_AA64MMFR1_HPD_SHIFT 12 372 #define ID_AA64MMFR1_VHE_SHIFT 8 373 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 374 #define ID_AA64MMFR1_HADBS_SHIFT 0 375 376 #define ID_AA64MMFR1_VMIDBITS_8 0 377 #define ID_AA64MMFR1_VMIDBITS_16 2 378 379 /* id_aa64mmfr2 */ 380 #define ID_AA64MMFR2_LVA_SHIFT 16 381 #define ID_AA64MMFR2_IESB_SHIFT 12 382 #define ID_AA64MMFR2_LSM_SHIFT 8 383 #define ID_AA64MMFR2_UAO_SHIFT 4 384 #define ID_AA64MMFR2_CNP_SHIFT 0 385 386 /* id_aa64dfr0 */ 387 #define ID_AA64DFR0_PMSVER_SHIFT 32 388 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 389 #define ID_AA64DFR0_WRPS_SHIFT 20 390 #define ID_AA64DFR0_BRPS_SHIFT 12 391 #define ID_AA64DFR0_PMUVER_SHIFT 8 392 #define ID_AA64DFR0_TRACEVER_SHIFT 4 393 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 394 395 #define ID_ISAR5_RDM_SHIFT 24 396 #define ID_ISAR5_CRC32_SHIFT 16 397 #define ID_ISAR5_SHA2_SHIFT 12 398 #define ID_ISAR5_SHA1_SHIFT 8 399 #define ID_ISAR5_AES_SHIFT 4 400 #define ID_ISAR5_SEVL_SHIFT 0 401 402 #define MVFR0_FPROUND_SHIFT 28 403 #define MVFR0_FPSHVEC_SHIFT 24 404 #define MVFR0_FPSQRT_SHIFT 20 405 #define MVFR0_FPDIVIDE_SHIFT 16 406 #define MVFR0_FPTRAP_SHIFT 12 407 #define MVFR0_FPDP_SHIFT 8 408 #define MVFR0_FPSP_SHIFT 4 409 #define MVFR0_SIMD_SHIFT 0 410 411 #define MVFR1_SIMDFMAC_SHIFT 28 412 #define MVFR1_FPHP_SHIFT 24 413 #define MVFR1_SIMDHP_SHIFT 20 414 #define MVFR1_SIMDSP_SHIFT 16 415 #define MVFR1_SIMDINT_SHIFT 12 416 #define MVFR1_SIMDLS_SHIFT 8 417 #define MVFR1_FPDNAN_SHIFT 4 418 #define MVFR1_FPFTZ_SHIFT 0 419 420 421 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 422 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 423 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 424 425 #define ID_AA64MMFR0_TGRAN4_NI 0xf 426 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 427 #define ID_AA64MMFR0_TGRAN64_NI 0xf 428 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 429 #define ID_AA64MMFR0_TGRAN16_NI 0x0 430 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 431 432 #if defined(CONFIG_ARM64_4K_PAGES) 433 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 434 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED 435 #elif defined(CONFIG_ARM64_16K_PAGES) 436 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 437 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED 438 #elif defined(CONFIG_ARM64_64K_PAGES) 439 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 440 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED 441 #endif 442 443 444 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 445 #define SYS_MPIDR_SAFE_VAL (1UL << 31) 446 447 #ifdef __ASSEMBLY__ 448 449 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 450 .equ .L__reg_num_x\num, \num 451 .endr 452 .equ .L__reg_num_xzr, 31 453 454 .macro mrs_s, rt, sreg 455 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 456 .endm 457 458 .macro msr_s, sreg, rt 459 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 460 .endm 461 462 #else 463 464 #include <linux/types.h> 465 466 asm( 467 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" 468 " .equ .L__reg_num_x\\num, \\num\n" 469 " .endr\n" 470 " .equ .L__reg_num_xzr, 31\n" 471 "\n" 472 " .macro mrs_s, rt, sreg\n" 473 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) 474 " .endm\n" 475 "\n" 476 " .macro msr_s, sreg, rt\n" 477 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) 478 " .endm\n" 479 ); 480 481 /* 482 * Unlike read_cpuid, calls to read_sysreg are never expected to be 483 * optimized away or replaced with synthetic values. 484 */ 485 #define read_sysreg(r) ({ \ 486 u64 __val; \ 487 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 488 __val; \ 489 }) 490 491 /* 492 * The "Z" constraint normally means a zero immediate, but when combined with 493 * the "%x0" template means XZR. 494 */ 495 #define write_sysreg(v, r) do { \ 496 u64 __val = (u64)(v); \ 497 asm volatile("msr " __stringify(r) ", %x0" \ 498 : : "rZ" (__val)); \ 499 } while (0) 500 501 /* 502 * For registers without architectural names, or simply unsupported by 503 * GAS. 504 */ 505 #define read_sysreg_s(r) ({ \ 506 u64 __val; \ 507 asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \ 508 __val; \ 509 }) 510 511 #define write_sysreg_s(v, r) do { \ 512 u64 __val = (u64)(v); \ 513 asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \ 514 } while (0) 515 516 static inline void config_sctlr_el1(u32 clear, u32 set) 517 { 518 u32 val; 519 520 val = read_sysreg(sctlr_el1); 521 val &= ~clear; 522 val |= set; 523 write_sysreg(val, sctlr_el1); 524 } 525 526 #endif 527 528 #endif /* __ASM_SYSREG_H */ 529