1 /* 2 * Macros for accessing system registers with older binutils. 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * Author: Catalin Marinas <catalin.marinas@arm.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __ASM_SYSREG_H 21 #define __ASM_SYSREG_H 22 23 #include <asm/opcodes.h> 24 25 #define SCTLR_EL1_CP15BEN (0x1 << 5) 26 #define SCTLR_EL1_SED (0x1 << 8) 27 28 /* 29 * ARMv8 ARM reserves the following encoding for system registers: 30 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 31 * C5.2, version:ARM DDI 0487A.f) 32 * [20-19] : Op0 33 * [18-16] : Op1 34 * [15-12] : CRn 35 * [11-8] : CRm 36 * [7-5] : Op2 37 */ 38 #define sys_reg(op0, op1, crn, crm, op2) \ 39 ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5)) 40 41 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4) 42 #define SCTLR_EL1_SPAN (1 << 23) 43 44 #define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\ 45 (!!x)<<8 | 0x1f) 46 47 #ifdef __ASSEMBLY__ 48 49 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 50 .equ __reg_num_x\num, \num 51 .endr 52 .equ __reg_num_xzr, 31 53 54 .macro mrs_s, rt, sreg 55 .inst 0xd5200000|(\sreg)|(__reg_num_\rt) 56 .endm 57 58 .macro msr_s, sreg, rt 59 .inst 0xd5000000|(\sreg)|(__reg_num_\rt) 60 .endm 61 62 #else 63 64 asm( 65 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" 66 " .equ __reg_num_x\\num, \\num\n" 67 " .endr\n" 68 " .equ __reg_num_xzr, 31\n" 69 "\n" 70 " .macro mrs_s, rt, sreg\n" 71 " .inst 0xd5200000|(\\sreg)|(__reg_num_\\rt)\n" 72 " .endm\n" 73 "\n" 74 " .macro msr_s, sreg, rt\n" 75 " .inst 0xd5000000|(\\sreg)|(__reg_num_\\rt)\n" 76 " .endm\n" 77 ); 78 79 static inline void config_sctlr_el1(u32 clear, u32 set) 80 { 81 u32 val; 82 83 asm volatile("mrs %0, sctlr_el1" : "=r" (val)); 84 val &= ~clear; 85 val |= set; 86 asm volatile("msr sctlr_el1, %0" : : "r" (val)); 87 } 88 #endif 89 90 #endif /* __ASM_SYSREG_H */ 91