1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #ifndef __ASM_SYSREG_H 10 #define __ASM_SYSREG_H 11 12 #include <linux/bits.h> 13 #include <linux/stringify.h> 14 15 /* 16 * ARMv8 ARM reserves the following encoding for system registers: 17 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 18 * C5.2, version:ARM DDI 0487A.f) 19 * [20-19] : Op0 20 * [18-16] : Op1 21 * [15-12] : CRn 22 * [11-8] : CRm 23 * [7-5] : Op2 24 */ 25 #define Op0_shift 19 26 #define Op0_mask 0x3 27 #define Op1_shift 16 28 #define Op1_mask 0x7 29 #define CRn_shift 12 30 #define CRn_mask 0xf 31 #define CRm_shift 8 32 #define CRm_mask 0xf 33 #define Op2_shift 5 34 #define Op2_mask 0x7 35 36 #define sys_reg(op0, op1, crn, crm, op2) \ 37 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 38 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 39 ((op2) << Op2_shift)) 40 41 #define sys_insn sys_reg 42 43 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 44 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 45 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 46 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 47 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 48 49 #ifndef CONFIG_BROKEN_GAS_INST 50 51 #ifdef __ASSEMBLY__ 52 // The space separator is omitted so that __emit_inst(x) can be parsed as 53 // either an assembler directive or an assembler macro argument. 54 #define __emit_inst(x) .inst(x) 55 #else 56 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 57 #endif 58 59 #else /* CONFIG_BROKEN_GAS_INST */ 60 61 #ifndef CONFIG_CPU_BIG_ENDIAN 62 #define __INSTR_BSWAP(x) (x) 63 #else /* CONFIG_CPU_BIG_ENDIAN */ 64 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 65 (((x) << 8) & 0x00ff0000) | \ 66 (((x) >> 8) & 0x0000ff00) | \ 67 (((x) >> 24) & 0x000000ff)) 68 #endif /* CONFIG_CPU_BIG_ENDIAN */ 69 70 #ifdef __ASSEMBLY__ 71 #define __emit_inst(x) .long __INSTR_BSWAP(x) 72 #else /* __ASSEMBLY__ */ 73 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 74 #endif /* __ASSEMBLY__ */ 75 76 #endif /* CONFIG_BROKEN_GAS_INST */ 77 78 /* 79 * Instructions for modifying PSTATE fields. 80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 81 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 82 * for accessing PSTATE fields have the following encoding: 83 * Op0 = 0, CRn = 4 84 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 85 * CRm = Imm4 for the instruction. 86 * Rt = 0x1f 87 */ 88 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 89 #define PSTATE_Imm_shift CRm_shift 90 91 #define PSTATE_PAN pstate_field(0, 4) 92 #define PSTATE_UAO pstate_field(0, 3) 93 #define PSTATE_SSBS pstate_field(3, 1) 94 95 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) 96 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) 97 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) 98 99 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ 100 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) 101 102 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) 103 104 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 105 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 106 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 107 108 /* 109 * System registers, organised loosely by encoding but grouped together 110 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. 111 */ 112 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 113 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 114 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 115 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 116 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 117 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 118 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 119 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 120 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 121 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 122 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 123 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 124 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 125 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 126 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 127 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 128 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 129 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 130 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 131 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 132 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 133 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 134 135 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 136 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 137 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 138 139 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 140 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 141 #define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) 142 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 143 #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5) 144 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 145 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 146 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 147 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 148 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 149 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 150 #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) 151 152 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 153 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 154 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 155 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 156 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 157 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 158 #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) 159 160 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 161 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 162 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 163 164 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 165 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 166 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) 167 168 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 169 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 170 171 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 172 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 173 174 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 175 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 176 177 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 178 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 179 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 180 181 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 182 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 183 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 184 185 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) 186 187 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 188 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 189 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 190 191 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 192 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 193 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 194 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 195 196 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 197 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 198 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 199 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 200 201 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 202 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 203 204 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) 205 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) 206 207 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 208 209 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 210 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 211 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 212 213 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 214 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 215 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 216 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 217 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 218 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 219 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 220 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 221 222 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 223 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 224 225 #define SYS_PAR_EL1_F BIT(0) 226 #define SYS_PAR_EL1_FST GENMASK(6, 1) 227 228 /*** Statistical Profiling Extension ***/ 229 /* ID registers */ 230 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 231 #define SYS_PMSIDR_EL1_FE_SHIFT 0 232 #define SYS_PMSIDR_EL1_FT_SHIFT 1 233 #define SYS_PMSIDR_EL1_FL_SHIFT 2 234 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 235 #define SYS_PMSIDR_EL1_LDS_SHIFT 4 236 #define SYS_PMSIDR_EL1_ERND_SHIFT 5 237 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 238 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 239 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 240 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 241 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 242 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 243 244 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 245 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 246 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 247 #define SYS_PMBIDR_EL1_P_SHIFT 4 248 #define SYS_PMBIDR_EL1_F_SHIFT 5 249 250 /* Sampling controls */ 251 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 252 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0 253 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1 254 #define SYS_PMSCR_EL1_CX_SHIFT 3 255 #define SYS_PMSCR_EL1_PA_SHIFT 4 256 #define SYS_PMSCR_EL1_TS_SHIFT 5 257 #define SYS_PMSCR_EL1_PCT_SHIFT 6 258 259 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 260 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 261 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1 262 #define SYS_PMSCR_EL2_CX_SHIFT 3 263 #define SYS_PMSCR_EL2_PA_SHIFT 4 264 #define SYS_PMSCR_EL2_TS_SHIFT 5 265 #define SYS_PMSCR_EL2_PCT_SHIFT 6 266 267 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 268 269 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 270 #define SYS_PMSIRR_EL1_RND_SHIFT 0 271 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 272 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 273 274 /* Filtering controls */ 275 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 276 #define SYS_PMSFCR_EL1_FE_SHIFT 0 277 #define SYS_PMSFCR_EL1_FT_SHIFT 1 278 #define SYS_PMSFCR_EL1_FL_SHIFT 2 279 #define SYS_PMSFCR_EL1_B_SHIFT 16 280 #define SYS_PMSFCR_EL1_LD_SHIFT 17 281 #define SYS_PMSFCR_EL1_ST_SHIFT 18 282 283 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 284 #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL 285 286 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 287 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 288 289 /* Buffer controls */ 290 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 291 #define SYS_PMBLIMITR_EL1_E_SHIFT 0 292 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1 293 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 294 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 295 296 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 297 298 /* Buffer error reporting */ 299 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 300 #define SYS_PMBSR_EL1_COLL_SHIFT 16 301 #define SYS_PMBSR_EL1_S_SHIFT 17 302 #define SYS_PMBSR_EL1_EA_SHIFT 18 303 #define SYS_PMBSR_EL1_DL_SHIFT 19 304 #define SYS_PMBSR_EL1_EC_SHIFT 26 305 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL 306 307 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 308 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 309 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 310 311 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 312 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 313 314 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 315 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 316 317 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 318 319 /*** End of Statistical Profiling Extension ***/ 320 321 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 322 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 323 324 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 325 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 326 327 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) 328 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) 329 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) 330 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) 331 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) 332 333 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 334 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 335 336 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 337 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 338 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 339 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 340 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 341 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 342 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 343 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 344 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 345 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 346 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 347 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 348 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 349 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 350 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 351 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 352 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 353 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 354 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 355 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 356 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 357 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 358 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 359 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 360 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 361 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 362 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 363 364 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 365 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 366 367 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 368 369 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) 370 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 371 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 372 373 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 374 375 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 376 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 377 378 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) 379 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) 380 381 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 382 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 383 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 384 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 385 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 386 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 387 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 388 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 389 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 390 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 391 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 392 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 393 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 394 395 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 396 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 397 398 /* Definitions for system register interface to AMU for ARMv8.4 onwards */ 399 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) 400 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) 401 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) 402 #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) 403 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) 404 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) 405 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) 406 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) 407 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) 408 409 /* 410 * Group 0 of activity monitors (architected): 411 * op0 op1 CRn CRm op2 412 * Counter: 11 011 1101 010:n<3> n<2:0> 413 * Type: 11 011 1101 011:n<3> n<2:0> 414 * n: 0-15 415 * 416 * Group 1 of activity monitors (auxiliary): 417 * op0 op1 CRn CRm op2 418 * Counter: 11 011 1101 110:n<3> n<2:0> 419 * Type: 11 011 1101 111:n<3> n<2:0> 420 * n: 0-15 421 */ 422 423 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) 424 #define SYS_AMEVTYPE0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) 425 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) 426 #define SYS_AMEVTYPE1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) 427 428 /* AMU v1: Fixed (architecturally defined) activity monitors */ 429 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) 430 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) 431 #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) 432 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) 433 434 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 435 436 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 437 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 438 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 439 440 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) 441 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) 442 443 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 444 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 445 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 446 447 #define __PMEV_op2(n) ((n) & 0x7) 448 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 449 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 450 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 451 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 452 453 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) 454 455 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 456 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 457 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) 458 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) 459 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 460 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) 461 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 462 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 463 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) 464 465 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 466 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 467 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 468 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 469 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 470 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 471 472 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 473 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 474 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 475 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 476 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 477 478 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 479 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 480 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 481 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 482 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 483 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 484 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 485 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 486 487 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 488 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 489 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 490 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 491 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 492 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 493 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 494 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 495 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 496 497 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 498 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 499 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 500 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 501 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 502 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 503 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 504 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 505 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 506 507 /* VHE encodings for architectural EL0/1 system registers */ 508 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) 509 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) 510 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) 511 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) 512 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) 513 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) 514 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) 515 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) 516 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) 517 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) 518 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) 519 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) 520 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) 521 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) 522 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) 523 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) 524 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) 525 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) 526 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) 527 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) 528 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) 529 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) 530 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) 531 532 /* Common SCTLR_ELx flags. */ 533 #define SCTLR_ELx_DSSBS (BIT(44)) 534 #define SCTLR_ELx_ENIA (BIT(31)) 535 #define SCTLR_ELx_ENIB (BIT(30)) 536 #define SCTLR_ELx_ENDA (BIT(27)) 537 #define SCTLR_ELx_EE (BIT(25)) 538 #define SCTLR_ELx_IESB (BIT(21)) 539 #define SCTLR_ELx_WXN (BIT(19)) 540 #define SCTLR_ELx_ENDB (BIT(13)) 541 #define SCTLR_ELx_I (BIT(12)) 542 #define SCTLR_ELx_SA (BIT(3)) 543 #define SCTLR_ELx_C (BIT(2)) 544 #define SCTLR_ELx_A (BIT(1)) 545 #define SCTLR_ELx_M (BIT(0)) 546 547 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 548 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB) 549 550 /* SCTLR_EL2 specific flags. */ 551 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 552 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 553 (BIT(29))) 554 555 #ifdef CONFIG_CPU_BIG_ENDIAN 556 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 557 #else 558 #define ENDIAN_SET_EL2 0 559 #endif 560 561 /* SCTLR_EL1 specific flags. */ 562 #define SCTLR_EL1_BT1 (BIT(36)) 563 #define SCTLR_EL1_BT0 (BIT(35)) 564 #define SCTLR_EL1_UCI (BIT(26)) 565 #define SCTLR_EL1_E0E (BIT(24)) 566 #define SCTLR_EL1_SPAN (BIT(23)) 567 #define SCTLR_EL1_NTWE (BIT(18)) 568 #define SCTLR_EL1_NTWI (BIT(16)) 569 #define SCTLR_EL1_UCT (BIT(15)) 570 #define SCTLR_EL1_DZE (BIT(14)) 571 #define SCTLR_EL1_UMA (BIT(9)) 572 #define SCTLR_EL1_SED (BIT(8)) 573 #define SCTLR_EL1_ITD (BIT(7)) 574 #define SCTLR_EL1_CP15BEN (BIT(5)) 575 #define SCTLR_EL1_SA0 (BIT(4)) 576 577 #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \ 578 (BIT(29))) 579 580 #ifdef CONFIG_CPU_BIG_ENDIAN 581 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 582 #else 583 #define ENDIAN_SET_EL1 0 584 #endif 585 586 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\ 587 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\ 588 SCTLR_EL1_DZE | SCTLR_EL1_UCT |\ 589 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\ 590 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1) 591 592 /* MAIR_ELx memory attributes (used by Linux) */ 593 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) 594 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) 595 #define MAIR_ATTR_DEVICE_GRE UL(0x0c) 596 #define MAIR_ATTR_NORMAL_NC UL(0x44) 597 #define MAIR_ATTR_NORMAL_WT UL(0xbb) 598 #define MAIR_ATTR_NORMAL UL(0xff) 599 #define MAIR_ATTR_MASK UL(0xff) 600 601 /* Position the attr at the correct index */ 602 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) 603 604 /* id_aa64isar0 */ 605 #define ID_AA64ISAR0_RNDR_SHIFT 60 606 #define ID_AA64ISAR0_TLB_SHIFT 56 607 #define ID_AA64ISAR0_TS_SHIFT 52 608 #define ID_AA64ISAR0_FHM_SHIFT 48 609 #define ID_AA64ISAR0_DP_SHIFT 44 610 #define ID_AA64ISAR0_SM4_SHIFT 40 611 #define ID_AA64ISAR0_SM3_SHIFT 36 612 #define ID_AA64ISAR0_SHA3_SHIFT 32 613 #define ID_AA64ISAR0_RDM_SHIFT 28 614 #define ID_AA64ISAR0_ATOMICS_SHIFT 20 615 #define ID_AA64ISAR0_CRC32_SHIFT 16 616 #define ID_AA64ISAR0_SHA2_SHIFT 12 617 #define ID_AA64ISAR0_SHA1_SHIFT 8 618 #define ID_AA64ISAR0_AES_SHIFT 4 619 620 /* id_aa64isar1 */ 621 #define ID_AA64ISAR1_I8MM_SHIFT 52 622 #define ID_AA64ISAR1_DGH_SHIFT 48 623 #define ID_AA64ISAR1_BF16_SHIFT 44 624 #define ID_AA64ISAR1_SPECRES_SHIFT 40 625 #define ID_AA64ISAR1_SB_SHIFT 36 626 #define ID_AA64ISAR1_FRINTTS_SHIFT 32 627 #define ID_AA64ISAR1_GPI_SHIFT 28 628 #define ID_AA64ISAR1_GPA_SHIFT 24 629 #define ID_AA64ISAR1_LRCPC_SHIFT 20 630 #define ID_AA64ISAR1_FCMA_SHIFT 16 631 #define ID_AA64ISAR1_JSCVT_SHIFT 12 632 #define ID_AA64ISAR1_API_SHIFT 8 633 #define ID_AA64ISAR1_APA_SHIFT 4 634 #define ID_AA64ISAR1_DPB_SHIFT 0 635 636 #define ID_AA64ISAR1_APA_NI 0x0 637 #define ID_AA64ISAR1_APA_ARCHITECTED 0x1 638 #define ID_AA64ISAR1_API_NI 0x0 639 #define ID_AA64ISAR1_API_IMP_DEF 0x1 640 #define ID_AA64ISAR1_GPA_NI 0x0 641 #define ID_AA64ISAR1_GPA_ARCHITECTED 0x1 642 #define ID_AA64ISAR1_GPI_NI 0x0 643 #define ID_AA64ISAR1_GPI_IMP_DEF 0x1 644 645 /* id_aa64pfr0 */ 646 #define ID_AA64PFR0_CSV3_SHIFT 60 647 #define ID_AA64PFR0_CSV2_SHIFT 56 648 #define ID_AA64PFR0_DIT_SHIFT 48 649 #define ID_AA64PFR0_AMU_SHIFT 44 650 #define ID_AA64PFR0_MPAM_SHIFT 40 651 #define ID_AA64PFR0_SEL2_SHIFT 36 652 #define ID_AA64PFR0_SVE_SHIFT 32 653 #define ID_AA64PFR0_RAS_SHIFT 28 654 #define ID_AA64PFR0_GIC_SHIFT 24 655 #define ID_AA64PFR0_ASIMD_SHIFT 20 656 #define ID_AA64PFR0_FP_SHIFT 16 657 #define ID_AA64PFR0_EL3_SHIFT 12 658 #define ID_AA64PFR0_EL2_SHIFT 8 659 #define ID_AA64PFR0_EL1_SHIFT 4 660 #define ID_AA64PFR0_EL0_SHIFT 0 661 662 #define ID_AA64PFR0_AMU 0x1 663 #define ID_AA64PFR0_SVE 0x1 664 #define ID_AA64PFR0_RAS_V1 0x1 665 #define ID_AA64PFR0_FP_NI 0xf 666 #define ID_AA64PFR0_FP_SUPPORTED 0x0 667 #define ID_AA64PFR0_ASIMD_NI 0xf 668 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 669 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 670 #define ID_AA64PFR0_EL1_32BIT_64BIT 0x2 671 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 672 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 673 674 /* id_aa64pfr1 */ 675 #define ID_AA64PFR1_MPAMFRAC_SHIFT 16 676 #define ID_AA64PFR1_RASFRAC_SHIFT 12 677 #define ID_AA64PFR1_MTE_SHIFT 8 678 #define ID_AA64PFR1_SSBS_SHIFT 4 679 #define ID_AA64PFR1_BT_SHIFT 0 680 681 #define ID_AA64PFR1_SSBS_PSTATE_NI 0 682 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 683 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 684 #define ID_AA64PFR1_BT_BTI 0x1 685 686 /* id_aa64zfr0 */ 687 #define ID_AA64ZFR0_F64MM_SHIFT 56 688 #define ID_AA64ZFR0_F32MM_SHIFT 52 689 #define ID_AA64ZFR0_I8MM_SHIFT 44 690 #define ID_AA64ZFR0_SM4_SHIFT 40 691 #define ID_AA64ZFR0_SHA3_SHIFT 32 692 #define ID_AA64ZFR0_BF16_SHIFT 20 693 #define ID_AA64ZFR0_BITPERM_SHIFT 16 694 #define ID_AA64ZFR0_AES_SHIFT 4 695 #define ID_AA64ZFR0_SVEVER_SHIFT 0 696 697 #define ID_AA64ZFR0_F64MM 0x1 698 #define ID_AA64ZFR0_F32MM 0x1 699 #define ID_AA64ZFR0_I8MM 0x1 700 #define ID_AA64ZFR0_BF16 0x1 701 #define ID_AA64ZFR0_SM4 0x1 702 #define ID_AA64ZFR0_SHA3 0x1 703 #define ID_AA64ZFR0_BITPERM 0x1 704 #define ID_AA64ZFR0_AES 0x1 705 #define ID_AA64ZFR0_AES_PMULL 0x2 706 #define ID_AA64ZFR0_SVEVER_SVE2 0x1 707 708 /* id_aa64mmfr0 */ 709 #define ID_AA64MMFR0_TGRAN4_2_SHIFT 40 710 #define ID_AA64MMFR0_TGRAN64_2_SHIFT 36 711 #define ID_AA64MMFR0_TGRAN16_2_SHIFT 32 712 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 713 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 714 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 715 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 716 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 717 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 718 #define ID_AA64MMFR0_ASID_SHIFT 4 719 #define ID_AA64MMFR0_PARANGE_SHIFT 0 720 721 #define ID_AA64MMFR0_TGRAN4_NI 0xf 722 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 723 #define ID_AA64MMFR0_TGRAN64_NI 0xf 724 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 725 #define ID_AA64MMFR0_TGRAN16_NI 0x0 726 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 727 #define ID_AA64MMFR0_PARANGE_48 0x5 728 #define ID_AA64MMFR0_PARANGE_52 0x6 729 730 #ifdef CONFIG_ARM64_PA_BITS_52 731 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 732 #else 733 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48 734 #endif 735 736 /* id_aa64mmfr1 */ 737 #define ID_AA64MMFR1_PAN_SHIFT 20 738 #define ID_AA64MMFR1_LOR_SHIFT 16 739 #define ID_AA64MMFR1_HPD_SHIFT 12 740 #define ID_AA64MMFR1_VHE_SHIFT 8 741 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 742 #define ID_AA64MMFR1_HADBS_SHIFT 0 743 744 #define ID_AA64MMFR1_VMIDBITS_8 0 745 #define ID_AA64MMFR1_VMIDBITS_16 2 746 747 /* id_aa64mmfr2 */ 748 #define ID_AA64MMFR2_E0PD_SHIFT 60 749 #define ID_AA64MMFR2_FWB_SHIFT 40 750 #define ID_AA64MMFR2_AT_SHIFT 32 751 #define ID_AA64MMFR2_LVA_SHIFT 16 752 #define ID_AA64MMFR2_IESB_SHIFT 12 753 #define ID_AA64MMFR2_LSM_SHIFT 8 754 #define ID_AA64MMFR2_UAO_SHIFT 4 755 #define ID_AA64MMFR2_CNP_SHIFT 0 756 757 /* id_aa64dfr0 */ 758 #define ID_AA64DFR0_PMSVER_SHIFT 32 759 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 760 #define ID_AA64DFR0_WRPS_SHIFT 20 761 #define ID_AA64DFR0_BRPS_SHIFT 12 762 #define ID_AA64DFR0_PMUVER_SHIFT 8 763 #define ID_AA64DFR0_TRACEVER_SHIFT 4 764 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 765 766 #define ID_AA64DFR0_PMUVER_8_0 0x1 767 #define ID_AA64DFR0_PMUVER_8_1 0x4 768 #define ID_AA64DFR0_PMUVER_8_4 0x5 769 #define ID_AA64DFR0_PMUVER_8_5 0x6 770 #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf 771 772 #define ID_DFR0_PERFMON_SHIFT 24 773 774 #define ID_DFR0_PERFMON_8_1 0x4 775 776 #define ID_ISAR4_SWP_FRAC_SHIFT 28 777 #define ID_ISAR4_PSR_M_SHIFT 24 778 #define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT 20 779 #define ID_ISAR4_BARRIER_SHIFT 16 780 #define ID_ISAR4_SMC_SHIFT 12 781 #define ID_ISAR4_WRITEBACK_SHIFT 8 782 #define ID_ISAR4_WITHSHIFTS_SHIFT 4 783 #define ID_ISAR4_UNPRIV_SHIFT 0 784 785 #define ID_DFR1_MTPMU_SHIFT 0 786 787 #define ID_ISAR0_DIVIDE_SHIFT 24 788 #define ID_ISAR0_DEBUG_SHIFT 20 789 #define ID_ISAR0_COPROC_SHIFT 16 790 #define ID_ISAR0_CMPBRANCH_SHIFT 12 791 #define ID_ISAR0_BITFIELD_SHIFT 8 792 #define ID_ISAR0_BITCOUNT_SHIFT 4 793 #define ID_ISAR0_SWAP_SHIFT 0 794 795 #define ID_ISAR5_RDM_SHIFT 24 796 #define ID_ISAR5_CRC32_SHIFT 16 797 #define ID_ISAR5_SHA2_SHIFT 12 798 #define ID_ISAR5_SHA1_SHIFT 8 799 #define ID_ISAR5_AES_SHIFT 4 800 #define ID_ISAR5_SEVL_SHIFT 0 801 802 #define ID_ISAR6_I8MM_SHIFT 24 803 #define ID_ISAR6_BF16_SHIFT 20 804 #define ID_ISAR6_SPECRES_SHIFT 16 805 #define ID_ISAR6_SB_SHIFT 12 806 #define ID_ISAR6_FHM_SHIFT 8 807 #define ID_ISAR6_DP_SHIFT 4 808 #define ID_ISAR6_JSCVT_SHIFT 0 809 810 #define ID_MMFR4_EVT_SHIFT 28 811 #define ID_MMFR4_CCIDX_SHIFT 24 812 #define ID_MMFR4_LSM_SHIFT 20 813 #define ID_MMFR4_HPDS_SHIFT 16 814 #define ID_MMFR4_CNP_SHIFT 12 815 #define ID_MMFR4_XNX_SHIFT 8 816 #define ID_MMFR4_SPECSEI_SHIFT 0 817 818 #define ID_MMFR5_ETS_SHIFT 0 819 820 #define ID_PFR0_DIT_SHIFT 24 821 #define ID_PFR0_CSV2_SHIFT 16 822 823 #define ID_PFR2_SSBS_SHIFT 4 824 #define ID_PFR2_CSV3_SHIFT 0 825 826 #define MVFR0_FPROUND_SHIFT 28 827 #define MVFR0_FPSHVEC_SHIFT 24 828 #define MVFR0_FPSQRT_SHIFT 20 829 #define MVFR0_FPDIVIDE_SHIFT 16 830 #define MVFR0_FPTRAP_SHIFT 12 831 #define MVFR0_FPDP_SHIFT 8 832 #define MVFR0_FPSP_SHIFT 4 833 #define MVFR0_SIMD_SHIFT 0 834 835 #define MVFR1_SIMDFMAC_SHIFT 28 836 #define MVFR1_FPHP_SHIFT 24 837 #define MVFR1_SIMDHP_SHIFT 20 838 #define MVFR1_SIMDSP_SHIFT 16 839 #define MVFR1_SIMDINT_SHIFT 12 840 #define MVFR1_SIMDLS_SHIFT 8 841 #define MVFR1_FPDNAN_SHIFT 4 842 #define MVFR1_FPFTZ_SHIFT 0 843 844 #define ID_PFR1_GIC_SHIFT 28 845 #define ID_PFR1_VIRT_FRAC_SHIFT 24 846 #define ID_PFR1_SEC_FRAC_SHIFT 20 847 #define ID_PFR1_GENTIMER_SHIFT 16 848 #define ID_PFR1_VIRTUALIZATION_SHIFT 12 849 #define ID_PFR1_MPROGMOD_SHIFT 8 850 #define ID_PFR1_SECURITY_SHIFT 4 851 #define ID_PFR1_PROGMOD_SHIFT 0 852 853 #if defined(CONFIG_ARM64_4K_PAGES) 854 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 855 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED 856 #elif defined(CONFIG_ARM64_16K_PAGES) 857 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 858 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED 859 #elif defined(CONFIG_ARM64_64K_PAGES) 860 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 861 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED 862 #endif 863 864 865 /* 866 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which 867 * are reserved by the SVE architecture for future expansion of the LEN 868 * field, with compatible semantics. 869 */ 870 #define ZCR_ELx_LEN_SHIFT 0 871 #define ZCR_ELx_LEN_SIZE 9 872 #define ZCR_ELx_LEN_MASK 0x1ff 873 874 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ 875 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ 876 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) 877 878 879 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 880 #define SYS_MPIDR_SAFE_VAL (BIT(31)) 881 882 #ifdef __ASSEMBLY__ 883 884 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 885 .equ .L__reg_num_x\num, \num 886 .endr 887 .equ .L__reg_num_xzr, 31 888 889 .macro mrs_s, rt, sreg 890 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 891 .endm 892 893 .macro msr_s, sreg, rt 894 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 895 .endm 896 897 #else 898 899 #include <linux/build_bug.h> 900 #include <linux/types.h> 901 902 #define __DEFINE_MRS_MSR_S_REGNUM \ 903 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \ 904 " .equ .L__reg_num_x\\num, \\num\n" \ 905 " .endr\n" \ 906 " .equ .L__reg_num_xzr, 31\n" 907 908 #define DEFINE_MRS_S \ 909 __DEFINE_MRS_MSR_S_REGNUM \ 910 " .macro mrs_s, rt, sreg\n" \ 911 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \ 912 " .endm\n" 913 914 #define DEFINE_MSR_S \ 915 __DEFINE_MRS_MSR_S_REGNUM \ 916 " .macro msr_s, sreg, rt\n" \ 917 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \ 918 " .endm\n" 919 920 #define UNDEFINE_MRS_S \ 921 " .purgem mrs_s\n" 922 923 #define UNDEFINE_MSR_S \ 924 " .purgem msr_s\n" 925 926 #define __mrs_s(v, r) \ 927 DEFINE_MRS_S \ 928 " mrs_s " v ", " __stringify(r) "\n" \ 929 UNDEFINE_MRS_S 930 931 #define __msr_s(r, v) \ 932 DEFINE_MSR_S \ 933 " msr_s " __stringify(r) ", " v "\n" \ 934 UNDEFINE_MSR_S 935 936 /* 937 * Unlike read_cpuid, calls to read_sysreg are never expected to be 938 * optimized away or replaced with synthetic values. 939 */ 940 #define read_sysreg(r) ({ \ 941 u64 __val; \ 942 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 943 __val; \ 944 }) 945 946 /* 947 * The "Z" constraint normally means a zero immediate, but when combined with 948 * the "%x0" template means XZR. 949 */ 950 #define write_sysreg(v, r) do { \ 951 u64 __val = (u64)(v); \ 952 asm volatile("msr " __stringify(r) ", %x0" \ 953 : : "rZ" (__val)); \ 954 } while (0) 955 956 /* 957 * For registers without architectural names, or simply unsupported by 958 * GAS. 959 */ 960 #define read_sysreg_s(r) ({ \ 961 u64 __val; \ 962 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ 963 __val; \ 964 }) 965 966 #define write_sysreg_s(v, r) do { \ 967 u64 __val = (u64)(v); \ 968 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ 969 } while (0) 970 971 /* 972 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 973 * set mask are set. Other bits are left as-is. 974 */ 975 #define sysreg_clear_set(sysreg, clear, set) do { \ 976 u64 __scs_val = read_sysreg(sysreg); \ 977 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 978 if (__scs_new != __scs_val) \ 979 write_sysreg(__scs_new, sysreg); \ 980 } while (0) 981 982 #endif 983 984 #endif /* __ASM_SYSREG_H */ 985