1 /* 2 * Macros for accessing system registers with older binutils. 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * Author: Catalin Marinas <catalin.marinas@arm.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __ASM_SYSREG_H 21 #define __ASM_SYSREG_H 22 23 #include <asm/opcodes.h> 24 25 /* 26 * ARMv8 ARM reserves the following encoding for system registers: 27 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 28 * C5.2, version:ARM DDI 0487A.f) 29 * [20-19] : Op0 30 * [18-16] : Op1 31 * [15-12] : CRn 32 * [11-8] : CRm 33 * [7-5] : Op2 34 */ 35 #define sys_reg(op0, op1, crn, crm, op2) \ 36 ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5)) 37 38 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 39 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 40 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 41 42 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 43 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 44 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 45 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 46 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 47 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 48 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 49 50 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 51 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 52 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 53 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 54 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 55 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 56 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 57 58 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 59 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 60 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 61 62 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 63 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 64 65 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 66 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 67 68 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 69 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 70 71 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 72 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 73 74 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 75 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 76 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 77 78 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4) 79 80 #define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\ 81 (!!x)<<8 | 0x1f) 82 83 /* SCTLR_EL1 */ 84 #define SCTLR_EL1_CP15BEN (0x1 << 5) 85 #define SCTLR_EL1_SED (0x1 << 8) 86 #define SCTLR_EL1_SPAN (0x1 << 23) 87 88 89 /* id_aa64isar0 */ 90 #define ID_AA64ISAR0_RDM_SHIFT 28 91 #define ID_AA64ISAR0_ATOMICS_SHIFT 20 92 #define ID_AA64ISAR0_CRC32_SHIFT 16 93 #define ID_AA64ISAR0_SHA2_SHIFT 12 94 #define ID_AA64ISAR0_SHA1_SHIFT 8 95 #define ID_AA64ISAR0_AES_SHIFT 4 96 97 /* id_aa64pfr0 */ 98 #define ID_AA64PFR0_GIC_SHIFT 24 99 #define ID_AA64PFR0_ASIMD_SHIFT 20 100 #define ID_AA64PFR0_FP_SHIFT 16 101 #define ID_AA64PFR0_EL3_SHIFT 12 102 #define ID_AA64PFR0_EL2_SHIFT 8 103 #define ID_AA64PFR0_EL1_SHIFT 4 104 #define ID_AA64PFR0_EL0_SHIFT 0 105 106 #define ID_AA64PFR0_FP_NI 0xf 107 #define ID_AA64PFR0_FP_SUPPORTED 0x0 108 #define ID_AA64PFR0_ASIMD_NI 0xf 109 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 110 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 111 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 112 113 /* id_aa64mmfr0 */ 114 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 115 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 116 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 117 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 118 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 119 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 120 #define ID_AA64MMFR0_ASID_SHIFT 4 121 #define ID_AA64MMFR0_PARANGE_SHIFT 0 122 123 #define ID_AA64MMFR0_TGRAN4_NI 0xf 124 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 125 #define ID_AA64MMFR0_TGRAN64_NI 0xf 126 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 127 #define ID_AA64MMFR0_TGRAN16_NI 0x0 128 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 129 130 /* id_aa64mmfr1 */ 131 #define ID_AA64MMFR1_PAN_SHIFT 20 132 #define ID_AA64MMFR1_LOR_SHIFT 16 133 #define ID_AA64MMFR1_HPD_SHIFT 12 134 #define ID_AA64MMFR1_VHE_SHIFT 8 135 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 136 #define ID_AA64MMFR1_HADBS_SHIFT 0 137 138 /* id_aa64dfr0 */ 139 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 140 #define ID_AA64DFR0_WRPS_SHIFT 20 141 #define ID_AA64DFR0_BRPS_SHIFT 12 142 #define ID_AA64DFR0_PMUVER_SHIFT 8 143 #define ID_AA64DFR0_TRACEVER_SHIFT 4 144 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 145 146 #define ID_ISAR5_RDM_SHIFT 24 147 #define ID_ISAR5_CRC32_SHIFT 16 148 #define ID_ISAR5_SHA2_SHIFT 12 149 #define ID_ISAR5_SHA1_SHIFT 8 150 #define ID_ISAR5_AES_SHIFT 4 151 #define ID_ISAR5_SEVL_SHIFT 0 152 153 #define MVFR0_FPROUND_SHIFT 28 154 #define MVFR0_FPSHVEC_SHIFT 24 155 #define MVFR0_FPSQRT_SHIFT 20 156 #define MVFR0_FPDIVIDE_SHIFT 16 157 #define MVFR0_FPTRAP_SHIFT 12 158 #define MVFR0_FPDP_SHIFT 8 159 #define MVFR0_FPSP_SHIFT 4 160 #define MVFR0_SIMD_SHIFT 0 161 162 #define MVFR1_SIMDFMAC_SHIFT 28 163 #define MVFR1_FPHP_SHIFT 24 164 #define MVFR1_SIMDHP_SHIFT 20 165 #define MVFR1_SIMDSP_SHIFT 16 166 #define MVFR1_SIMDINT_SHIFT 12 167 #define MVFR1_SIMDLS_SHIFT 8 168 #define MVFR1_FPDNAN_SHIFT 4 169 #define MVFR1_FPFTZ_SHIFT 0 170 171 172 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 173 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 174 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 175 176 #define ID_AA64MMFR0_TGRAN4_NI 0xf 177 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 178 #define ID_AA64MMFR0_TGRAN64_NI 0xf 179 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 180 #define ID_AA64MMFR0_TGRAN16_NI 0x0 181 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 182 183 #if defined(CONFIG_ARM64_4K_PAGES) 184 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 185 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED 186 #elif defined(CONFIG_ARM64_16K_PAGES) 187 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 188 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED 189 #elif defined(CONFIG_ARM64_64K_PAGES) 190 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 191 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED 192 #endif 193 194 #ifdef __ASSEMBLY__ 195 196 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 197 .equ __reg_num_x\num, \num 198 .endr 199 .equ __reg_num_xzr, 31 200 201 .macro mrs_s, rt, sreg 202 .inst 0xd5200000|(\sreg)|(__reg_num_\rt) 203 .endm 204 205 .macro msr_s, sreg, rt 206 .inst 0xd5000000|(\sreg)|(__reg_num_\rt) 207 .endm 208 209 #else 210 211 asm( 212 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" 213 " .equ __reg_num_x\\num, \\num\n" 214 " .endr\n" 215 " .equ __reg_num_xzr, 31\n" 216 "\n" 217 " .macro mrs_s, rt, sreg\n" 218 " .inst 0xd5200000|(\\sreg)|(__reg_num_\\rt)\n" 219 " .endm\n" 220 "\n" 221 " .macro msr_s, sreg, rt\n" 222 " .inst 0xd5000000|(\\sreg)|(__reg_num_\\rt)\n" 223 " .endm\n" 224 ); 225 226 static inline void config_sctlr_el1(u32 clear, u32 set) 227 { 228 u32 val; 229 230 asm volatile("mrs %0, sctlr_el1" : "=r" (val)); 231 val &= ~clear; 232 val |= set; 233 asm volatile("msr sctlr_el1, %0" : : "r" (val)); 234 } 235 #endif 236 237 #endif /* __ASM_SYSREG_H */ 238