1 /* 2 * Macros for accessing system registers with older binutils. 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * Author: Catalin Marinas <catalin.marinas@arm.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __ASM_SYSREG_H 21 #define __ASM_SYSREG_H 22 23 #include <linux/stringify.h> 24 25 /* 26 * ARMv8 ARM reserves the following encoding for system registers: 27 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 28 * C5.2, version:ARM DDI 0487A.f) 29 * [20-19] : Op0 30 * [18-16] : Op1 31 * [15-12] : CRn 32 * [11-8] : CRm 33 * [7-5] : Op2 34 */ 35 #define Op0_shift 19 36 #define Op0_mask 0x3 37 #define Op1_shift 16 38 #define Op1_mask 0x7 39 #define CRn_shift 12 40 #define CRn_mask 0xf 41 #define CRm_shift 8 42 #define CRm_mask 0xf 43 #define Op2_shift 5 44 #define Op2_mask 0x7 45 46 #define sys_reg(op0, op1, crn, crm, op2) \ 47 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 48 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 49 ((op2) << Op2_shift)) 50 51 #define sys_insn sys_reg 52 53 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 54 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 55 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 56 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 57 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 58 59 #ifndef CONFIG_BROKEN_GAS_INST 60 61 #ifdef __ASSEMBLY__ 62 #define __emit_inst(x) .inst (x) 63 #else 64 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 65 #endif 66 67 #else /* CONFIG_BROKEN_GAS_INST */ 68 69 #ifndef CONFIG_CPU_BIG_ENDIAN 70 #define __INSTR_BSWAP(x) (x) 71 #else /* CONFIG_CPU_BIG_ENDIAN */ 72 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 73 (((x) << 8) & 0x00ff0000) | \ 74 (((x) >> 8) & 0x0000ff00) | \ 75 (((x) >> 24) & 0x000000ff)) 76 #endif /* CONFIG_CPU_BIG_ENDIAN */ 77 78 #ifdef __ASSEMBLY__ 79 #define __emit_inst(x) .long __INSTR_BSWAP(x) 80 #else /* __ASSEMBLY__ */ 81 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 82 #endif /* __ASSEMBLY__ */ 83 84 #endif /* CONFIG_BROKEN_GAS_INST */ 85 86 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4) 87 #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3) 88 89 #define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \ 90 (!!x)<<8 | 0x1f) 91 #define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \ 92 (!!x)<<8 | 0x1f) 93 94 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 95 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 96 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 97 98 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 99 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 100 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 101 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 102 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 103 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 104 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 105 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 106 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 107 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 108 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 109 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 110 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 111 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 112 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 113 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 114 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 115 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 116 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 117 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 118 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 119 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 120 121 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 122 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 123 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 124 125 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 126 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 127 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 128 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 129 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 130 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 131 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 132 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 133 134 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 135 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 136 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 137 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 138 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 139 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 140 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 141 142 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 143 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 144 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 145 146 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 147 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 148 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) 149 150 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 151 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 152 153 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 154 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 155 156 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 157 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 158 159 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 160 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 161 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 162 163 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 164 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 165 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 166 167 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) 168 169 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 170 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 171 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 172 173 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 174 175 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 176 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 177 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 178 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 179 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 180 181 /*** Statistical Profiling Extension ***/ 182 /* ID registers */ 183 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 184 #define SYS_PMSIDR_EL1_FE_SHIFT 0 185 #define SYS_PMSIDR_EL1_FT_SHIFT 1 186 #define SYS_PMSIDR_EL1_FL_SHIFT 2 187 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 188 #define SYS_PMSIDR_EL1_LDS_SHIFT 4 189 #define SYS_PMSIDR_EL1_ERND_SHIFT 5 190 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 191 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 192 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 193 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 194 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 195 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 196 197 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 198 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 199 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 200 #define SYS_PMBIDR_EL1_P_SHIFT 4 201 #define SYS_PMBIDR_EL1_F_SHIFT 5 202 203 /* Sampling controls */ 204 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 205 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0 206 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1 207 #define SYS_PMSCR_EL1_CX_SHIFT 3 208 #define SYS_PMSCR_EL1_PA_SHIFT 4 209 #define SYS_PMSCR_EL1_TS_SHIFT 5 210 #define SYS_PMSCR_EL1_PCT_SHIFT 6 211 212 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 213 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 214 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1 215 #define SYS_PMSCR_EL2_CX_SHIFT 3 216 #define SYS_PMSCR_EL2_PA_SHIFT 4 217 #define SYS_PMSCR_EL2_TS_SHIFT 5 218 #define SYS_PMSCR_EL2_PCT_SHIFT 6 219 220 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 221 222 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 223 #define SYS_PMSIRR_EL1_RND_SHIFT 0 224 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 225 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 226 227 /* Filtering controls */ 228 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 229 #define SYS_PMSFCR_EL1_FE_SHIFT 0 230 #define SYS_PMSFCR_EL1_FT_SHIFT 1 231 #define SYS_PMSFCR_EL1_FL_SHIFT 2 232 #define SYS_PMSFCR_EL1_B_SHIFT 16 233 #define SYS_PMSFCR_EL1_LD_SHIFT 17 234 #define SYS_PMSFCR_EL1_ST_SHIFT 18 235 236 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 237 #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL 238 239 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 240 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 241 242 /* Buffer controls */ 243 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 244 #define SYS_PMBLIMITR_EL1_E_SHIFT 0 245 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1 246 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 247 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 248 249 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 250 251 /* Buffer error reporting */ 252 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 253 #define SYS_PMBSR_EL1_COLL_SHIFT 16 254 #define SYS_PMBSR_EL1_S_SHIFT 17 255 #define SYS_PMBSR_EL1_EA_SHIFT 18 256 #define SYS_PMBSR_EL1_DL_SHIFT 19 257 #define SYS_PMBSR_EL1_EC_SHIFT 26 258 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL 259 260 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 261 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 262 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 263 264 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 265 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 266 267 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 268 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 269 270 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 271 272 /*** End of Statistical Profiling Extension ***/ 273 274 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 275 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 276 277 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 278 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 279 280 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 281 282 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 283 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 284 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 285 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 286 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 287 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 288 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 289 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 290 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 291 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 292 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 293 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 294 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 295 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 296 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 297 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 298 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 299 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 300 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 301 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 302 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 303 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 304 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 305 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 306 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 307 308 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 309 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 310 311 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 312 313 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 314 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 315 316 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 317 318 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 319 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 320 321 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 322 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 323 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 324 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 325 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 326 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 327 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 328 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 329 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 330 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 331 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 332 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 333 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 334 335 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 336 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 337 338 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 339 340 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 341 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 342 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 343 344 #define __PMEV_op2(n) ((n) & 0x7) 345 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 346 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 347 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 348 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 349 350 #define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7) 351 352 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 353 354 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 355 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 356 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 357 358 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 359 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 360 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 361 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 362 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 363 364 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 365 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 366 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 367 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 368 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 369 370 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 371 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 372 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 373 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 374 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 375 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 376 #define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5) 377 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 378 379 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 380 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 381 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 382 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 383 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 384 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 385 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 386 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 387 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 388 389 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 390 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 391 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 392 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 393 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 394 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 395 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 396 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 397 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 398 399 /* Common SCTLR_ELx flags. */ 400 #define SCTLR_ELx_EE (1 << 25) 401 #define SCTLR_ELx_I (1 << 12) 402 #define SCTLR_ELx_SA (1 << 3) 403 #define SCTLR_ELx_C (1 << 2) 404 #define SCTLR_ELx_A (1 << 1) 405 #define SCTLR_ELx_M 1 406 407 #define SCTLR_EL2_RES1 ((1 << 4) | (1 << 5) | (1 << 11) | (1 << 16) | \ 408 (1 << 18) | (1 << 22) | (1 << 23) | (1 << 28) | \ 409 (1 << 29)) 410 411 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 412 SCTLR_ELx_SA | SCTLR_ELx_I) 413 414 /* SCTLR_EL1 specific flags. */ 415 #define SCTLR_EL1_UCI (1 << 26) 416 #define SCTLR_EL1_SPAN (1 << 23) 417 #define SCTLR_EL1_UCT (1 << 15) 418 #define SCTLR_EL1_SED (1 << 8) 419 #define SCTLR_EL1_CP15BEN (1 << 5) 420 421 /* id_aa64isar0 */ 422 #define ID_AA64ISAR0_DP_SHIFT 44 423 #define ID_AA64ISAR0_SM4_SHIFT 40 424 #define ID_AA64ISAR0_SM3_SHIFT 36 425 #define ID_AA64ISAR0_SHA3_SHIFT 32 426 #define ID_AA64ISAR0_RDM_SHIFT 28 427 #define ID_AA64ISAR0_ATOMICS_SHIFT 20 428 #define ID_AA64ISAR0_CRC32_SHIFT 16 429 #define ID_AA64ISAR0_SHA2_SHIFT 12 430 #define ID_AA64ISAR0_SHA1_SHIFT 8 431 #define ID_AA64ISAR0_AES_SHIFT 4 432 433 /* id_aa64isar1 */ 434 #define ID_AA64ISAR1_LRCPC_SHIFT 20 435 #define ID_AA64ISAR1_FCMA_SHIFT 16 436 #define ID_AA64ISAR1_JSCVT_SHIFT 12 437 #define ID_AA64ISAR1_DPB_SHIFT 0 438 439 /* id_aa64pfr0 */ 440 #define ID_AA64PFR0_SVE_SHIFT 32 441 #define ID_AA64PFR0_GIC_SHIFT 24 442 #define ID_AA64PFR0_ASIMD_SHIFT 20 443 #define ID_AA64PFR0_FP_SHIFT 16 444 #define ID_AA64PFR0_EL3_SHIFT 12 445 #define ID_AA64PFR0_EL2_SHIFT 8 446 #define ID_AA64PFR0_EL1_SHIFT 4 447 #define ID_AA64PFR0_EL0_SHIFT 0 448 449 #define ID_AA64PFR0_SVE 0x1 450 #define ID_AA64PFR0_FP_NI 0xf 451 #define ID_AA64PFR0_FP_SUPPORTED 0x0 452 #define ID_AA64PFR0_ASIMD_NI 0xf 453 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 454 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 455 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 456 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 457 458 /* id_aa64mmfr0 */ 459 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 460 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 461 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 462 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 463 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 464 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 465 #define ID_AA64MMFR0_ASID_SHIFT 4 466 #define ID_AA64MMFR0_PARANGE_SHIFT 0 467 468 #define ID_AA64MMFR0_TGRAN4_NI 0xf 469 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 470 #define ID_AA64MMFR0_TGRAN64_NI 0xf 471 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 472 #define ID_AA64MMFR0_TGRAN16_NI 0x0 473 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 474 475 /* id_aa64mmfr1 */ 476 #define ID_AA64MMFR1_PAN_SHIFT 20 477 #define ID_AA64MMFR1_LOR_SHIFT 16 478 #define ID_AA64MMFR1_HPD_SHIFT 12 479 #define ID_AA64MMFR1_VHE_SHIFT 8 480 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 481 #define ID_AA64MMFR1_HADBS_SHIFT 0 482 483 #define ID_AA64MMFR1_VMIDBITS_8 0 484 #define ID_AA64MMFR1_VMIDBITS_16 2 485 486 /* id_aa64mmfr2 */ 487 #define ID_AA64MMFR2_LVA_SHIFT 16 488 #define ID_AA64MMFR2_IESB_SHIFT 12 489 #define ID_AA64MMFR2_LSM_SHIFT 8 490 #define ID_AA64MMFR2_UAO_SHIFT 4 491 #define ID_AA64MMFR2_CNP_SHIFT 0 492 493 /* id_aa64dfr0 */ 494 #define ID_AA64DFR0_PMSVER_SHIFT 32 495 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 496 #define ID_AA64DFR0_WRPS_SHIFT 20 497 #define ID_AA64DFR0_BRPS_SHIFT 12 498 #define ID_AA64DFR0_PMUVER_SHIFT 8 499 #define ID_AA64DFR0_TRACEVER_SHIFT 4 500 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 501 502 #define ID_ISAR5_RDM_SHIFT 24 503 #define ID_ISAR5_CRC32_SHIFT 16 504 #define ID_ISAR5_SHA2_SHIFT 12 505 #define ID_ISAR5_SHA1_SHIFT 8 506 #define ID_ISAR5_AES_SHIFT 4 507 #define ID_ISAR5_SEVL_SHIFT 0 508 509 #define MVFR0_FPROUND_SHIFT 28 510 #define MVFR0_FPSHVEC_SHIFT 24 511 #define MVFR0_FPSQRT_SHIFT 20 512 #define MVFR0_FPDIVIDE_SHIFT 16 513 #define MVFR0_FPTRAP_SHIFT 12 514 #define MVFR0_FPDP_SHIFT 8 515 #define MVFR0_FPSP_SHIFT 4 516 #define MVFR0_SIMD_SHIFT 0 517 518 #define MVFR1_SIMDFMAC_SHIFT 28 519 #define MVFR1_FPHP_SHIFT 24 520 #define MVFR1_SIMDHP_SHIFT 20 521 #define MVFR1_SIMDSP_SHIFT 16 522 #define MVFR1_SIMDINT_SHIFT 12 523 #define MVFR1_SIMDLS_SHIFT 8 524 #define MVFR1_FPDNAN_SHIFT 4 525 #define MVFR1_FPFTZ_SHIFT 0 526 527 528 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 529 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 530 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 531 532 #define ID_AA64MMFR0_TGRAN4_NI 0xf 533 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 534 #define ID_AA64MMFR0_TGRAN64_NI 0xf 535 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 536 #define ID_AA64MMFR0_TGRAN16_NI 0x0 537 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 538 539 #if defined(CONFIG_ARM64_4K_PAGES) 540 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 541 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED 542 #elif defined(CONFIG_ARM64_16K_PAGES) 543 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 544 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED 545 #elif defined(CONFIG_ARM64_64K_PAGES) 546 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 547 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED 548 #endif 549 550 551 /* 552 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which 553 * are reserved by the SVE architecture for future expansion of the LEN 554 * field, with compatible semantics. 555 */ 556 #define ZCR_ELx_LEN_SHIFT 0 557 #define ZCR_ELx_LEN_SIZE 9 558 #define ZCR_ELx_LEN_MASK 0x1ff 559 560 #define CPACR_EL1_ZEN_EL1EN (1 << 16) /* enable EL1 access */ 561 #define CPACR_EL1_ZEN_EL0EN (1 << 17) /* enable EL0 access, if EL1EN set */ 562 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) 563 564 565 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 566 #define SYS_MPIDR_SAFE_VAL (1UL << 31) 567 568 #ifdef __ASSEMBLY__ 569 570 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 571 .equ .L__reg_num_x\num, \num 572 .endr 573 .equ .L__reg_num_xzr, 31 574 575 .macro mrs_s, rt, sreg 576 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 577 .endm 578 579 .macro msr_s, sreg, rt 580 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 581 .endm 582 583 #else 584 585 #include <linux/types.h> 586 587 asm( 588 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" 589 " .equ .L__reg_num_x\\num, \\num\n" 590 " .endr\n" 591 " .equ .L__reg_num_xzr, 31\n" 592 "\n" 593 " .macro mrs_s, rt, sreg\n" 594 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) 595 " .endm\n" 596 "\n" 597 " .macro msr_s, sreg, rt\n" 598 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) 599 " .endm\n" 600 ); 601 602 /* 603 * Unlike read_cpuid, calls to read_sysreg are never expected to be 604 * optimized away or replaced with synthetic values. 605 */ 606 #define read_sysreg(r) ({ \ 607 u64 __val; \ 608 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 609 __val; \ 610 }) 611 612 /* 613 * The "Z" constraint normally means a zero immediate, but when combined with 614 * the "%x0" template means XZR. 615 */ 616 #define write_sysreg(v, r) do { \ 617 u64 __val = (u64)(v); \ 618 asm volatile("msr " __stringify(r) ", %x0" \ 619 : : "rZ" (__val)); \ 620 } while (0) 621 622 /* 623 * For registers without architectural names, or simply unsupported by 624 * GAS. 625 */ 626 #define read_sysreg_s(r) ({ \ 627 u64 __val; \ 628 asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \ 629 __val; \ 630 }) 631 632 #define write_sysreg_s(v, r) do { \ 633 u64 __val = (u64)(v); \ 634 asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \ 635 } while (0) 636 637 static inline void config_sctlr_el1(u32 clear, u32 set) 638 { 639 u32 val; 640 641 val = read_sysreg(sctlr_el1); 642 val &= ~clear; 643 val |= set; 644 write_sysreg(val, sctlr_el1); 645 } 646 647 #endif 648 649 #endif /* __ASM_SYSREG_H */ 650