1 /* 2 * Macros for accessing system registers with older binutils. 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * Author: Catalin Marinas <catalin.marinas@arm.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __ASM_SYSREG_H 21 #define __ASM_SYSREG_H 22 23 #include <linux/stringify.h> 24 25 /* 26 * ARMv8 ARM reserves the following encoding for system registers: 27 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 28 * C5.2, version:ARM DDI 0487A.f) 29 * [20-19] : Op0 30 * [18-16] : Op1 31 * [15-12] : CRn 32 * [11-8] : CRm 33 * [7-5] : Op2 34 */ 35 #define Op0_shift 19 36 #define Op0_mask 0x3 37 #define Op1_shift 16 38 #define Op1_mask 0x7 39 #define CRn_shift 12 40 #define CRn_mask 0xf 41 #define CRm_shift 8 42 #define CRm_mask 0xf 43 #define Op2_shift 5 44 #define Op2_mask 0x7 45 46 #define sys_reg(op0, op1, crn, crm, op2) \ 47 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 48 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 49 ((op2) << Op2_shift)) 50 51 #define sys_insn sys_reg 52 53 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 54 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 55 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 56 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 57 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 58 59 #ifndef CONFIG_BROKEN_GAS_INST 60 61 #ifdef __ASSEMBLY__ 62 #define __emit_inst(x) .inst (x) 63 #else 64 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 65 #endif 66 67 #else /* CONFIG_BROKEN_GAS_INST */ 68 69 #ifndef CONFIG_CPU_BIG_ENDIAN 70 #define __INSTR_BSWAP(x) (x) 71 #else /* CONFIG_CPU_BIG_ENDIAN */ 72 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 73 (((x) << 8) & 0x00ff0000) | \ 74 (((x) >> 8) & 0x0000ff00) | \ 75 (((x) >> 24) & 0x000000ff)) 76 #endif /* CONFIG_CPU_BIG_ENDIAN */ 77 78 #ifdef __ASSEMBLY__ 79 #define __emit_inst(x) .long __INSTR_BSWAP(x) 80 #else /* __ASSEMBLY__ */ 81 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 82 #endif /* __ASSEMBLY__ */ 83 84 #endif /* CONFIG_BROKEN_GAS_INST */ 85 86 /* 87 * Instructions for modifying PSTATE fields. 88 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 89 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 90 * for accessing PSTATE fields have the following encoding: 91 * Op0 = 0, CRn = 4 92 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 93 * CRm = Imm4 for the instruction. 94 * Rt = 0x1f 95 */ 96 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 97 #define PSTATE_Imm_shift CRm_shift 98 99 #define PSTATE_PAN pstate_field(0, 4) 100 #define PSTATE_UAO pstate_field(0, 3) 101 #define PSTATE_SSBS pstate_field(3, 1) 102 103 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) 104 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) 105 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) 106 107 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 108 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 109 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 110 111 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 112 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 113 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 114 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 115 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 116 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 117 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 118 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 119 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 120 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 121 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 122 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 123 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 124 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 125 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 126 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 127 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 128 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 129 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 130 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 131 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 132 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 133 134 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 135 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 136 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 137 138 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 139 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 140 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 141 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 142 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 143 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 144 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 145 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 146 147 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 148 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 149 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 150 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 151 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 152 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 153 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 154 155 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 156 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 157 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 158 159 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 160 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 161 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) 162 163 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 164 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 165 166 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 167 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 168 169 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 170 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 171 172 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 173 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 174 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 175 176 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 177 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 178 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 179 180 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) 181 182 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 183 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 184 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 185 186 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 187 188 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 189 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 190 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 191 192 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 193 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 194 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 195 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 196 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 197 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 198 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 199 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 200 201 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 202 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 203 204 /*** Statistical Profiling Extension ***/ 205 /* ID registers */ 206 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 207 #define SYS_PMSIDR_EL1_FE_SHIFT 0 208 #define SYS_PMSIDR_EL1_FT_SHIFT 1 209 #define SYS_PMSIDR_EL1_FL_SHIFT 2 210 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 211 #define SYS_PMSIDR_EL1_LDS_SHIFT 4 212 #define SYS_PMSIDR_EL1_ERND_SHIFT 5 213 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 214 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 215 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 216 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 217 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 218 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 219 220 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 221 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 222 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 223 #define SYS_PMBIDR_EL1_P_SHIFT 4 224 #define SYS_PMBIDR_EL1_F_SHIFT 5 225 226 /* Sampling controls */ 227 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 228 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0 229 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1 230 #define SYS_PMSCR_EL1_CX_SHIFT 3 231 #define SYS_PMSCR_EL1_PA_SHIFT 4 232 #define SYS_PMSCR_EL1_TS_SHIFT 5 233 #define SYS_PMSCR_EL1_PCT_SHIFT 6 234 235 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 236 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 237 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1 238 #define SYS_PMSCR_EL2_CX_SHIFT 3 239 #define SYS_PMSCR_EL2_PA_SHIFT 4 240 #define SYS_PMSCR_EL2_TS_SHIFT 5 241 #define SYS_PMSCR_EL2_PCT_SHIFT 6 242 243 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 244 245 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 246 #define SYS_PMSIRR_EL1_RND_SHIFT 0 247 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 248 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 249 250 /* Filtering controls */ 251 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 252 #define SYS_PMSFCR_EL1_FE_SHIFT 0 253 #define SYS_PMSFCR_EL1_FT_SHIFT 1 254 #define SYS_PMSFCR_EL1_FL_SHIFT 2 255 #define SYS_PMSFCR_EL1_B_SHIFT 16 256 #define SYS_PMSFCR_EL1_LD_SHIFT 17 257 #define SYS_PMSFCR_EL1_ST_SHIFT 18 258 259 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 260 #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL 261 262 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 263 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 264 265 /* Buffer controls */ 266 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 267 #define SYS_PMBLIMITR_EL1_E_SHIFT 0 268 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1 269 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 270 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 271 272 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 273 274 /* Buffer error reporting */ 275 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 276 #define SYS_PMBSR_EL1_COLL_SHIFT 16 277 #define SYS_PMBSR_EL1_S_SHIFT 17 278 #define SYS_PMBSR_EL1_EA_SHIFT 18 279 #define SYS_PMBSR_EL1_DL_SHIFT 19 280 #define SYS_PMBSR_EL1_EC_SHIFT 26 281 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL 282 283 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 284 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 285 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 286 287 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 288 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 289 290 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 291 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 292 293 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 294 295 /*** End of Statistical Profiling Extension ***/ 296 297 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 298 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 299 300 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 301 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 302 303 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) 304 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) 305 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) 306 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) 307 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) 308 309 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 310 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 311 312 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 313 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 314 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 315 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 316 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 317 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 318 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 319 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 320 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 321 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 322 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 323 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 324 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 325 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 326 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 327 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 328 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 329 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 330 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 331 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 332 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 333 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 334 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 335 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 336 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 337 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 338 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 339 340 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 341 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 342 343 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 344 345 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 346 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 347 348 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 349 350 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 351 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 352 353 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 354 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 355 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 356 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 357 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 358 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 359 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 360 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 361 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 362 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 363 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 364 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 365 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 366 367 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 368 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 369 370 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 371 372 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 373 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 374 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 375 376 #define __PMEV_op2(n) ((n) & 0x7) 377 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 378 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 379 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 380 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 381 382 #define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7) 383 384 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 385 386 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 387 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 388 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 389 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 390 391 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 392 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 393 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 394 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 395 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 396 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 397 398 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 399 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 400 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 401 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 402 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 403 404 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 405 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 406 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 407 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 408 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 409 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 410 #define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5) 411 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 412 413 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 414 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 415 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 416 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 417 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 418 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 419 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 420 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 421 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 422 423 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 424 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 425 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 426 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 427 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 428 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 429 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 430 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 431 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 432 433 /* Common SCTLR_ELx flags. */ 434 #define SCTLR_ELx_DSSBS (1UL << 44) 435 #define SCTLR_ELx_EE (1 << 25) 436 #define SCTLR_ELx_IESB (1 << 21) 437 #define SCTLR_ELx_WXN (1 << 19) 438 #define SCTLR_ELx_I (1 << 12) 439 #define SCTLR_ELx_SA (1 << 3) 440 #define SCTLR_ELx_C (1 << 2) 441 #define SCTLR_ELx_A (1 << 1) 442 #define SCTLR_ELx_M 1 443 444 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 445 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB) 446 447 /* SCTLR_EL2 specific flags. */ 448 #define SCTLR_EL2_RES1 ((1 << 4) | (1 << 5) | (1 << 11) | (1 << 16) | \ 449 (1 << 18) | (1 << 22) | (1 << 23) | (1 << 28) | \ 450 (1 << 29)) 451 #define SCTLR_EL2_RES0 ((1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | \ 452 (1 << 10) | (1 << 13) | (1 << 14) | (1 << 15) | \ 453 (1 << 17) | (1 << 20) | (1 << 24) | (1 << 26) | \ 454 (1 << 27) | (1 << 30) | (1 << 31) | \ 455 (0xffffefffUL << 32)) 456 457 #ifdef CONFIG_CPU_BIG_ENDIAN 458 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 459 #define ENDIAN_CLEAR_EL2 0 460 #else 461 #define ENDIAN_SET_EL2 0 462 #define ENDIAN_CLEAR_EL2 SCTLR_ELx_EE 463 #endif 464 465 /* SCTLR_EL2 value used for the hyp-stub */ 466 #define SCTLR_EL2_SET (SCTLR_ELx_IESB | ENDIAN_SET_EL2 | SCTLR_EL2_RES1) 467 #define SCTLR_EL2_CLEAR (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 468 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \ 469 SCTLR_ELx_DSSBS | ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0) 470 471 #if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffffUL 472 #error "Inconsistent SCTLR_EL2 set/clear bits" 473 #endif 474 475 /* SCTLR_EL1 specific flags. */ 476 #define SCTLR_EL1_UCI (1 << 26) 477 #define SCTLR_EL1_E0E (1 << 24) 478 #define SCTLR_EL1_SPAN (1 << 23) 479 #define SCTLR_EL1_NTWE (1 << 18) 480 #define SCTLR_EL1_NTWI (1 << 16) 481 #define SCTLR_EL1_UCT (1 << 15) 482 #define SCTLR_EL1_DZE (1 << 14) 483 #define SCTLR_EL1_UMA (1 << 9) 484 #define SCTLR_EL1_SED (1 << 8) 485 #define SCTLR_EL1_ITD (1 << 7) 486 #define SCTLR_EL1_CP15BEN (1 << 5) 487 #define SCTLR_EL1_SA0 (1 << 4) 488 489 #define SCTLR_EL1_RES1 ((1 << 11) | (1 << 20) | (1 << 22) | (1 << 28) | \ 490 (1 << 29)) 491 #define SCTLR_EL1_RES0 ((1 << 6) | (1 << 10) | (1 << 13) | (1 << 17) | \ 492 (1 << 27) | (1 << 30) | (1 << 31) | \ 493 (0xffffefffUL << 32)) 494 495 #ifdef CONFIG_CPU_BIG_ENDIAN 496 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 497 #define ENDIAN_CLEAR_EL1 0 498 #else 499 #define ENDIAN_SET_EL1 0 500 #define ENDIAN_CLEAR_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 501 #endif 502 503 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\ 504 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\ 505 SCTLR_EL1_DZE | SCTLR_EL1_UCT |\ 506 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\ 507 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1) 508 #define SCTLR_EL1_CLEAR (SCTLR_ELx_A | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD |\ 509 SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\ 510 SCTLR_ELx_DSSBS | SCTLR_EL1_NTWI | SCTLR_EL1_RES0) 511 512 #if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffffUL 513 #error "Inconsistent SCTLR_EL1 set/clear bits" 514 #endif 515 516 /* id_aa64isar0 */ 517 #define ID_AA64ISAR0_TS_SHIFT 52 518 #define ID_AA64ISAR0_FHM_SHIFT 48 519 #define ID_AA64ISAR0_DP_SHIFT 44 520 #define ID_AA64ISAR0_SM4_SHIFT 40 521 #define ID_AA64ISAR0_SM3_SHIFT 36 522 #define ID_AA64ISAR0_SHA3_SHIFT 32 523 #define ID_AA64ISAR0_RDM_SHIFT 28 524 #define ID_AA64ISAR0_ATOMICS_SHIFT 20 525 #define ID_AA64ISAR0_CRC32_SHIFT 16 526 #define ID_AA64ISAR0_SHA2_SHIFT 12 527 #define ID_AA64ISAR0_SHA1_SHIFT 8 528 #define ID_AA64ISAR0_AES_SHIFT 4 529 530 /* id_aa64isar1 */ 531 #define ID_AA64ISAR1_LRCPC_SHIFT 20 532 #define ID_AA64ISAR1_FCMA_SHIFT 16 533 #define ID_AA64ISAR1_JSCVT_SHIFT 12 534 #define ID_AA64ISAR1_DPB_SHIFT 0 535 536 /* id_aa64pfr0 */ 537 #define ID_AA64PFR0_CSV3_SHIFT 60 538 #define ID_AA64PFR0_CSV2_SHIFT 56 539 #define ID_AA64PFR0_DIT_SHIFT 48 540 #define ID_AA64PFR0_SVE_SHIFT 32 541 #define ID_AA64PFR0_RAS_SHIFT 28 542 #define ID_AA64PFR0_GIC_SHIFT 24 543 #define ID_AA64PFR0_ASIMD_SHIFT 20 544 #define ID_AA64PFR0_FP_SHIFT 16 545 #define ID_AA64PFR0_EL3_SHIFT 12 546 #define ID_AA64PFR0_EL2_SHIFT 8 547 #define ID_AA64PFR0_EL1_SHIFT 4 548 #define ID_AA64PFR0_EL0_SHIFT 0 549 550 #define ID_AA64PFR0_SVE 0x1 551 #define ID_AA64PFR0_RAS_V1 0x1 552 #define ID_AA64PFR0_FP_NI 0xf 553 #define ID_AA64PFR0_FP_SUPPORTED 0x0 554 #define ID_AA64PFR0_ASIMD_NI 0xf 555 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 556 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 557 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 558 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 559 560 /* id_aa64pfr1 */ 561 #define ID_AA64PFR1_SSBS_SHIFT 4 562 563 #define ID_AA64PFR1_SSBS_PSTATE_NI 0 564 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 565 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 566 567 /* id_aa64mmfr0 */ 568 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 569 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 570 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 571 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 572 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 573 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 574 #define ID_AA64MMFR0_ASID_SHIFT 4 575 #define ID_AA64MMFR0_PARANGE_SHIFT 0 576 577 #define ID_AA64MMFR0_TGRAN4_NI 0xf 578 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 579 #define ID_AA64MMFR0_TGRAN64_NI 0xf 580 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 581 #define ID_AA64MMFR0_TGRAN16_NI 0x0 582 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 583 #define ID_AA64MMFR0_PARANGE_48 0x5 584 #define ID_AA64MMFR0_PARANGE_52 0x6 585 586 #ifdef CONFIG_ARM64_PA_BITS_52 587 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 588 #else 589 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48 590 #endif 591 592 /* id_aa64mmfr1 */ 593 #define ID_AA64MMFR1_PAN_SHIFT 20 594 #define ID_AA64MMFR1_LOR_SHIFT 16 595 #define ID_AA64MMFR1_HPD_SHIFT 12 596 #define ID_AA64MMFR1_VHE_SHIFT 8 597 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 598 #define ID_AA64MMFR1_HADBS_SHIFT 0 599 600 #define ID_AA64MMFR1_VMIDBITS_8 0 601 #define ID_AA64MMFR1_VMIDBITS_16 2 602 603 /* id_aa64mmfr2 */ 604 #define ID_AA64MMFR2_FWB_SHIFT 40 605 #define ID_AA64MMFR2_AT_SHIFT 32 606 #define ID_AA64MMFR2_LVA_SHIFT 16 607 #define ID_AA64MMFR2_IESB_SHIFT 12 608 #define ID_AA64MMFR2_LSM_SHIFT 8 609 #define ID_AA64MMFR2_UAO_SHIFT 4 610 #define ID_AA64MMFR2_CNP_SHIFT 0 611 612 /* id_aa64dfr0 */ 613 #define ID_AA64DFR0_PMSVER_SHIFT 32 614 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 615 #define ID_AA64DFR0_WRPS_SHIFT 20 616 #define ID_AA64DFR0_BRPS_SHIFT 12 617 #define ID_AA64DFR0_PMUVER_SHIFT 8 618 #define ID_AA64DFR0_TRACEVER_SHIFT 4 619 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 620 621 #define ID_ISAR5_RDM_SHIFT 24 622 #define ID_ISAR5_CRC32_SHIFT 16 623 #define ID_ISAR5_SHA2_SHIFT 12 624 #define ID_ISAR5_SHA1_SHIFT 8 625 #define ID_ISAR5_AES_SHIFT 4 626 #define ID_ISAR5_SEVL_SHIFT 0 627 628 #define MVFR0_FPROUND_SHIFT 28 629 #define MVFR0_FPSHVEC_SHIFT 24 630 #define MVFR0_FPSQRT_SHIFT 20 631 #define MVFR0_FPDIVIDE_SHIFT 16 632 #define MVFR0_FPTRAP_SHIFT 12 633 #define MVFR0_FPDP_SHIFT 8 634 #define MVFR0_FPSP_SHIFT 4 635 #define MVFR0_SIMD_SHIFT 0 636 637 #define MVFR1_SIMDFMAC_SHIFT 28 638 #define MVFR1_FPHP_SHIFT 24 639 #define MVFR1_SIMDHP_SHIFT 20 640 #define MVFR1_SIMDSP_SHIFT 16 641 #define MVFR1_SIMDINT_SHIFT 12 642 #define MVFR1_SIMDLS_SHIFT 8 643 #define MVFR1_FPDNAN_SHIFT 4 644 #define MVFR1_FPFTZ_SHIFT 0 645 646 647 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 648 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 649 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 650 651 #define ID_AA64MMFR0_TGRAN4_NI 0xf 652 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 653 #define ID_AA64MMFR0_TGRAN64_NI 0xf 654 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 655 #define ID_AA64MMFR0_TGRAN16_NI 0x0 656 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 657 658 #if defined(CONFIG_ARM64_4K_PAGES) 659 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 660 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED 661 #elif defined(CONFIG_ARM64_16K_PAGES) 662 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 663 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED 664 #elif defined(CONFIG_ARM64_64K_PAGES) 665 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 666 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED 667 #endif 668 669 670 /* 671 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which 672 * are reserved by the SVE architecture for future expansion of the LEN 673 * field, with compatible semantics. 674 */ 675 #define ZCR_ELx_LEN_SHIFT 0 676 #define ZCR_ELx_LEN_SIZE 9 677 #define ZCR_ELx_LEN_MASK 0x1ff 678 679 #define CPACR_EL1_ZEN_EL1EN (1 << 16) /* enable EL1 access */ 680 #define CPACR_EL1_ZEN_EL0EN (1 << 17) /* enable EL0 access, if EL1EN set */ 681 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) 682 683 684 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 685 #define SYS_MPIDR_SAFE_VAL (1UL << 31) 686 687 #ifdef __ASSEMBLY__ 688 689 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 690 .equ .L__reg_num_x\num, \num 691 .endr 692 .equ .L__reg_num_xzr, 31 693 694 .macro mrs_s, rt, sreg 695 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 696 .endm 697 698 .macro msr_s, sreg, rt 699 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 700 .endm 701 702 #else 703 704 #include <linux/build_bug.h> 705 #include <linux/types.h> 706 707 asm( 708 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" 709 " .equ .L__reg_num_x\\num, \\num\n" 710 " .endr\n" 711 " .equ .L__reg_num_xzr, 31\n" 712 "\n" 713 " .macro mrs_s, rt, sreg\n" 714 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) 715 " .endm\n" 716 "\n" 717 " .macro msr_s, sreg, rt\n" 718 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) 719 " .endm\n" 720 ); 721 722 /* 723 * Unlike read_cpuid, calls to read_sysreg are never expected to be 724 * optimized away or replaced with synthetic values. 725 */ 726 #define read_sysreg(r) ({ \ 727 u64 __val; \ 728 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 729 __val; \ 730 }) 731 732 /* 733 * The "Z" constraint normally means a zero immediate, but when combined with 734 * the "%x0" template means XZR. 735 */ 736 #define write_sysreg(v, r) do { \ 737 u64 __val = (u64)(v); \ 738 asm volatile("msr " __stringify(r) ", %x0" \ 739 : : "rZ" (__val)); \ 740 } while (0) 741 742 /* 743 * For registers without architectural names, or simply unsupported by 744 * GAS. 745 */ 746 #define read_sysreg_s(r) ({ \ 747 u64 __val; \ 748 asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \ 749 __val; \ 750 }) 751 752 #define write_sysreg_s(v, r) do { \ 753 u64 __val = (u64)(v); \ 754 asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \ 755 } while (0) 756 757 /* 758 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 759 * set mask are set. Other bits are left as-is. 760 */ 761 #define sysreg_clear_set(sysreg, clear, set) do { \ 762 u64 __scs_val = read_sysreg(sysreg); \ 763 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 764 if (__scs_new != __scs_val) \ 765 write_sysreg(__scs_new, sysreg); \ 766 } while (0) 767 768 #endif 769 770 #endif /* __ASM_SYSREG_H */ 771