xref: /openbmc/linux/arch/arm64/include/asm/sysreg.h (revision 3381df09)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Macros for accessing system registers with older binutils.
4  *
5  * Copyright (C) 2014 ARM Ltd.
6  * Author: Catalin Marinas <catalin.marinas@arm.com>
7  */
8 
9 #ifndef __ASM_SYSREG_H
10 #define __ASM_SYSREG_H
11 
12 #include <linux/bits.h>
13 #include <linux/stringify.h>
14 
15 /*
16  * ARMv8 ARM reserves the following encoding for system registers:
17  * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
18  *  C5.2, version:ARM DDI 0487A.f)
19  *	[20-19] : Op0
20  *	[18-16] : Op1
21  *	[15-12] : CRn
22  *	[11-8]  : CRm
23  *	[7-5]   : Op2
24  */
25 #define Op0_shift	19
26 #define Op0_mask	0x3
27 #define Op1_shift	16
28 #define Op1_mask	0x7
29 #define CRn_shift	12
30 #define CRn_mask	0xf
31 #define CRm_shift	8
32 #define CRm_mask	0xf
33 #define Op2_shift	5
34 #define Op2_mask	0x7
35 
36 #define sys_reg(op0, op1, crn, crm, op2) \
37 	(((op0) << Op0_shift) | ((op1) << Op1_shift) | \
38 	 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
39 	 ((op2) << Op2_shift))
40 
41 #define sys_insn	sys_reg
42 
43 #define sys_reg_Op0(id)	(((id) >> Op0_shift) & Op0_mask)
44 #define sys_reg_Op1(id)	(((id) >> Op1_shift) & Op1_mask)
45 #define sys_reg_CRn(id)	(((id) >> CRn_shift) & CRn_mask)
46 #define sys_reg_CRm(id)	(((id) >> CRm_shift) & CRm_mask)
47 #define sys_reg_Op2(id)	(((id) >> Op2_shift) & Op2_mask)
48 
49 #ifndef CONFIG_BROKEN_GAS_INST
50 
51 #ifdef __ASSEMBLY__
52 #define __emit_inst(x)			.inst (x)
53 #else
54 #define __emit_inst(x)			".inst " __stringify((x)) "\n\t"
55 #endif
56 
57 #else  /* CONFIG_BROKEN_GAS_INST */
58 
59 #ifndef CONFIG_CPU_BIG_ENDIAN
60 #define __INSTR_BSWAP(x)		(x)
61 #else  /* CONFIG_CPU_BIG_ENDIAN */
62 #define __INSTR_BSWAP(x)		((((x) << 24) & 0xff000000)	| \
63 					 (((x) <<  8) & 0x00ff0000)	| \
64 					 (((x) >>  8) & 0x0000ff00)	| \
65 					 (((x) >> 24) & 0x000000ff))
66 #endif	/* CONFIG_CPU_BIG_ENDIAN */
67 
68 #ifdef __ASSEMBLY__
69 #define __emit_inst(x)			.long __INSTR_BSWAP(x)
70 #else  /* __ASSEMBLY__ */
71 #define __emit_inst(x)			".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
72 #endif	/* __ASSEMBLY__ */
73 
74 #endif	/* CONFIG_BROKEN_GAS_INST */
75 
76 /*
77  * Instructions for modifying PSTATE fields.
78  * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
79  * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
80  * for accessing PSTATE fields have the following encoding:
81  *	Op0 = 0, CRn = 4
82  *	Op1, Op2 encodes the PSTATE field modified and defines the constraints.
83  *	CRm = Imm4 for the instruction.
84  *	Rt = 0x1f
85  */
86 #define pstate_field(op1, op2)		((op1) << Op1_shift | (op2) << Op2_shift)
87 #define PSTATE_Imm_shift		CRm_shift
88 
89 #define PSTATE_PAN			pstate_field(0, 4)
90 #define PSTATE_UAO			pstate_field(0, 3)
91 #define PSTATE_SSBS			pstate_field(3, 1)
92 
93 #define SET_PSTATE_PAN(x)		__emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
94 #define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
95 #define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
96 
97 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \
98 	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
99 
100 #define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
101 
102 #define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
103 #define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
104 #define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
105 
106 #define SYS_OSDTRRX_EL1			sys_reg(2, 0, 0, 0, 2)
107 #define SYS_MDCCINT_EL1			sys_reg(2, 0, 0, 2, 0)
108 #define SYS_MDSCR_EL1			sys_reg(2, 0, 0, 2, 2)
109 #define SYS_OSDTRTX_EL1			sys_reg(2, 0, 0, 3, 2)
110 #define SYS_OSECCR_EL1			sys_reg(2, 0, 0, 6, 2)
111 #define SYS_DBGBVRn_EL1(n)		sys_reg(2, 0, 0, n, 4)
112 #define SYS_DBGBCRn_EL1(n)		sys_reg(2, 0, 0, n, 5)
113 #define SYS_DBGWVRn_EL1(n)		sys_reg(2, 0, 0, n, 6)
114 #define SYS_DBGWCRn_EL1(n)		sys_reg(2, 0, 0, n, 7)
115 #define SYS_MDRAR_EL1			sys_reg(2, 0, 1, 0, 0)
116 #define SYS_OSLAR_EL1			sys_reg(2, 0, 1, 0, 4)
117 #define SYS_OSLSR_EL1			sys_reg(2, 0, 1, 1, 4)
118 #define SYS_OSDLR_EL1			sys_reg(2, 0, 1, 3, 4)
119 #define SYS_DBGPRCR_EL1			sys_reg(2, 0, 1, 4, 4)
120 #define SYS_DBGCLAIMSET_EL1		sys_reg(2, 0, 7, 8, 6)
121 #define SYS_DBGCLAIMCLR_EL1		sys_reg(2, 0, 7, 9, 6)
122 #define SYS_DBGAUTHSTATUS_EL1		sys_reg(2, 0, 7, 14, 6)
123 #define SYS_MDCCSR_EL0			sys_reg(2, 3, 0, 1, 0)
124 #define SYS_DBGDTR_EL0			sys_reg(2, 3, 0, 4, 0)
125 #define SYS_DBGDTRRX_EL0		sys_reg(2, 3, 0, 5, 0)
126 #define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
127 #define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)
128 
129 #define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
130 #define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
131 #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
132 
133 #define SYS_ID_PFR0_EL1			sys_reg(3, 0, 0, 1, 0)
134 #define SYS_ID_PFR1_EL1			sys_reg(3, 0, 0, 1, 1)
135 #define SYS_ID_DFR0_EL1			sys_reg(3, 0, 0, 1, 2)
136 #define SYS_ID_AFR0_EL1			sys_reg(3, 0, 0, 1, 3)
137 #define SYS_ID_MMFR0_EL1		sys_reg(3, 0, 0, 1, 4)
138 #define SYS_ID_MMFR1_EL1		sys_reg(3, 0, 0, 1, 5)
139 #define SYS_ID_MMFR2_EL1		sys_reg(3, 0, 0, 1, 6)
140 #define SYS_ID_MMFR3_EL1		sys_reg(3, 0, 0, 1, 7)
141 
142 #define SYS_ID_ISAR0_EL1		sys_reg(3, 0, 0, 2, 0)
143 #define SYS_ID_ISAR1_EL1		sys_reg(3, 0, 0, 2, 1)
144 #define SYS_ID_ISAR2_EL1		sys_reg(3, 0, 0, 2, 2)
145 #define SYS_ID_ISAR3_EL1		sys_reg(3, 0, 0, 2, 3)
146 #define SYS_ID_ISAR4_EL1		sys_reg(3, 0, 0, 2, 4)
147 #define SYS_ID_ISAR5_EL1		sys_reg(3, 0, 0, 2, 5)
148 #define SYS_ID_MMFR4_EL1		sys_reg(3, 0, 0, 2, 6)
149 #define SYS_ID_ISAR6_EL1		sys_reg(3, 0, 0, 2, 7)
150 
151 #define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)
152 #define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
153 #define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)
154 
155 #define SYS_ID_AA64PFR0_EL1		sys_reg(3, 0, 0, 4, 0)
156 #define SYS_ID_AA64PFR1_EL1		sys_reg(3, 0, 0, 4, 1)
157 #define SYS_ID_AA64ZFR0_EL1		sys_reg(3, 0, 0, 4, 4)
158 
159 #define SYS_ID_AA64DFR0_EL1		sys_reg(3, 0, 0, 5, 0)
160 #define SYS_ID_AA64DFR1_EL1		sys_reg(3, 0, 0, 5, 1)
161 
162 #define SYS_ID_AA64AFR0_EL1		sys_reg(3, 0, 0, 5, 4)
163 #define SYS_ID_AA64AFR1_EL1		sys_reg(3, 0, 0, 5, 5)
164 
165 #define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
166 #define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
167 
168 #define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
169 #define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
170 #define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
171 
172 #define SYS_SCTLR_EL1			sys_reg(3, 0, 1, 0, 0)
173 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
174 #define SYS_CPACR_EL1			sys_reg(3, 0, 1, 0, 2)
175 
176 #define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
177 
178 #define SYS_TTBR0_EL1			sys_reg(3, 0, 2, 0, 0)
179 #define SYS_TTBR1_EL1			sys_reg(3, 0, 2, 0, 1)
180 #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
181 
182 #define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
183 #define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
184 #define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
185 #define SYS_APIBKEYHI_EL1		sys_reg(3, 0, 2, 1, 3)
186 
187 #define SYS_APDAKEYLO_EL1		sys_reg(3, 0, 2, 2, 0)
188 #define SYS_APDAKEYHI_EL1		sys_reg(3, 0, 2, 2, 1)
189 #define SYS_APDBKEYLO_EL1		sys_reg(3, 0, 2, 2, 2)
190 #define SYS_APDBKEYHI_EL1		sys_reg(3, 0, 2, 2, 3)
191 
192 #define SYS_APGAKEYLO_EL1		sys_reg(3, 0, 2, 3, 0)
193 #define SYS_APGAKEYHI_EL1		sys_reg(3, 0, 2, 3, 1)
194 
195 #define SYS_SPSR_EL1			sys_reg(3, 0, 4, 0, 0)
196 #define SYS_ELR_EL1			sys_reg(3, 0, 4, 0, 1)
197 
198 #define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
199 
200 #define SYS_AFSR0_EL1			sys_reg(3, 0, 5, 1, 0)
201 #define SYS_AFSR1_EL1			sys_reg(3, 0, 5, 1, 1)
202 #define SYS_ESR_EL1			sys_reg(3, 0, 5, 2, 0)
203 
204 #define SYS_ERRIDR_EL1			sys_reg(3, 0, 5, 3, 0)
205 #define SYS_ERRSELR_EL1			sys_reg(3, 0, 5, 3, 1)
206 #define SYS_ERXFR_EL1			sys_reg(3, 0, 5, 4, 0)
207 #define SYS_ERXCTLR_EL1			sys_reg(3, 0, 5, 4, 1)
208 #define SYS_ERXSTATUS_EL1		sys_reg(3, 0, 5, 4, 2)
209 #define SYS_ERXADDR_EL1			sys_reg(3, 0, 5, 4, 3)
210 #define SYS_ERXMISC0_EL1		sys_reg(3, 0, 5, 5, 0)
211 #define SYS_ERXMISC1_EL1		sys_reg(3, 0, 5, 5, 1)
212 
213 #define SYS_FAR_EL1			sys_reg(3, 0, 6, 0, 0)
214 #define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)
215 
216 #define SYS_PAR_EL1_F			BIT(0)
217 #define SYS_PAR_EL1_FST			GENMASK(6, 1)
218 
219 /*** Statistical Profiling Extension ***/
220 /* ID registers */
221 #define SYS_PMSIDR_EL1			sys_reg(3, 0, 9, 9, 7)
222 #define SYS_PMSIDR_EL1_FE_SHIFT		0
223 #define SYS_PMSIDR_EL1_FT_SHIFT		1
224 #define SYS_PMSIDR_EL1_FL_SHIFT		2
225 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT	3
226 #define SYS_PMSIDR_EL1_LDS_SHIFT	4
227 #define SYS_PMSIDR_EL1_ERND_SHIFT	5
228 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT	8
229 #define SYS_PMSIDR_EL1_INTERVAL_MASK	0xfUL
230 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT	12
231 #define SYS_PMSIDR_EL1_MAXSIZE_MASK	0xfUL
232 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT	16
233 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK	0xfUL
234 
235 #define SYS_PMBIDR_EL1			sys_reg(3, 0, 9, 10, 7)
236 #define SYS_PMBIDR_EL1_ALIGN_SHIFT	0
237 #define SYS_PMBIDR_EL1_ALIGN_MASK	0xfU
238 #define SYS_PMBIDR_EL1_P_SHIFT		4
239 #define SYS_PMBIDR_EL1_F_SHIFT		5
240 
241 /* Sampling controls */
242 #define SYS_PMSCR_EL1			sys_reg(3, 0, 9, 9, 0)
243 #define SYS_PMSCR_EL1_E0SPE_SHIFT	0
244 #define SYS_PMSCR_EL1_E1SPE_SHIFT	1
245 #define SYS_PMSCR_EL1_CX_SHIFT		3
246 #define SYS_PMSCR_EL1_PA_SHIFT		4
247 #define SYS_PMSCR_EL1_TS_SHIFT		5
248 #define SYS_PMSCR_EL1_PCT_SHIFT		6
249 
250 #define SYS_PMSCR_EL2			sys_reg(3, 4, 9, 9, 0)
251 #define SYS_PMSCR_EL2_E0HSPE_SHIFT	0
252 #define SYS_PMSCR_EL2_E2SPE_SHIFT	1
253 #define SYS_PMSCR_EL2_CX_SHIFT		3
254 #define SYS_PMSCR_EL2_PA_SHIFT		4
255 #define SYS_PMSCR_EL2_TS_SHIFT		5
256 #define SYS_PMSCR_EL2_PCT_SHIFT		6
257 
258 #define SYS_PMSICR_EL1			sys_reg(3, 0, 9, 9, 2)
259 
260 #define SYS_PMSIRR_EL1			sys_reg(3, 0, 9, 9, 3)
261 #define SYS_PMSIRR_EL1_RND_SHIFT	0
262 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT	8
263 #define SYS_PMSIRR_EL1_INTERVAL_MASK	0xffffffUL
264 
265 /* Filtering controls */
266 #define SYS_PMSFCR_EL1			sys_reg(3, 0, 9, 9, 4)
267 #define SYS_PMSFCR_EL1_FE_SHIFT		0
268 #define SYS_PMSFCR_EL1_FT_SHIFT		1
269 #define SYS_PMSFCR_EL1_FL_SHIFT		2
270 #define SYS_PMSFCR_EL1_B_SHIFT		16
271 #define SYS_PMSFCR_EL1_LD_SHIFT		17
272 #define SYS_PMSFCR_EL1_ST_SHIFT		18
273 
274 #define SYS_PMSEVFR_EL1			sys_reg(3, 0, 9, 9, 5)
275 #define SYS_PMSEVFR_EL1_RES0		0x0000ffff00ff0f55UL
276 
277 #define SYS_PMSLATFR_EL1		sys_reg(3, 0, 9, 9, 6)
278 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT	0
279 
280 /* Buffer controls */
281 #define SYS_PMBLIMITR_EL1		sys_reg(3, 0, 9, 10, 0)
282 #define SYS_PMBLIMITR_EL1_E_SHIFT	0
283 #define SYS_PMBLIMITR_EL1_FM_SHIFT	1
284 #define SYS_PMBLIMITR_EL1_FM_MASK	0x3UL
285 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ	(0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
286 
287 #define SYS_PMBPTR_EL1			sys_reg(3, 0, 9, 10, 1)
288 
289 /* Buffer error reporting */
290 #define SYS_PMBSR_EL1			sys_reg(3, 0, 9, 10, 3)
291 #define SYS_PMBSR_EL1_COLL_SHIFT	16
292 #define SYS_PMBSR_EL1_S_SHIFT		17
293 #define SYS_PMBSR_EL1_EA_SHIFT		18
294 #define SYS_PMBSR_EL1_DL_SHIFT		19
295 #define SYS_PMBSR_EL1_EC_SHIFT		26
296 #define SYS_PMBSR_EL1_EC_MASK		0x3fUL
297 
298 #define SYS_PMBSR_EL1_EC_BUF		(0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
299 #define SYS_PMBSR_EL1_EC_FAULT_S1	(0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
300 #define SYS_PMBSR_EL1_EC_FAULT_S2	(0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
301 
302 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT	0
303 #define SYS_PMBSR_EL1_FAULT_FSC_MASK	0x3fUL
304 
305 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT	0
306 #define SYS_PMBSR_EL1_BUF_BSC_MASK	0x3fUL
307 
308 #define SYS_PMBSR_EL1_BUF_BSC_FULL	(0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
309 
310 /*** End of Statistical Profiling Extension ***/
311 
312 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
313 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
314 
315 #define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
316 #define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
317 
318 #define SYS_LORSA_EL1			sys_reg(3, 0, 10, 4, 0)
319 #define SYS_LOREA_EL1			sys_reg(3, 0, 10, 4, 1)
320 #define SYS_LORN_EL1			sys_reg(3, 0, 10, 4, 2)
321 #define SYS_LORC_EL1			sys_reg(3, 0, 10, 4, 3)
322 #define SYS_LORID_EL1			sys_reg(3, 0, 10, 4, 7)
323 
324 #define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
325 #define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
326 
327 #define SYS_ICC_IAR0_EL1		sys_reg(3, 0, 12, 8, 0)
328 #define SYS_ICC_EOIR0_EL1		sys_reg(3, 0, 12, 8, 1)
329 #define SYS_ICC_HPPIR0_EL1		sys_reg(3, 0, 12, 8, 2)
330 #define SYS_ICC_BPR0_EL1		sys_reg(3, 0, 12, 8, 3)
331 #define SYS_ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)
332 #define SYS_ICC_AP0R0_EL1		SYS_ICC_AP0Rn_EL1(0)
333 #define SYS_ICC_AP0R1_EL1		SYS_ICC_AP0Rn_EL1(1)
334 #define SYS_ICC_AP0R2_EL1		SYS_ICC_AP0Rn_EL1(2)
335 #define SYS_ICC_AP0R3_EL1		SYS_ICC_AP0Rn_EL1(3)
336 #define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)
337 #define SYS_ICC_AP1R0_EL1		SYS_ICC_AP1Rn_EL1(0)
338 #define SYS_ICC_AP1R1_EL1		SYS_ICC_AP1Rn_EL1(1)
339 #define SYS_ICC_AP1R2_EL1		SYS_ICC_AP1Rn_EL1(2)
340 #define SYS_ICC_AP1R3_EL1		SYS_ICC_AP1Rn_EL1(3)
341 #define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
342 #define SYS_ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)
343 #define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
344 #define SYS_ICC_ASGI1R_EL1		sys_reg(3, 0, 12, 11, 6)
345 #define SYS_ICC_SGI0R_EL1		sys_reg(3, 0, 12, 11, 7)
346 #define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
347 #define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
348 #define SYS_ICC_HPPIR1_EL1		sys_reg(3, 0, 12, 12, 2)
349 #define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
350 #define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
351 #define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
352 #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
353 #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
354 
355 #define SYS_CONTEXTIDR_EL1		sys_reg(3, 0, 13, 0, 1)
356 #define SYS_TPIDR_EL1			sys_reg(3, 0, 13, 0, 4)
357 
358 #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
359 
360 #define SYS_CCSIDR_EL1			sys_reg(3, 1, 0, 0, 0)
361 #define SYS_CLIDR_EL1			sys_reg(3, 1, 0, 0, 1)
362 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
363 
364 #define SYS_CSSELR_EL1			sys_reg(3, 2, 0, 0, 0)
365 
366 #define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)
367 #define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)
368 
369 #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
370 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
371 
372 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
373 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
374 #define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
375 #define SYS_PMOVSCLR_EL0		sys_reg(3, 3, 9, 12, 3)
376 #define SYS_PMSWINC_EL0			sys_reg(3, 3, 9, 12, 4)
377 #define SYS_PMSELR_EL0			sys_reg(3, 3, 9, 12, 5)
378 #define SYS_PMCEID0_EL0			sys_reg(3, 3, 9, 12, 6)
379 #define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
380 #define SYS_PMCCNTR_EL0			sys_reg(3, 3, 9, 13, 0)
381 #define SYS_PMXEVTYPER_EL0		sys_reg(3, 3, 9, 13, 1)
382 #define SYS_PMXEVCNTR_EL0		sys_reg(3, 3, 9, 13, 2)
383 #define SYS_PMUSERENR_EL0		sys_reg(3, 3, 9, 14, 0)
384 #define SYS_PMOVSSET_EL0		sys_reg(3, 3, 9, 14, 3)
385 
386 #define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
387 #define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
388 
389 /* Definitions for system register interface to AMU for ARMv8.4 onwards */
390 #define SYS_AM_EL0(crm, op2)		sys_reg(3, 3, 13, (crm), (op2))
391 #define SYS_AMCR_EL0			SYS_AM_EL0(2, 0)
392 #define SYS_AMCFGR_EL0			SYS_AM_EL0(2, 1)
393 #define SYS_AMCGCR_EL0			SYS_AM_EL0(2, 2)
394 #define SYS_AMUSERENR_EL0		SYS_AM_EL0(2, 3)
395 #define SYS_AMCNTENCLR0_EL0		SYS_AM_EL0(2, 4)
396 #define SYS_AMCNTENSET0_EL0		SYS_AM_EL0(2, 5)
397 #define SYS_AMCNTENCLR1_EL0		SYS_AM_EL0(3, 0)
398 #define SYS_AMCNTENSET1_EL0		SYS_AM_EL0(3, 1)
399 
400 /*
401  * Group 0 of activity monitors (architected):
402  *                op0  op1  CRn   CRm       op2
403  * Counter:       11   011  1101  010:n<3>  n<2:0>
404  * Type:          11   011  1101  011:n<3>  n<2:0>
405  * n: 0-15
406  *
407  * Group 1 of activity monitors (auxiliary):
408  *                op0  op1  CRn   CRm       op2
409  * Counter:       11   011  1101  110:n<3>  n<2:0>
410  * Type:          11   011  1101  111:n<3>  n<2:0>
411  * n: 0-15
412  */
413 
414 #define SYS_AMEVCNTR0_EL0(n)		SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
415 #define SYS_AMEVTYPE0_EL0(n)		SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
416 #define SYS_AMEVCNTR1_EL0(n)		SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
417 #define SYS_AMEVTYPE1_EL0(n)		SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
418 
419 /* AMU v1: Fixed (architecturally defined) activity monitors */
420 #define SYS_AMEVCNTR0_CORE_EL0		SYS_AMEVCNTR0_EL0(0)
421 #define SYS_AMEVCNTR0_CONST_EL0		SYS_AMEVCNTR0_EL0(1)
422 #define SYS_AMEVCNTR0_INST_RET_EL0	SYS_AMEVCNTR0_EL0(2)
423 #define SYS_AMEVCNTR0_MEM_STALL		SYS_AMEVCNTR0_EL0(3)
424 
425 #define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
426 
427 #define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
428 #define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
429 #define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)
430 
431 #define SYS_CNTV_CTL_EL0		sys_reg(3, 3, 14, 3, 1)
432 #define SYS_CNTV_CVAL_EL0		sys_reg(3, 3, 14, 3, 2)
433 
434 #define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)
435 #define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)
436 #define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)
437 
438 #define __PMEV_op2(n)			((n) & 0x7)
439 #define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
440 #define SYS_PMEVCNTRn_EL0(n)		sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
441 #define __TYPER_CRm(n)			(0xc | (((n) >> 3) & 0x3))
442 #define SYS_PMEVTYPERn_EL0(n)		sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
443 
444 #define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
445 
446 #define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)
447 #define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
448 #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
449 #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
450 #define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
451 #define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
452 #define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)
453 #define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
454 #define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
455 
456 #define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1,  1)
457 #define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
458 #define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
459 #define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
460 #define SYS_ICH_AP0R2_EL2		__SYS__AP0Rx_EL2(2)
461 #define SYS_ICH_AP0R3_EL2		__SYS__AP0Rx_EL2(3)
462 
463 #define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
464 #define SYS_ICH_AP1R0_EL2		__SYS__AP1Rx_EL2(0)
465 #define SYS_ICH_AP1R1_EL2		__SYS__AP1Rx_EL2(1)
466 #define SYS_ICH_AP1R2_EL2		__SYS__AP1Rx_EL2(2)
467 #define SYS_ICH_AP1R3_EL2		__SYS__AP1Rx_EL2(3)
468 
469 #define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
470 #define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
471 #define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
472 #define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
473 #define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)
474 #define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
475 #define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)
476 #define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
477 
478 #define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
479 #define SYS_ICH_LR0_EL2			__SYS__LR0_EL2(0)
480 #define SYS_ICH_LR1_EL2			__SYS__LR0_EL2(1)
481 #define SYS_ICH_LR2_EL2			__SYS__LR0_EL2(2)
482 #define SYS_ICH_LR3_EL2			__SYS__LR0_EL2(3)
483 #define SYS_ICH_LR4_EL2			__SYS__LR0_EL2(4)
484 #define SYS_ICH_LR5_EL2			__SYS__LR0_EL2(5)
485 #define SYS_ICH_LR6_EL2			__SYS__LR0_EL2(6)
486 #define SYS_ICH_LR7_EL2			__SYS__LR0_EL2(7)
487 
488 #define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
489 #define SYS_ICH_LR8_EL2			__SYS__LR8_EL2(0)
490 #define SYS_ICH_LR9_EL2			__SYS__LR8_EL2(1)
491 #define SYS_ICH_LR10_EL2		__SYS__LR8_EL2(2)
492 #define SYS_ICH_LR11_EL2		__SYS__LR8_EL2(3)
493 #define SYS_ICH_LR12_EL2		__SYS__LR8_EL2(4)
494 #define SYS_ICH_LR13_EL2		__SYS__LR8_EL2(5)
495 #define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
496 #define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
497 
498 /* VHE encodings for architectural EL0/1 system registers */
499 #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
500 #define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)
501 #define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)
502 #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
503 #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
504 #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
505 #define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)
506 #define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)
507 #define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)
508 #define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
509 #define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
510 #define SYS_FAR_EL12			sys_reg(3, 5, 6, 0, 0)
511 #define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
512 #define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
513 #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
514 #define SYS_CONTEXTIDR_EL12		sys_reg(3, 5, 13, 0, 1)
515 #define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
516 #define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
517 #define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
518 #define SYS_CNTP_CVAL_EL02		sys_reg(3, 5, 14, 2, 2)
519 #define SYS_CNTV_TVAL_EL02		sys_reg(3, 5, 14, 3, 0)
520 #define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
521 #define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
522 
523 /* Common SCTLR_ELx flags. */
524 #define SCTLR_ELx_DSSBS	(BIT(44))
525 #define SCTLR_ELx_ENIA	(BIT(31))
526 #define SCTLR_ELx_ENIB	(BIT(30))
527 #define SCTLR_ELx_ENDA	(BIT(27))
528 #define SCTLR_ELx_EE    (BIT(25))
529 #define SCTLR_ELx_IESB	(BIT(21))
530 #define SCTLR_ELx_WXN	(BIT(19))
531 #define SCTLR_ELx_ENDB	(BIT(13))
532 #define SCTLR_ELx_I	(BIT(12))
533 #define SCTLR_ELx_SA	(BIT(3))
534 #define SCTLR_ELx_C	(BIT(2))
535 #define SCTLR_ELx_A	(BIT(1))
536 #define SCTLR_ELx_M	(BIT(0))
537 
538 #define SCTLR_ELx_FLAGS	(SCTLR_ELx_M  | SCTLR_ELx_A | SCTLR_ELx_C | \
539 			 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB)
540 
541 /* SCTLR_EL2 specific flags. */
542 #define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
543 			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
544 			 (BIT(29)))
545 
546 #ifdef CONFIG_CPU_BIG_ENDIAN
547 #define ENDIAN_SET_EL2		SCTLR_ELx_EE
548 #else
549 #define ENDIAN_SET_EL2		0
550 #endif
551 
552 /* SCTLR_EL1 specific flags. */
553 #define SCTLR_EL1_UCI		(BIT(26))
554 #define SCTLR_EL1_E0E		(BIT(24))
555 #define SCTLR_EL1_SPAN		(BIT(23))
556 #define SCTLR_EL1_NTWE		(BIT(18))
557 #define SCTLR_EL1_NTWI		(BIT(16))
558 #define SCTLR_EL1_UCT		(BIT(15))
559 #define SCTLR_EL1_DZE		(BIT(14))
560 #define SCTLR_EL1_UMA		(BIT(9))
561 #define SCTLR_EL1_SED		(BIT(8))
562 #define SCTLR_EL1_ITD		(BIT(7))
563 #define SCTLR_EL1_CP15BEN	(BIT(5))
564 #define SCTLR_EL1_SA0		(BIT(4))
565 
566 #define SCTLR_EL1_RES1	((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
567 			 (BIT(29)))
568 
569 #ifdef CONFIG_CPU_BIG_ENDIAN
570 #define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
571 #else
572 #define ENDIAN_SET_EL1		0
573 #endif
574 
575 #define SCTLR_EL1_SET	(SCTLR_ELx_M    | SCTLR_ELx_C    | SCTLR_ELx_SA   |\
576 			 SCTLR_EL1_SA0  | SCTLR_EL1_SED  | SCTLR_ELx_I    |\
577 			 SCTLR_EL1_DZE  | SCTLR_EL1_UCT                   |\
578 			 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\
579 			 ENDIAN_SET_EL1 | SCTLR_EL1_UCI  | SCTLR_EL1_RES1)
580 
581 /* MAIR_ELx memory attributes (used by Linux) */
582 #define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
583 #define MAIR_ATTR_DEVICE_nGnRE		UL(0x04)
584 #define MAIR_ATTR_DEVICE_GRE		UL(0x0c)
585 #define MAIR_ATTR_NORMAL_NC		UL(0x44)
586 #define MAIR_ATTR_NORMAL_WT		UL(0xbb)
587 #define MAIR_ATTR_NORMAL		UL(0xff)
588 #define MAIR_ATTR_MASK			UL(0xff)
589 
590 /* Position the attr at the correct index */
591 #define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
592 
593 /* id_aa64isar0 */
594 #define ID_AA64ISAR0_RNDR_SHIFT		60
595 #define ID_AA64ISAR0_TS_SHIFT		52
596 #define ID_AA64ISAR0_FHM_SHIFT		48
597 #define ID_AA64ISAR0_DP_SHIFT		44
598 #define ID_AA64ISAR0_SM4_SHIFT		40
599 #define ID_AA64ISAR0_SM3_SHIFT		36
600 #define ID_AA64ISAR0_SHA3_SHIFT		32
601 #define ID_AA64ISAR0_RDM_SHIFT		28
602 #define ID_AA64ISAR0_ATOMICS_SHIFT	20
603 #define ID_AA64ISAR0_CRC32_SHIFT	16
604 #define ID_AA64ISAR0_SHA2_SHIFT		12
605 #define ID_AA64ISAR0_SHA1_SHIFT		8
606 #define ID_AA64ISAR0_AES_SHIFT		4
607 
608 /* id_aa64isar1 */
609 #define ID_AA64ISAR1_I8MM_SHIFT		52
610 #define ID_AA64ISAR1_DGH_SHIFT		48
611 #define ID_AA64ISAR1_BF16_SHIFT		44
612 #define ID_AA64ISAR1_SPECRES_SHIFT	40
613 #define ID_AA64ISAR1_SB_SHIFT		36
614 #define ID_AA64ISAR1_FRINTTS_SHIFT	32
615 #define ID_AA64ISAR1_GPI_SHIFT		28
616 #define ID_AA64ISAR1_GPA_SHIFT		24
617 #define ID_AA64ISAR1_LRCPC_SHIFT	20
618 #define ID_AA64ISAR1_FCMA_SHIFT		16
619 #define ID_AA64ISAR1_JSCVT_SHIFT	12
620 #define ID_AA64ISAR1_API_SHIFT		8
621 #define ID_AA64ISAR1_APA_SHIFT		4
622 #define ID_AA64ISAR1_DPB_SHIFT		0
623 
624 #define ID_AA64ISAR1_APA_NI		0x0
625 #define ID_AA64ISAR1_APA_ARCHITECTED	0x1
626 #define ID_AA64ISAR1_API_NI		0x0
627 #define ID_AA64ISAR1_API_IMP_DEF	0x1
628 #define ID_AA64ISAR1_GPA_NI		0x0
629 #define ID_AA64ISAR1_GPA_ARCHITECTED	0x1
630 #define ID_AA64ISAR1_GPI_NI		0x0
631 #define ID_AA64ISAR1_GPI_IMP_DEF	0x1
632 
633 /* id_aa64pfr0 */
634 #define ID_AA64PFR0_CSV3_SHIFT		60
635 #define ID_AA64PFR0_CSV2_SHIFT		56
636 #define ID_AA64PFR0_DIT_SHIFT		48
637 #define ID_AA64PFR0_AMU_SHIFT		44
638 #define ID_AA64PFR0_SVE_SHIFT		32
639 #define ID_AA64PFR0_RAS_SHIFT		28
640 #define ID_AA64PFR0_GIC_SHIFT		24
641 #define ID_AA64PFR0_ASIMD_SHIFT		20
642 #define ID_AA64PFR0_FP_SHIFT		16
643 #define ID_AA64PFR0_EL3_SHIFT		12
644 #define ID_AA64PFR0_EL2_SHIFT		8
645 #define ID_AA64PFR0_EL1_SHIFT		4
646 #define ID_AA64PFR0_EL0_SHIFT		0
647 
648 #define ID_AA64PFR0_AMU			0x1
649 #define ID_AA64PFR0_SVE			0x1
650 #define ID_AA64PFR0_RAS_V1		0x1
651 #define ID_AA64PFR0_FP_NI		0xf
652 #define ID_AA64PFR0_FP_SUPPORTED	0x0
653 #define ID_AA64PFR0_ASIMD_NI		0xf
654 #define ID_AA64PFR0_ASIMD_SUPPORTED	0x0
655 #define ID_AA64PFR0_EL1_64BIT_ONLY	0x1
656 #define ID_AA64PFR0_EL0_64BIT_ONLY	0x1
657 #define ID_AA64PFR0_EL0_32BIT_64BIT	0x2
658 
659 /* id_aa64pfr1 */
660 #define ID_AA64PFR1_SSBS_SHIFT		4
661 
662 #define ID_AA64PFR1_SSBS_PSTATE_NI	0
663 #define ID_AA64PFR1_SSBS_PSTATE_ONLY	1
664 #define ID_AA64PFR1_SSBS_PSTATE_INSNS	2
665 
666 /* id_aa64zfr0 */
667 #define ID_AA64ZFR0_F64MM_SHIFT		56
668 #define ID_AA64ZFR0_F32MM_SHIFT		52
669 #define ID_AA64ZFR0_I8MM_SHIFT		44
670 #define ID_AA64ZFR0_SM4_SHIFT		40
671 #define ID_AA64ZFR0_SHA3_SHIFT		32
672 #define ID_AA64ZFR0_BF16_SHIFT		20
673 #define ID_AA64ZFR0_BITPERM_SHIFT	16
674 #define ID_AA64ZFR0_AES_SHIFT		4
675 #define ID_AA64ZFR0_SVEVER_SHIFT	0
676 
677 #define ID_AA64ZFR0_F64MM		0x1
678 #define ID_AA64ZFR0_F32MM		0x1
679 #define ID_AA64ZFR0_I8MM		0x1
680 #define ID_AA64ZFR0_BF16		0x1
681 #define ID_AA64ZFR0_SM4			0x1
682 #define ID_AA64ZFR0_SHA3		0x1
683 #define ID_AA64ZFR0_BITPERM		0x1
684 #define ID_AA64ZFR0_AES			0x1
685 #define ID_AA64ZFR0_AES_PMULL		0x2
686 #define ID_AA64ZFR0_SVEVER_SVE2		0x1
687 
688 /* id_aa64mmfr0 */
689 #define ID_AA64MMFR0_TGRAN4_SHIFT	28
690 #define ID_AA64MMFR0_TGRAN64_SHIFT	24
691 #define ID_AA64MMFR0_TGRAN16_SHIFT	20
692 #define ID_AA64MMFR0_BIGENDEL0_SHIFT	16
693 #define ID_AA64MMFR0_SNSMEM_SHIFT	12
694 #define ID_AA64MMFR0_BIGENDEL_SHIFT	8
695 #define ID_AA64MMFR0_ASID_SHIFT		4
696 #define ID_AA64MMFR0_PARANGE_SHIFT	0
697 
698 #define ID_AA64MMFR0_TGRAN4_NI		0xf
699 #define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
700 #define ID_AA64MMFR0_TGRAN64_NI		0xf
701 #define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0
702 #define ID_AA64MMFR0_TGRAN16_NI		0x0
703 #define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1
704 #define ID_AA64MMFR0_PARANGE_48		0x5
705 #define ID_AA64MMFR0_PARANGE_52		0x6
706 
707 #ifdef CONFIG_ARM64_PA_BITS_52
708 #define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_52
709 #else
710 #define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_48
711 #endif
712 
713 /* id_aa64mmfr1 */
714 #define ID_AA64MMFR1_PAN_SHIFT		20
715 #define ID_AA64MMFR1_LOR_SHIFT		16
716 #define ID_AA64MMFR1_HPD_SHIFT		12
717 #define ID_AA64MMFR1_VHE_SHIFT		8
718 #define ID_AA64MMFR1_VMIDBITS_SHIFT	4
719 #define ID_AA64MMFR1_HADBS_SHIFT	0
720 
721 #define ID_AA64MMFR1_VMIDBITS_8		0
722 #define ID_AA64MMFR1_VMIDBITS_16	2
723 
724 /* id_aa64mmfr2 */
725 #define ID_AA64MMFR2_E0PD_SHIFT		60
726 #define ID_AA64MMFR2_FWB_SHIFT		40
727 #define ID_AA64MMFR2_AT_SHIFT		32
728 #define ID_AA64MMFR2_LVA_SHIFT		16
729 #define ID_AA64MMFR2_IESB_SHIFT		12
730 #define ID_AA64MMFR2_LSM_SHIFT		8
731 #define ID_AA64MMFR2_UAO_SHIFT		4
732 #define ID_AA64MMFR2_CNP_SHIFT		0
733 
734 /* id_aa64dfr0 */
735 #define ID_AA64DFR0_PMSVER_SHIFT	32
736 #define ID_AA64DFR0_CTX_CMPS_SHIFT	28
737 #define ID_AA64DFR0_WRPS_SHIFT		20
738 #define ID_AA64DFR0_BRPS_SHIFT		12
739 #define ID_AA64DFR0_PMUVER_SHIFT	8
740 #define ID_AA64DFR0_TRACEVER_SHIFT	4
741 #define ID_AA64DFR0_DEBUGVER_SHIFT	0
742 
743 #define ID_AA64DFR0_PMUVER_8_0		0x1
744 #define ID_AA64DFR0_PMUVER_8_1		0x4
745 #define ID_AA64DFR0_PMUVER_8_4		0x5
746 #define ID_AA64DFR0_PMUVER_8_5		0x6
747 #define ID_AA64DFR0_PMUVER_IMP_DEF	0xf
748 
749 #define ID_DFR0_PERFMON_SHIFT		24
750 
751 #define ID_DFR0_PERFMON_8_1		0x4
752 
753 #define ID_ISAR5_RDM_SHIFT		24
754 #define ID_ISAR5_CRC32_SHIFT		16
755 #define ID_ISAR5_SHA2_SHIFT		12
756 #define ID_ISAR5_SHA1_SHIFT		8
757 #define ID_ISAR5_AES_SHIFT		4
758 #define ID_ISAR5_SEVL_SHIFT		0
759 
760 #define ID_ISAR6_I8MM_SHIFT		24
761 #define ID_ISAR6_BF16_SHIFT		20
762 #define ID_ISAR6_SPECRES_SHIFT		16
763 #define ID_ISAR6_SB_SHIFT		12
764 #define ID_ISAR6_FHM_SHIFT		8
765 #define ID_ISAR6_DP_SHIFT		4
766 #define ID_ISAR6_JSCVT_SHIFT		0
767 
768 #define MVFR0_FPROUND_SHIFT		28
769 #define MVFR0_FPSHVEC_SHIFT		24
770 #define MVFR0_FPSQRT_SHIFT		20
771 #define MVFR0_FPDIVIDE_SHIFT		16
772 #define MVFR0_FPTRAP_SHIFT		12
773 #define MVFR0_FPDP_SHIFT		8
774 #define MVFR0_FPSP_SHIFT		4
775 #define MVFR0_SIMD_SHIFT		0
776 
777 #define MVFR1_SIMDFMAC_SHIFT		28
778 #define MVFR1_FPHP_SHIFT		24
779 #define MVFR1_SIMDHP_SHIFT		20
780 #define MVFR1_SIMDSP_SHIFT		16
781 #define MVFR1_SIMDINT_SHIFT		12
782 #define MVFR1_SIMDLS_SHIFT		8
783 #define MVFR1_FPDNAN_SHIFT		4
784 #define MVFR1_FPFTZ_SHIFT		0
785 
786 
787 #define ID_AA64MMFR0_TGRAN4_SHIFT	28
788 #define ID_AA64MMFR0_TGRAN64_SHIFT	24
789 #define ID_AA64MMFR0_TGRAN16_SHIFT	20
790 
791 #define ID_AA64MMFR0_TGRAN4_NI		0xf
792 #define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0
793 #define ID_AA64MMFR0_TGRAN64_NI		0xf
794 #define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0
795 #define ID_AA64MMFR0_TGRAN16_NI		0x0
796 #define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1
797 
798 #if defined(CONFIG_ARM64_4K_PAGES)
799 #define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN4_SHIFT
800 #define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN4_SUPPORTED
801 #elif defined(CONFIG_ARM64_16K_PAGES)
802 #define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN16_SHIFT
803 #define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN16_SUPPORTED
804 #elif defined(CONFIG_ARM64_64K_PAGES)
805 #define ID_AA64MMFR0_TGRAN_SHIFT	ID_AA64MMFR0_TGRAN64_SHIFT
806 #define ID_AA64MMFR0_TGRAN_SUPPORTED	ID_AA64MMFR0_TGRAN64_SUPPORTED
807 #endif
808 
809 
810 /*
811  * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
812  * are reserved by the SVE architecture for future expansion of the LEN
813  * field, with compatible semantics.
814  */
815 #define ZCR_ELx_LEN_SHIFT	0
816 #define ZCR_ELx_LEN_SIZE	9
817 #define ZCR_ELx_LEN_MASK	0x1ff
818 
819 #define CPACR_EL1_ZEN_EL1EN	(BIT(16)) /* enable EL1 access */
820 #define CPACR_EL1_ZEN_EL0EN	(BIT(17)) /* enable EL0 access, if EL1EN set */
821 #define CPACR_EL1_ZEN		(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
822 
823 
824 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
825 #define SYS_MPIDR_SAFE_VAL	(BIT(31))
826 
827 #ifdef __ASSEMBLY__
828 
829 	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
830 	.equ	.L__reg_num_x\num, \num
831 	.endr
832 	.equ	.L__reg_num_xzr, 31
833 
834 	.macro	mrs_s, rt, sreg
835 	 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
836 	.endm
837 
838 	.macro	msr_s, sreg, rt
839 	__emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
840 	.endm
841 
842 #else
843 
844 #include <linux/build_bug.h>
845 #include <linux/types.h>
846 
847 #define __DEFINE_MRS_MSR_S_REGNUM				\
848 "	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
849 "	.equ	.L__reg_num_x\\num, \\num\n"			\
850 "	.endr\n"						\
851 "	.equ	.L__reg_num_xzr, 31\n"
852 
853 #define DEFINE_MRS_S						\
854 	__DEFINE_MRS_MSR_S_REGNUM				\
855 "	.macro	mrs_s, rt, sreg\n"				\
856 	__emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt))	\
857 "	.endm\n"
858 
859 #define DEFINE_MSR_S						\
860 	__DEFINE_MRS_MSR_S_REGNUM				\
861 "	.macro	msr_s, sreg, rt\n"				\
862 	__emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt))	\
863 "	.endm\n"
864 
865 #define UNDEFINE_MRS_S						\
866 "	.purgem	mrs_s\n"
867 
868 #define UNDEFINE_MSR_S						\
869 "	.purgem	msr_s\n"
870 
871 #define __mrs_s(v, r)						\
872 	DEFINE_MRS_S						\
873 "	mrs_s " v ", " __stringify(r) "\n"			\
874 	UNDEFINE_MRS_S
875 
876 #define __msr_s(r, v)						\
877 	DEFINE_MSR_S						\
878 "	msr_s " __stringify(r) ", " v "\n"			\
879 	UNDEFINE_MSR_S
880 
881 /*
882  * Unlike read_cpuid, calls to read_sysreg are never expected to be
883  * optimized away or replaced with synthetic values.
884  */
885 #define read_sysreg(r) ({					\
886 	u64 __val;						\
887 	asm volatile("mrs %0, " __stringify(r) : "=r" (__val));	\
888 	__val;							\
889 })
890 
891 /*
892  * The "Z" constraint normally means a zero immediate, but when combined with
893  * the "%x0" template means XZR.
894  */
895 #define write_sysreg(v, r) do {					\
896 	u64 __val = (u64)(v);					\
897 	asm volatile("msr " __stringify(r) ", %x0"		\
898 		     : : "rZ" (__val));				\
899 } while (0)
900 
901 /*
902  * For registers without architectural names, or simply unsupported by
903  * GAS.
904  */
905 #define read_sysreg_s(r) ({						\
906 	u64 __val;							\
907 	asm volatile(__mrs_s("%0", r) : "=r" (__val));			\
908 	__val;								\
909 })
910 
911 #define write_sysreg_s(v, r) do {					\
912 	u64 __val = (u64)(v);						\
913 	asm volatile(__msr_s(r, "%x0") : : "rZ" (__val));		\
914 } while (0)
915 
916 /*
917  * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
918  * set mask are set. Other bits are left as-is.
919  */
920 #define sysreg_clear_set(sysreg, clear, set) do {			\
921 	u64 __scs_val = read_sysreg(sysreg);				\
922 	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
923 	if (__scs_new != __scs_val)					\
924 		write_sysreg(__scs_new, sysreg);			\
925 } while (0)
926 
927 #endif
928 
929 #endif	/* __ASM_SYSREG_H */
930