1 /* 2 * Macros for accessing system registers with older binutils. 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * Author: Catalin Marinas <catalin.marinas@arm.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __ASM_SYSREG_H 21 #define __ASM_SYSREG_H 22 23 #include <linux/const.h> 24 #include <linux/stringify.h> 25 26 /* 27 * ARMv8 ARM reserves the following encoding for system registers: 28 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 29 * C5.2, version:ARM DDI 0487A.f) 30 * [20-19] : Op0 31 * [18-16] : Op1 32 * [15-12] : CRn 33 * [11-8] : CRm 34 * [7-5] : Op2 35 */ 36 #define Op0_shift 19 37 #define Op0_mask 0x3 38 #define Op1_shift 16 39 #define Op1_mask 0x7 40 #define CRn_shift 12 41 #define CRn_mask 0xf 42 #define CRm_shift 8 43 #define CRm_mask 0xf 44 #define Op2_shift 5 45 #define Op2_mask 0x7 46 47 #define sys_reg(op0, op1, crn, crm, op2) \ 48 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 49 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 50 ((op2) << Op2_shift)) 51 52 #define sys_insn sys_reg 53 54 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 55 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 56 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 57 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 58 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 59 60 #ifndef CONFIG_BROKEN_GAS_INST 61 62 #ifdef __ASSEMBLY__ 63 #define __emit_inst(x) .inst (x) 64 #else 65 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 66 #endif 67 68 #else /* CONFIG_BROKEN_GAS_INST */ 69 70 #ifndef CONFIG_CPU_BIG_ENDIAN 71 #define __INSTR_BSWAP(x) (x) 72 #else /* CONFIG_CPU_BIG_ENDIAN */ 73 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 74 (((x) << 8) & 0x00ff0000) | \ 75 (((x) >> 8) & 0x0000ff00) | \ 76 (((x) >> 24) & 0x000000ff)) 77 #endif /* CONFIG_CPU_BIG_ENDIAN */ 78 79 #ifdef __ASSEMBLY__ 80 #define __emit_inst(x) .long __INSTR_BSWAP(x) 81 #else /* __ASSEMBLY__ */ 82 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 83 #endif /* __ASSEMBLY__ */ 84 85 #endif /* CONFIG_BROKEN_GAS_INST */ 86 87 /* 88 * Instructions for modifying PSTATE fields. 89 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 90 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 91 * for accessing PSTATE fields have the following encoding: 92 * Op0 = 0, CRn = 4 93 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 94 * CRm = Imm4 for the instruction. 95 * Rt = 0x1f 96 */ 97 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 98 #define PSTATE_Imm_shift CRm_shift 99 100 #define PSTATE_PAN pstate_field(0, 4) 101 #define PSTATE_UAO pstate_field(0, 3) 102 #define PSTATE_SSBS pstate_field(3, 1) 103 104 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) 105 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) 106 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) 107 108 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ 109 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) 110 111 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) 112 113 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 114 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 115 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 116 117 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 118 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 119 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 120 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 121 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 122 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 123 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 124 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 125 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 126 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 127 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 128 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 129 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 130 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 131 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 132 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 133 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 134 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 135 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 136 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 137 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 138 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 139 140 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 141 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 142 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 143 144 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 145 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 146 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 147 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 148 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 149 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 150 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 151 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 152 153 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 154 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 155 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 156 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 157 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 158 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 159 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 160 161 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 162 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 163 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 164 165 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 166 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 167 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) 168 169 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 170 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 171 172 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 173 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 174 175 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 176 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 177 178 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 179 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 180 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 181 182 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 183 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 184 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 185 186 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) 187 188 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 189 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 190 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 191 192 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 193 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 194 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 195 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 196 197 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 198 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 199 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 200 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 201 202 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 203 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 204 205 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 206 207 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 208 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 209 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 210 211 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 212 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 213 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 214 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 215 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 216 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 217 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 218 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 219 220 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 221 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 222 223 /*** Statistical Profiling Extension ***/ 224 /* ID registers */ 225 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 226 #define SYS_PMSIDR_EL1_FE_SHIFT 0 227 #define SYS_PMSIDR_EL1_FT_SHIFT 1 228 #define SYS_PMSIDR_EL1_FL_SHIFT 2 229 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 230 #define SYS_PMSIDR_EL1_LDS_SHIFT 4 231 #define SYS_PMSIDR_EL1_ERND_SHIFT 5 232 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 233 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 234 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 235 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 236 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 237 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 238 239 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 240 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 241 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 242 #define SYS_PMBIDR_EL1_P_SHIFT 4 243 #define SYS_PMBIDR_EL1_F_SHIFT 5 244 245 /* Sampling controls */ 246 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 247 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0 248 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1 249 #define SYS_PMSCR_EL1_CX_SHIFT 3 250 #define SYS_PMSCR_EL1_PA_SHIFT 4 251 #define SYS_PMSCR_EL1_TS_SHIFT 5 252 #define SYS_PMSCR_EL1_PCT_SHIFT 6 253 254 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 255 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 256 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1 257 #define SYS_PMSCR_EL2_CX_SHIFT 3 258 #define SYS_PMSCR_EL2_PA_SHIFT 4 259 #define SYS_PMSCR_EL2_TS_SHIFT 5 260 #define SYS_PMSCR_EL2_PCT_SHIFT 6 261 262 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 263 264 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 265 #define SYS_PMSIRR_EL1_RND_SHIFT 0 266 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 267 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 268 269 /* Filtering controls */ 270 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 271 #define SYS_PMSFCR_EL1_FE_SHIFT 0 272 #define SYS_PMSFCR_EL1_FT_SHIFT 1 273 #define SYS_PMSFCR_EL1_FL_SHIFT 2 274 #define SYS_PMSFCR_EL1_B_SHIFT 16 275 #define SYS_PMSFCR_EL1_LD_SHIFT 17 276 #define SYS_PMSFCR_EL1_ST_SHIFT 18 277 278 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 279 #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL 280 281 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 282 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 283 284 /* Buffer controls */ 285 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 286 #define SYS_PMBLIMITR_EL1_E_SHIFT 0 287 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1 288 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 289 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 290 291 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 292 293 /* Buffer error reporting */ 294 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 295 #define SYS_PMBSR_EL1_COLL_SHIFT 16 296 #define SYS_PMBSR_EL1_S_SHIFT 17 297 #define SYS_PMBSR_EL1_EA_SHIFT 18 298 #define SYS_PMBSR_EL1_DL_SHIFT 19 299 #define SYS_PMBSR_EL1_EC_SHIFT 26 300 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL 301 302 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 303 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 304 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 305 306 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 307 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 308 309 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 310 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 311 312 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 313 314 /*** End of Statistical Profiling Extension ***/ 315 316 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 317 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 318 319 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 320 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 321 322 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) 323 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) 324 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) 325 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) 326 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) 327 328 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 329 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 330 331 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 332 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 333 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 334 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 335 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 336 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 337 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 338 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 339 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 340 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 341 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 342 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 343 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 344 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 345 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 346 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 347 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 348 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 349 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 350 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 351 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 352 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 353 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 354 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 355 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 356 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 357 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 358 359 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 360 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 361 362 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 363 364 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) 365 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 366 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 367 368 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 369 370 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 371 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 372 373 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 374 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 375 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 376 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 377 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 378 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 379 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 380 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 381 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 382 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 383 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 384 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 385 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 386 387 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 388 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 389 390 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 391 392 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 393 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 394 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 395 396 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 397 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 398 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 399 400 #define __PMEV_op2(n) ((n) & 0x7) 401 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 402 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 403 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 404 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 405 406 #define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7) 407 408 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 409 410 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 411 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 412 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 413 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 414 415 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 416 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 417 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 418 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 419 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 420 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 421 422 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 423 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 424 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 425 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 426 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 427 428 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 429 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 430 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 431 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 432 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 433 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 434 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 435 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 436 437 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 438 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 439 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 440 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 441 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 442 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 443 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 444 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 445 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 446 447 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 448 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 449 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 450 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 451 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 452 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 453 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 454 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 455 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 456 457 /* Common SCTLR_ELx flags. */ 458 #define SCTLR_ELx_DSSBS (_BITUL(44)) 459 #define SCTLR_ELx_ENIA (_BITUL(31)) 460 #define SCTLR_ELx_ENIB (_BITUL(30)) 461 #define SCTLR_ELx_ENDA (_BITUL(27)) 462 #define SCTLR_ELx_EE (_BITUL(25)) 463 #define SCTLR_ELx_IESB (_BITUL(21)) 464 #define SCTLR_ELx_WXN (_BITUL(19)) 465 #define SCTLR_ELx_ENDB (_BITUL(13)) 466 #define SCTLR_ELx_I (_BITUL(12)) 467 #define SCTLR_ELx_SA (_BITUL(3)) 468 #define SCTLR_ELx_C (_BITUL(2)) 469 #define SCTLR_ELx_A (_BITUL(1)) 470 #define SCTLR_ELx_M (_BITUL(0)) 471 472 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 473 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB) 474 475 /* SCTLR_EL2 specific flags. */ 476 #define SCTLR_EL2_RES1 ((_BITUL(4)) | (_BITUL(5)) | (_BITUL(11)) | (_BITUL(16)) | \ 477 (_BITUL(18)) | (_BITUL(22)) | (_BITUL(23)) | (_BITUL(28)) | \ 478 (_BITUL(29))) 479 #define SCTLR_EL2_RES0 ((_BITUL(6)) | (_BITUL(7)) | (_BITUL(8)) | (_BITUL(9)) | \ 480 (_BITUL(10)) | (_BITUL(13)) | (_BITUL(14)) | (_BITUL(15)) | \ 481 (_BITUL(17)) | (_BITUL(20)) | (_BITUL(24)) | (_BITUL(26)) | \ 482 (_BITUL(27)) | (_BITUL(30)) | (_BITUL(31)) | \ 483 (0xffffefffUL << 32)) 484 485 #ifdef CONFIG_CPU_BIG_ENDIAN 486 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 487 #define ENDIAN_CLEAR_EL2 0 488 #else 489 #define ENDIAN_SET_EL2 0 490 #define ENDIAN_CLEAR_EL2 SCTLR_ELx_EE 491 #endif 492 493 /* SCTLR_EL2 value used for the hyp-stub */ 494 #define SCTLR_EL2_SET (SCTLR_ELx_IESB | ENDIAN_SET_EL2 | SCTLR_EL2_RES1) 495 #define SCTLR_EL2_CLEAR (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 496 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \ 497 SCTLR_ELx_DSSBS | ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0) 498 499 #if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffffUL 500 #error "Inconsistent SCTLR_EL2 set/clear bits" 501 #endif 502 503 /* SCTLR_EL1 specific flags. */ 504 #define SCTLR_EL1_UCI (_BITUL(26)) 505 #define SCTLR_EL1_E0E (_BITUL(24)) 506 #define SCTLR_EL1_SPAN (_BITUL(23)) 507 #define SCTLR_EL1_NTWE (_BITUL(18)) 508 #define SCTLR_EL1_NTWI (_BITUL(16)) 509 #define SCTLR_EL1_UCT (_BITUL(15)) 510 #define SCTLR_EL1_DZE (_BITUL(14)) 511 #define SCTLR_EL1_UMA (_BITUL(9)) 512 #define SCTLR_EL1_SED (_BITUL(8)) 513 #define SCTLR_EL1_ITD (_BITUL(7)) 514 #define SCTLR_EL1_CP15BEN (_BITUL(5)) 515 #define SCTLR_EL1_SA0 (_BITUL(4)) 516 517 #define SCTLR_EL1_RES1 ((_BITUL(11)) | (_BITUL(20)) | (_BITUL(22)) | (_BITUL(28)) | \ 518 (_BITUL(29))) 519 #define SCTLR_EL1_RES0 ((_BITUL(6)) | (_BITUL(10)) | (_BITUL(13)) | (_BITUL(17)) | \ 520 (_BITUL(27)) | (_BITUL(30)) | (_BITUL(31)) | \ 521 (0xffffefffUL << 32)) 522 523 #ifdef CONFIG_CPU_BIG_ENDIAN 524 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 525 #define ENDIAN_CLEAR_EL1 0 526 #else 527 #define ENDIAN_SET_EL1 0 528 #define ENDIAN_CLEAR_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 529 #endif 530 531 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\ 532 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\ 533 SCTLR_EL1_DZE | SCTLR_EL1_UCT |\ 534 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\ 535 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1) 536 #define SCTLR_EL1_CLEAR (SCTLR_ELx_A | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD |\ 537 SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\ 538 SCTLR_ELx_DSSBS | SCTLR_EL1_NTWI | SCTLR_EL1_RES0) 539 540 #if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffffUL 541 #error "Inconsistent SCTLR_EL1 set/clear bits" 542 #endif 543 544 /* id_aa64isar0 */ 545 #define ID_AA64ISAR0_TS_SHIFT 52 546 #define ID_AA64ISAR0_FHM_SHIFT 48 547 #define ID_AA64ISAR0_DP_SHIFT 44 548 #define ID_AA64ISAR0_SM4_SHIFT 40 549 #define ID_AA64ISAR0_SM3_SHIFT 36 550 #define ID_AA64ISAR0_SHA3_SHIFT 32 551 #define ID_AA64ISAR0_RDM_SHIFT 28 552 #define ID_AA64ISAR0_ATOMICS_SHIFT 20 553 #define ID_AA64ISAR0_CRC32_SHIFT 16 554 #define ID_AA64ISAR0_SHA2_SHIFT 12 555 #define ID_AA64ISAR0_SHA1_SHIFT 8 556 #define ID_AA64ISAR0_AES_SHIFT 4 557 558 /* id_aa64isar1 */ 559 #define ID_AA64ISAR1_SB_SHIFT 36 560 #define ID_AA64ISAR1_GPI_SHIFT 28 561 #define ID_AA64ISAR1_GPA_SHIFT 24 562 #define ID_AA64ISAR1_LRCPC_SHIFT 20 563 #define ID_AA64ISAR1_FCMA_SHIFT 16 564 #define ID_AA64ISAR1_JSCVT_SHIFT 12 565 #define ID_AA64ISAR1_API_SHIFT 8 566 #define ID_AA64ISAR1_APA_SHIFT 4 567 #define ID_AA64ISAR1_DPB_SHIFT 0 568 569 #define ID_AA64ISAR1_APA_NI 0x0 570 #define ID_AA64ISAR1_APA_ARCHITECTED 0x1 571 #define ID_AA64ISAR1_API_NI 0x0 572 #define ID_AA64ISAR1_API_IMP_DEF 0x1 573 #define ID_AA64ISAR1_GPA_NI 0x0 574 #define ID_AA64ISAR1_GPA_ARCHITECTED 0x1 575 #define ID_AA64ISAR1_GPI_NI 0x0 576 #define ID_AA64ISAR1_GPI_IMP_DEF 0x1 577 578 /* id_aa64pfr0 */ 579 #define ID_AA64PFR0_CSV3_SHIFT 60 580 #define ID_AA64PFR0_CSV2_SHIFT 56 581 #define ID_AA64PFR0_DIT_SHIFT 48 582 #define ID_AA64PFR0_SVE_SHIFT 32 583 #define ID_AA64PFR0_RAS_SHIFT 28 584 #define ID_AA64PFR0_GIC_SHIFT 24 585 #define ID_AA64PFR0_ASIMD_SHIFT 20 586 #define ID_AA64PFR0_FP_SHIFT 16 587 #define ID_AA64PFR0_EL3_SHIFT 12 588 #define ID_AA64PFR0_EL2_SHIFT 8 589 #define ID_AA64PFR0_EL1_SHIFT 4 590 #define ID_AA64PFR0_EL0_SHIFT 0 591 592 #define ID_AA64PFR0_SVE 0x1 593 #define ID_AA64PFR0_RAS_V1 0x1 594 #define ID_AA64PFR0_FP_NI 0xf 595 #define ID_AA64PFR0_FP_SUPPORTED 0x0 596 #define ID_AA64PFR0_ASIMD_NI 0xf 597 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 598 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 599 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 600 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 601 602 /* id_aa64pfr1 */ 603 #define ID_AA64PFR1_SSBS_SHIFT 4 604 605 #define ID_AA64PFR1_SSBS_PSTATE_NI 0 606 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 607 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 608 609 /* id_aa64mmfr0 */ 610 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 611 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 612 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 613 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 614 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 615 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 616 #define ID_AA64MMFR0_ASID_SHIFT 4 617 #define ID_AA64MMFR0_PARANGE_SHIFT 0 618 619 #define ID_AA64MMFR0_TGRAN4_NI 0xf 620 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 621 #define ID_AA64MMFR0_TGRAN64_NI 0xf 622 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 623 #define ID_AA64MMFR0_TGRAN16_NI 0x0 624 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 625 #define ID_AA64MMFR0_PARANGE_48 0x5 626 #define ID_AA64MMFR0_PARANGE_52 0x6 627 628 #ifdef CONFIG_ARM64_PA_BITS_52 629 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 630 #else 631 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48 632 #endif 633 634 /* id_aa64mmfr1 */ 635 #define ID_AA64MMFR1_PAN_SHIFT 20 636 #define ID_AA64MMFR1_LOR_SHIFT 16 637 #define ID_AA64MMFR1_HPD_SHIFT 12 638 #define ID_AA64MMFR1_VHE_SHIFT 8 639 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 640 #define ID_AA64MMFR1_HADBS_SHIFT 0 641 642 #define ID_AA64MMFR1_VMIDBITS_8 0 643 #define ID_AA64MMFR1_VMIDBITS_16 2 644 645 /* id_aa64mmfr2 */ 646 #define ID_AA64MMFR2_FWB_SHIFT 40 647 #define ID_AA64MMFR2_AT_SHIFT 32 648 #define ID_AA64MMFR2_LVA_SHIFT 16 649 #define ID_AA64MMFR2_IESB_SHIFT 12 650 #define ID_AA64MMFR2_LSM_SHIFT 8 651 #define ID_AA64MMFR2_UAO_SHIFT 4 652 #define ID_AA64MMFR2_CNP_SHIFT 0 653 654 /* id_aa64dfr0 */ 655 #define ID_AA64DFR0_PMSVER_SHIFT 32 656 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 657 #define ID_AA64DFR0_WRPS_SHIFT 20 658 #define ID_AA64DFR0_BRPS_SHIFT 12 659 #define ID_AA64DFR0_PMUVER_SHIFT 8 660 #define ID_AA64DFR0_TRACEVER_SHIFT 4 661 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 662 663 #define ID_ISAR5_RDM_SHIFT 24 664 #define ID_ISAR5_CRC32_SHIFT 16 665 #define ID_ISAR5_SHA2_SHIFT 12 666 #define ID_ISAR5_SHA1_SHIFT 8 667 #define ID_ISAR5_AES_SHIFT 4 668 #define ID_ISAR5_SEVL_SHIFT 0 669 670 #define MVFR0_FPROUND_SHIFT 28 671 #define MVFR0_FPSHVEC_SHIFT 24 672 #define MVFR0_FPSQRT_SHIFT 20 673 #define MVFR0_FPDIVIDE_SHIFT 16 674 #define MVFR0_FPTRAP_SHIFT 12 675 #define MVFR0_FPDP_SHIFT 8 676 #define MVFR0_FPSP_SHIFT 4 677 #define MVFR0_SIMD_SHIFT 0 678 679 #define MVFR1_SIMDFMAC_SHIFT 28 680 #define MVFR1_FPHP_SHIFT 24 681 #define MVFR1_SIMDHP_SHIFT 20 682 #define MVFR1_SIMDSP_SHIFT 16 683 #define MVFR1_SIMDINT_SHIFT 12 684 #define MVFR1_SIMDLS_SHIFT 8 685 #define MVFR1_FPDNAN_SHIFT 4 686 #define MVFR1_FPFTZ_SHIFT 0 687 688 689 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 690 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 691 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 692 693 #define ID_AA64MMFR0_TGRAN4_NI 0xf 694 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 695 #define ID_AA64MMFR0_TGRAN64_NI 0xf 696 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 697 #define ID_AA64MMFR0_TGRAN16_NI 0x0 698 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 699 700 #if defined(CONFIG_ARM64_4K_PAGES) 701 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 702 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED 703 #elif defined(CONFIG_ARM64_16K_PAGES) 704 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 705 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED 706 #elif defined(CONFIG_ARM64_64K_PAGES) 707 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 708 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED 709 #endif 710 711 712 /* 713 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which 714 * are reserved by the SVE architecture for future expansion of the LEN 715 * field, with compatible semantics. 716 */ 717 #define ZCR_ELx_LEN_SHIFT 0 718 #define ZCR_ELx_LEN_SIZE 9 719 #define ZCR_ELx_LEN_MASK 0x1ff 720 721 #define CPACR_EL1_ZEN_EL1EN (_BITUL(16)) /* enable EL1 access */ 722 #define CPACR_EL1_ZEN_EL0EN (_BITUL(17)) /* enable EL0 access, if EL1EN set */ 723 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) 724 725 726 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 727 #define SYS_MPIDR_SAFE_VAL (_BITUL(31)) 728 729 #ifdef __ASSEMBLY__ 730 731 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 732 .equ .L__reg_num_x\num, \num 733 .endr 734 .equ .L__reg_num_xzr, 31 735 736 .macro mrs_s, rt, sreg 737 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 738 .endm 739 740 .macro msr_s, sreg, rt 741 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 742 .endm 743 744 #else 745 746 #include <linux/build_bug.h> 747 #include <linux/types.h> 748 749 asm( 750 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" 751 " .equ .L__reg_num_x\\num, \\num\n" 752 " .endr\n" 753 " .equ .L__reg_num_xzr, 31\n" 754 "\n" 755 " .macro mrs_s, rt, sreg\n" 756 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) 757 " .endm\n" 758 "\n" 759 " .macro msr_s, sreg, rt\n" 760 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) 761 " .endm\n" 762 ); 763 764 /* 765 * Unlike read_cpuid, calls to read_sysreg are never expected to be 766 * optimized away or replaced with synthetic values. 767 */ 768 #define read_sysreg(r) ({ \ 769 u64 __val; \ 770 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 771 __val; \ 772 }) 773 774 /* 775 * The "Z" constraint normally means a zero immediate, but when combined with 776 * the "%x0" template means XZR. 777 */ 778 #define write_sysreg(v, r) do { \ 779 u64 __val = (u64)(v); \ 780 asm volatile("msr " __stringify(r) ", %x0" \ 781 : : "rZ" (__val)); \ 782 } while (0) 783 784 /* 785 * For registers without architectural names, or simply unsupported by 786 * GAS. 787 */ 788 #define read_sysreg_s(r) ({ \ 789 u64 __val; \ 790 asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \ 791 __val; \ 792 }) 793 794 #define write_sysreg_s(v, r) do { \ 795 u64 __val = (u64)(v); \ 796 asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \ 797 } while (0) 798 799 /* 800 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 801 * set mask are set. Other bits are left as-is. 802 */ 803 #define sysreg_clear_set(sysreg, clear, set) do { \ 804 u64 __scs_val = read_sysreg(sysreg); \ 805 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 806 if (__scs_new != __scs_val) \ 807 write_sysreg(__scs_new, sysreg); \ 808 } while (0) 809 810 #endif 811 812 #endif /* __ASM_SYSREG_H */ 813