1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #ifndef __ASM_SYSREG_H 10 #define __ASM_SYSREG_H 11 12 #include <linux/bits.h> 13 #include <linux/stringify.h> 14 15 /* 16 * ARMv8 ARM reserves the following encoding for system registers: 17 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 18 * C5.2, version:ARM DDI 0487A.f) 19 * [20-19] : Op0 20 * [18-16] : Op1 21 * [15-12] : CRn 22 * [11-8] : CRm 23 * [7-5] : Op2 24 */ 25 #define Op0_shift 19 26 #define Op0_mask 0x3 27 #define Op1_shift 16 28 #define Op1_mask 0x7 29 #define CRn_shift 12 30 #define CRn_mask 0xf 31 #define CRm_shift 8 32 #define CRm_mask 0xf 33 #define Op2_shift 5 34 #define Op2_mask 0x7 35 36 #define sys_reg(op0, op1, crn, crm, op2) \ 37 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 38 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 39 ((op2) << Op2_shift)) 40 41 #define sys_insn sys_reg 42 43 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 44 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 45 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 46 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 47 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 48 49 #ifndef CONFIG_BROKEN_GAS_INST 50 51 #ifdef __ASSEMBLY__ 52 // The space separator is omitted so that __emit_inst(x) can be parsed as 53 // either an assembler directive or an assembler macro argument. 54 #define __emit_inst(x) .inst(x) 55 #else 56 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 57 #endif 58 59 #else /* CONFIG_BROKEN_GAS_INST */ 60 61 #ifndef CONFIG_CPU_BIG_ENDIAN 62 #define __INSTR_BSWAP(x) (x) 63 #else /* CONFIG_CPU_BIG_ENDIAN */ 64 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 65 (((x) << 8) & 0x00ff0000) | \ 66 (((x) >> 8) & 0x0000ff00) | \ 67 (((x) >> 24) & 0x000000ff)) 68 #endif /* CONFIG_CPU_BIG_ENDIAN */ 69 70 #ifdef __ASSEMBLY__ 71 #define __emit_inst(x) .long __INSTR_BSWAP(x) 72 #else /* __ASSEMBLY__ */ 73 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 74 #endif /* __ASSEMBLY__ */ 75 76 #endif /* CONFIG_BROKEN_GAS_INST */ 77 78 /* 79 * Instructions for modifying PSTATE fields. 80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 81 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 82 * for accessing PSTATE fields have the following encoding: 83 * Op0 = 0, CRn = 4 84 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 85 * CRm = Imm4 for the instruction. 86 * Rt = 0x1f 87 */ 88 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 89 #define PSTATE_Imm_shift CRm_shift 90 91 #define PSTATE_PAN pstate_field(0, 4) 92 #define PSTATE_UAO pstate_field(0, 3) 93 #define PSTATE_SSBS pstate_field(3, 1) 94 #define PSTATE_TCO pstate_field(3, 4) 95 96 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) 97 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) 98 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) 99 #define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift)) 100 101 #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) 102 #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) 103 #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x)) 104 105 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ 106 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) 107 108 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) 109 110 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 111 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 112 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 113 114 /* 115 * System registers, organised loosely by encoding but grouped together 116 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. 117 */ 118 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 119 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 120 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 121 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 122 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 123 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 124 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 125 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 126 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 127 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 128 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 129 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 130 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 131 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 132 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 133 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 134 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 135 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 136 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 137 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 138 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 139 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 140 141 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 142 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 143 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 144 145 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 146 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 147 #define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) 148 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 149 #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5) 150 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 151 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 152 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 153 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 154 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 155 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 156 #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) 157 158 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 159 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 160 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 161 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 162 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 163 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 164 #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) 165 166 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 167 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 168 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 169 170 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 171 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 172 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) 173 174 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 175 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 176 177 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 178 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 179 180 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 181 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 182 183 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 184 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 185 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 186 187 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 188 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 189 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 190 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) 191 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) 192 193 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) 194 #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) 195 196 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 197 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 198 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 199 200 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 201 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 202 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 203 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 204 205 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 206 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 207 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 208 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 209 210 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 211 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 212 213 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) 214 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) 215 216 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 217 218 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 219 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 220 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 221 222 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 223 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 224 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 225 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 226 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 227 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 228 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 229 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 230 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0) 231 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1) 232 233 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 234 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 235 236 #define SYS_PAR_EL1_F BIT(0) 237 #define SYS_PAR_EL1_FST GENMASK(6, 1) 238 239 /*** Statistical Profiling Extension ***/ 240 /* ID registers */ 241 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 242 #define SYS_PMSIDR_EL1_FE_SHIFT 0 243 #define SYS_PMSIDR_EL1_FT_SHIFT 1 244 #define SYS_PMSIDR_EL1_FL_SHIFT 2 245 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 246 #define SYS_PMSIDR_EL1_LDS_SHIFT 4 247 #define SYS_PMSIDR_EL1_ERND_SHIFT 5 248 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 249 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 250 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 251 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 252 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 253 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 254 255 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 256 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 257 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 258 #define SYS_PMBIDR_EL1_P_SHIFT 4 259 #define SYS_PMBIDR_EL1_F_SHIFT 5 260 261 /* Sampling controls */ 262 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 263 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0 264 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1 265 #define SYS_PMSCR_EL1_CX_SHIFT 3 266 #define SYS_PMSCR_EL1_PA_SHIFT 4 267 #define SYS_PMSCR_EL1_TS_SHIFT 5 268 #define SYS_PMSCR_EL1_PCT_SHIFT 6 269 270 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 271 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 272 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1 273 #define SYS_PMSCR_EL2_CX_SHIFT 3 274 #define SYS_PMSCR_EL2_PA_SHIFT 4 275 #define SYS_PMSCR_EL2_TS_SHIFT 5 276 #define SYS_PMSCR_EL2_PCT_SHIFT 6 277 278 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 279 280 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 281 #define SYS_PMSIRR_EL1_RND_SHIFT 0 282 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 283 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 284 285 /* Filtering controls */ 286 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 287 #define SYS_PMSFCR_EL1_FE_SHIFT 0 288 #define SYS_PMSFCR_EL1_FT_SHIFT 1 289 #define SYS_PMSFCR_EL1_FL_SHIFT 2 290 #define SYS_PMSFCR_EL1_B_SHIFT 16 291 #define SYS_PMSFCR_EL1_LD_SHIFT 17 292 #define SYS_PMSFCR_EL1_ST_SHIFT 18 293 294 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 295 #define SYS_PMSEVFR_EL1_RES0_8_2 \ 296 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ 297 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) 298 #define SYS_PMSEVFR_EL1_RES0_8_3 \ 299 (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) 300 301 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 302 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 303 304 /* Buffer controls */ 305 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 306 #define SYS_PMBLIMITR_EL1_E_SHIFT 0 307 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1 308 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 309 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 310 311 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 312 313 /* Buffer error reporting */ 314 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 315 #define SYS_PMBSR_EL1_COLL_SHIFT 16 316 #define SYS_PMBSR_EL1_S_SHIFT 17 317 #define SYS_PMBSR_EL1_EA_SHIFT 18 318 #define SYS_PMBSR_EL1_DL_SHIFT 19 319 #define SYS_PMBSR_EL1_EC_SHIFT 26 320 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL 321 322 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 323 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 324 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 325 326 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 327 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 328 329 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 330 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 331 332 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 333 334 /*** End of Statistical Profiling Extension ***/ 335 336 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 337 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 338 339 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6) 340 341 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 342 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 343 344 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) 345 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) 346 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) 347 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) 348 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) 349 350 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 351 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 352 353 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 354 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 355 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 356 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 357 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 358 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 359 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 360 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 361 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 362 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 363 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 364 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 365 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 366 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 367 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 368 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 369 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 370 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 371 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 372 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 373 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 374 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 375 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 376 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 377 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 378 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 379 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 380 381 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 382 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 383 384 #define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7) 385 386 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 387 388 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) 389 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 390 #define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4) 391 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 392 393 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 394 395 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 396 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 397 398 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) 399 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) 400 401 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 402 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 403 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 404 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 405 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 406 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 407 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 408 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 409 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 410 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 411 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 412 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 413 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 414 415 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 416 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 417 418 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7) 419 420 /* Definitions for system register interface to AMU for ARMv8.4 onwards */ 421 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) 422 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) 423 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) 424 #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) 425 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) 426 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) 427 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) 428 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) 429 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) 430 431 /* 432 * Group 0 of activity monitors (architected): 433 * op0 op1 CRn CRm op2 434 * Counter: 11 011 1101 010:n<3> n<2:0> 435 * Type: 11 011 1101 011:n<3> n<2:0> 436 * n: 0-15 437 * 438 * Group 1 of activity monitors (auxiliary): 439 * op0 op1 CRn CRm op2 440 * Counter: 11 011 1101 110:n<3> n<2:0> 441 * Type: 11 011 1101 111:n<3> n<2:0> 442 * n: 0-15 443 */ 444 445 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) 446 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) 447 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) 448 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) 449 450 /* AMU v1: Fixed (architecturally defined) activity monitors */ 451 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) 452 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) 453 #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) 454 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) 455 456 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 457 458 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 459 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 460 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 461 462 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) 463 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) 464 465 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 466 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 467 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 468 469 #define __PMEV_op2(n) ((n) & 0x7) 470 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 471 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 472 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 473 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 474 475 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) 476 477 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) 478 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 479 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) 480 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 481 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) 482 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) 483 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 484 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) 485 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 486 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 487 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0) 488 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) 489 490 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 491 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 492 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 493 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 494 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 495 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 496 497 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 498 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 499 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 500 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 501 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 502 503 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 504 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 505 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 506 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 507 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 508 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 509 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 510 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 511 512 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 513 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 514 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 515 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 516 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 517 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 518 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 519 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 520 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 521 522 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 523 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 524 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 525 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 526 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 527 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 528 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 529 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 530 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 531 532 /* VHE encodings for architectural EL0/1 system registers */ 533 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) 534 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) 535 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) 536 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) 537 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) 538 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) 539 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) 540 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) 541 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) 542 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) 543 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) 544 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) 545 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) 546 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) 547 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) 548 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) 549 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) 550 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) 551 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) 552 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) 553 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) 554 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) 555 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) 556 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) 557 558 /* Common SCTLR_ELx flags. */ 559 #define SCTLR_ELx_DSSBS (BIT(44)) 560 #define SCTLR_ELx_ATA (BIT(43)) 561 562 #define SCTLR_ELx_TCF_SHIFT 40 563 #define SCTLR_ELx_TCF_NONE (UL(0x0) << SCTLR_ELx_TCF_SHIFT) 564 #define SCTLR_ELx_TCF_SYNC (UL(0x1) << SCTLR_ELx_TCF_SHIFT) 565 #define SCTLR_ELx_TCF_ASYNC (UL(0x2) << SCTLR_ELx_TCF_SHIFT) 566 #define SCTLR_ELx_TCF_MASK (UL(0x3) << SCTLR_ELx_TCF_SHIFT) 567 568 #define SCTLR_ELx_ITFSB (BIT(37)) 569 #define SCTLR_ELx_ENIA (BIT(31)) 570 #define SCTLR_ELx_ENIB (BIT(30)) 571 #define SCTLR_ELx_ENDA (BIT(27)) 572 #define SCTLR_ELx_EE (BIT(25)) 573 #define SCTLR_ELx_IESB (BIT(21)) 574 #define SCTLR_ELx_WXN (BIT(19)) 575 #define SCTLR_ELx_ENDB (BIT(13)) 576 #define SCTLR_ELx_I (BIT(12)) 577 #define SCTLR_ELx_SA (BIT(3)) 578 #define SCTLR_ELx_C (BIT(2)) 579 #define SCTLR_ELx_A (BIT(1)) 580 #define SCTLR_ELx_M (BIT(0)) 581 582 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 583 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB) 584 585 /* SCTLR_EL2 specific flags. */ 586 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 587 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 588 (BIT(29))) 589 590 #ifdef CONFIG_CPU_BIG_ENDIAN 591 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 592 #else 593 #define ENDIAN_SET_EL2 0 594 #endif 595 596 #define INIT_SCTLR_EL2_MMU_OFF \ 597 (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) 598 599 /* SCTLR_EL1 specific flags. */ 600 #define SCTLR_EL1_ATA0 (BIT(42)) 601 602 #define SCTLR_EL1_TCF0_SHIFT 38 603 #define SCTLR_EL1_TCF0_NONE (UL(0x0) << SCTLR_EL1_TCF0_SHIFT) 604 #define SCTLR_EL1_TCF0_SYNC (UL(0x1) << SCTLR_EL1_TCF0_SHIFT) 605 #define SCTLR_EL1_TCF0_ASYNC (UL(0x2) << SCTLR_EL1_TCF0_SHIFT) 606 #define SCTLR_EL1_TCF0_MASK (UL(0x3) << SCTLR_EL1_TCF0_SHIFT) 607 608 #define SCTLR_EL1_BT1 (BIT(36)) 609 #define SCTLR_EL1_BT0 (BIT(35)) 610 #define SCTLR_EL1_UCI (BIT(26)) 611 #define SCTLR_EL1_E0E (BIT(24)) 612 #define SCTLR_EL1_SPAN (BIT(23)) 613 #define SCTLR_EL1_NTWE (BIT(18)) 614 #define SCTLR_EL1_NTWI (BIT(16)) 615 #define SCTLR_EL1_UCT (BIT(15)) 616 #define SCTLR_EL1_DZE (BIT(14)) 617 #define SCTLR_EL1_UMA (BIT(9)) 618 #define SCTLR_EL1_SED (BIT(8)) 619 #define SCTLR_EL1_ITD (BIT(7)) 620 #define SCTLR_EL1_CP15BEN (BIT(5)) 621 #define SCTLR_EL1_SA0 (BIT(4)) 622 623 #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \ 624 (BIT(29))) 625 626 #ifdef CONFIG_CPU_BIG_ENDIAN 627 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 628 #else 629 #define ENDIAN_SET_EL1 0 630 #endif 631 632 #define INIT_SCTLR_EL1_MMU_OFF \ 633 (ENDIAN_SET_EL1 | SCTLR_EL1_RES1) 634 635 #define INIT_SCTLR_EL1_MMU_ON \ 636 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_EL1_SA0 | \ 637 SCTLR_EL1_SED | SCTLR_ELx_I | SCTLR_EL1_DZE | SCTLR_EL1_UCT | \ 638 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \ 639 SCTLR_ELx_ATA | SCTLR_EL1_ATA0 | ENDIAN_SET_EL1 | SCTLR_EL1_UCI | \ 640 SCTLR_EL1_RES1) 641 642 /* MAIR_ELx memory attributes (used by Linux) */ 643 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) 644 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) 645 #define MAIR_ATTR_DEVICE_GRE UL(0x0c) 646 #define MAIR_ATTR_NORMAL_NC UL(0x44) 647 #define MAIR_ATTR_NORMAL_WT UL(0xbb) 648 #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0) 649 #define MAIR_ATTR_NORMAL UL(0xff) 650 #define MAIR_ATTR_MASK UL(0xff) 651 652 /* Position the attr at the correct index */ 653 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) 654 655 /* id_aa64isar0 */ 656 #define ID_AA64ISAR0_RNDR_SHIFT 60 657 #define ID_AA64ISAR0_TLB_SHIFT 56 658 #define ID_AA64ISAR0_TS_SHIFT 52 659 #define ID_AA64ISAR0_FHM_SHIFT 48 660 #define ID_AA64ISAR0_DP_SHIFT 44 661 #define ID_AA64ISAR0_SM4_SHIFT 40 662 #define ID_AA64ISAR0_SM3_SHIFT 36 663 #define ID_AA64ISAR0_SHA3_SHIFT 32 664 #define ID_AA64ISAR0_RDM_SHIFT 28 665 #define ID_AA64ISAR0_ATOMICS_SHIFT 20 666 #define ID_AA64ISAR0_CRC32_SHIFT 16 667 #define ID_AA64ISAR0_SHA2_SHIFT 12 668 #define ID_AA64ISAR0_SHA1_SHIFT 8 669 #define ID_AA64ISAR0_AES_SHIFT 4 670 671 #define ID_AA64ISAR0_TLB_RANGE_NI 0x0 672 #define ID_AA64ISAR0_TLB_RANGE 0x2 673 674 /* id_aa64isar1 */ 675 #define ID_AA64ISAR1_I8MM_SHIFT 52 676 #define ID_AA64ISAR1_DGH_SHIFT 48 677 #define ID_AA64ISAR1_BF16_SHIFT 44 678 #define ID_AA64ISAR1_SPECRES_SHIFT 40 679 #define ID_AA64ISAR1_SB_SHIFT 36 680 #define ID_AA64ISAR1_FRINTTS_SHIFT 32 681 #define ID_AA64ISAR1_GPI_SHIFT 28 682 #define ID_AA64ISAR1_GPA_SHIFT 24 683 #define ID_AA64ISAR1_LRCPC_SHIFT 20 684 #define ID_AA64ISAR1_FCMA_SHIFT 16 685 #define ID_AA64ISAR1_JSCVT_SHIFT 12 686 #define ID_AA64ISAR1_API_SHIFT 8 687 #define ID_AA64ISAR1_APA_SHIFT 4 688 #define ID_AA64ISAR1_DPB_SHIFT 0 689 690 #define ID_AA64ISAR1_APA_NI 0x0 691 #define ID_AA64ISAR1_APA_ARCHITECTED 0x1 692 #define ID_AA64ISAR1_APA_ARCH_EPAC 0x2 693 #define ID_AA64ISAR1_APA_ARCH_EPAC2 0x3 694 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC 0x4 695 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB 0x5 696 #define ID_AA64ISAR1_API_NI 0x0 697 #define ID_AA64ISAR1_API_IMP_DEF 0x1 698 #define ID_AA64ISAR1_API_IMP_DEF_EPAC 0x2 699 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2 0x3 700 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC 0x4 701 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB 0x5 702 #define ID_AA64ISAR1_GPA_NI 0x0 703 #define ID_AA64ISAR1_GPA_ARCHITECTED 0x1 704 #define ID_AA64ISAR1_GPI_NI 0x0 705 #define ID_AA64ISAR1_GPI_IMP_DEF 0x1 706 707 /* id_aa64pfr0 */ 708 #define ID_AA64PFR0_CSV3_SHIFT 60 709 #define ID_AA64PFR0_CSV2_SHIFT 56 710 #define ID_AA64PFR0_DIT_SHIFT 48 711 #define ID_AA64PFR0_AMU_SHIFT 44 712 #define ID_AA64PFR0_MPAM_SHIFT 40 713 #define ID_AA64PFR0_SEL2_SHIFT 36 714 #define ID_AA64PFR0_SVE_SHIFT 32 715 #define ID_AA64PFR0_RAS_SHIFT 28 716 #define ID_AA64PFR0_GIC_SHIFT 24 717 #define ID_AA64PFR0_ASIMD_SHIFT 20 718 #define ID_AA64PFR0_FP_SHIFT 16 719 #define ID_AA64PFR0_EL3_SHIFT 12 720 #define ID_AA64PFR0_EL2_SHIFT 8 721 #define ID_AA64PFR0_EL1_SHIFT 4 722 #define ID_AA64PFR0_EL0_SHIFT 0 723 724 #define ID_AA64PFR0_AMU 0x1 725 #define ID_AA64PFR0_SVE 0x1 726 #define ID_AA64PFR0_RAS_V1 0x1 727 #define ID_AA64PFR0_FP_NI 0xf 728 #define ID_AA64PFR0_FP_SUPPORTED 0x0 729 #define ID_AA64PFR0_ASIMD_NI 0xf 730 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 731 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 732 #define ID_AA64PFR0_EL1_32BIT_64BIT 0x2 733 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 734 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 735 736 /* id_aa64pfr1 */ 737 #define ID_AA64PFR1_MPAMFRAC_SHIFT 16 738 #define ID_AA64PFR1_RASFRAC_SHIFT 12 739 #define ID_AA64PFR1_MTE_SHIFT 8 740 #define ID_AA64PFR1_SSBS_SHIFT 4 741 #define ID_AA64PFR1_BT_SHIFT 0 742 743 #define ID_AA64PFR1_SSBS_PSTATE_NI 0 744 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 745 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 746 #define ID_AA64PFR1_BT_BTI 0x1 747 748 #define ID_AA64PFR1_MTE_NI 0x0 749 #define ID_AA64PFR1_MTE_EL0 0x1 750 #define ID_AA64PFR1_MTE 0x2 751 752 /* id_aa64zfr0 */ 753 #define ID_AA64ZFR0_F64MM_SHIFT 56 754 #define ID_AA64ZFR0_F32MM_SHIFT 52 755 #define ID_AA64ZFR0_I8MM_SHIFT 44 756 #define ID_AA64ZFR0_SM4_SHIFT 40 757 #define ID_AA64ZFR0_SHA3_SHIFT 32 758 #define ID_AA64ZFR0_BF16_SHIFT 20 759 #define ID_AA64ZFR0_BITPERM_SHIFT 16 760 #define ID_AA64ZFR0_AES_SHIFT 4 761 #define ID_AA64ZFR0_SVEVER_SHIFT 0 762 763 #define ID_AA64ZFR0_F64MM 0x1 764 #define ID_AA64ZFR0_F32MM 0x1 765 #define ID_AA64ZFR0_I8MM 0x1 766 #define ID_AA64ZFR0_BF16 0x1 767 #define ID_AA64ZFR0_SM4 0x1 768 #define ID_AA64ZFR0_SHA3 0x1 769 #define ID_AA64ZFR0_BITPERM 0x1 770 #define ID_AA64ZFR0_AES 0x1 771 #define ID_AA64ZFR0_AES_PMULL 0x2 772 #define ID_AA64ZFR0_SVEVER_SVE2 0x1 773 774 /* id_aa64mmfr0 */ 775 #define ID_AA64MMFR0_ECV_SHIFT 60 776 #define ID_AA64MMFR0_FGT_SHIFT 56 777 #define ID_AA64MMFR0_EXS_SHIFT 44 778 #define ID_AA64MMFR0_TGRAN4_2_SHIFT 40 779 #define ID_AA64MMFR0_TGRAN64_2_SHIFT 36 780 #define ID_AA64MMFR0_TGRAN16_2_SHIFT 32 781 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 782 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 783 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 784 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 785 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 786 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 787 #define ID_AA64MMFR0_ASID_SHIFT 4 788 #define ID_AA64MMFR0_PARANGE_SHIFT 0 789 790 #define ID_AA64MMFR0_TGRAN4_NI 0xf 791 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 792 #define ID_AA64MMFR0_TGRAN64_NI 0xf 793 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 794 #define ID_AA64MMFR0_TGRAN16_NI 0x0 795 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 796 #define ID_AA64MMFR0_PARANGE_48 0x5 797 #define ID_AA64MMFR0_PARANGE_52 0x6 798 799 #ifdef CONFIG_ARM64_PA_BITS_52 800 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 801 #else 802 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48 803 #endif 804 805 /* id_aa64mmfr1 */ 806 #define ID_AA64MMFR1_ETS_SHIFT 36 807 #define ID_AA64MMFR1_TWED_SHIFT 32 808 #define ID_AA64MMFR1_XNX_SHIFT 28 809 #define ID_AA64MMFR1_SPECSEI_SHIFT 24 810 #define ID_AA64MMFR1_PAN_SHIFT 20 811 #define ID_AA64MMFR1_LOR_SHIFT 16 812 #define ID_AA64MMFR1_HPD_SHIFT 12 813 #define ID_AA64MMFR1_VHE_SHIFT 8 814 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 815 #define ID_AA64MMFR1_HADBS_SHIFT 0 816 817 #define ID_AA64MMFR1_VMIDBITS_8 0 818 #define ID_AA64MMFR1_VMIDBITS_16 2 819 820 /* id_aa64mmfr2 */ 821 #define ID_AA64MMFR2_E0PD_SHIFT 60 822 #define ID_AA64MMFR2_EVT_SHIFT 56 823 #define ID_AA64MMFR2_BBM_SHIFT 52 824 #define ID_AA64MMFR2_TTL_SHIFT 48 825 #define ID_AA64MMFR2_FWB_SHIFT 40 826 #define ID_AA64MMFR2_IDS_SHIFT 36 827 #define ID_AA64MMFR2_AT_SHIFT 32 828 #define ID_AA64MMFR2_ST_SHIFT 28 829 #define ID_AA64MMFR2_NV_SHIFT 24 830 #define ID_AA64MMFR2_CCIDX_SHIFT 20 831 #define ID_AA64MMFR2_LVA_SHIFT 16 832 #define ID_AA64MMFR2_IESB_SHIFT 12 833 #define ID_AA64MMFR2_LSM_SHIFT 8 834 #define ID_AA64MMFR2_UAO_SHIFT 4 835 #define ID_AA64MMFR2_CNP_SHIFT 0 836 837 /* id_aa64dfr0 */ 838 #define ID_AA64DFR0_TRACE_FILT_SHIFT 40 839 #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 840 #define ID_AA64DFR0_PMSVER_SHIFT 32 841 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 842 #define ID_AA64DFR0_WRPS_SHIFT 20 843 #define ID_AA64DFR0_BRPS_SHIFT 12 844 #define ID_AA64DFR0_PMUVER_SHIFT 8 845 #define ID_AA64DFR0_TRACEVER_SHIFT 4 846 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 847 848 #define ID_AA64DFR0_PMUVER_8_0 0x1 849 #define ID_AA64DFR0_PMUVER_8_1 0x4 850 #define ID_AA64DFR0_PMUVER_8_4 0x5 851 #define ID_AA64DFR0_PMUVER_8_5 0x6 852 #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf 853 854 #define ID_AA64DFR0_PMSVER_8_2 0x1 855 #define ID_AA64DFR0_PMSVER_8_3 0x2 856 857 #define ID_DFR0_PERFMON_SHIFT 24 858 859 #define ID_DFR0_PERFMON_8_0 0x3 860 #define ID_DFR0_PERFMON_8_1 0x4 861 #define ID_DFR0_PERFMON_8_4 0x5 862 #define ID_DFR0_PERFMON_8_5 0x6 863 864 #define ID_ISAR4_SWP_FRAC_SHIFT 28 865 #define ID_ISAR4_PSR_M_SHIFT 24 866 #define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT 20 867 #define ID_ISAR4_BARRIER_SHIFT 16 868 #define ID_ISAR4_SMC_SHIFT 12 869 #define ID_ISAR4_WRITEBACK_SHIFT 8 870 #define ID_ISAR4_WITHSHIFTS_SHIFT 4 871 #define ID_ISAR4_UNPRIV_SHIFT 0 872 873 #define ID_DFR1_MTPMU_SHIFT 0 874 875 #define ID_ISAR0_DIVIDE_SHIFT 24 876 #define ID_ISAR0_DEBUG_SHIFT 20 877 #define ID_ISAR0_COPROC_SHIFT 16 878 #define ID_ISAR0_CMPBRANCH_SHIFT 12 879 #define ID_ISAR0_BITFIELD_SHIFT 8 880 #define ID_ISAR0_BITCOUNT_SHIFT 4 881 #define ID_ISAR0_SWAP_SHIFT 0 882 883 #define ID_ISAR5_RDM_SHIFT 24 884 #define ID_ISAR5_CRC32_SHIFT 16 885 #define ID_ISAR5_SHA2_SHIFT 12 886 #define ID_ISAR5_SHA1_SHIFT 8 887 #define ID_ISAR5_AES_SHIFT 4 888 #define ID_ISAR5_SEVL_SHIFT 0 889 890 #define ID_ISAR6_I8MM_SHIFT 24 891 #define ID_ISAR6_BF16_SHIFT 20 892 #define ID_ISAR6_SPECRES_SHIFT 16 893 #define ID_ISAR6_SB_SHIFT 12 894 #define ID_ISAR6_FHM_SHIFT 8 895 #define ID_ISAR6_DP_SHIFT 4 896 #define ID_ISAR6_JSCVT_SHIFT 0 897 898 #define ID_MMFR0_INNERSHR_SHIFT 28 899 #define ID_MMFR0_FCSE_SHIFT 24 900 #define ID_MMFR0_AUXREG_SHIFT 20 901 #define ID_MMFR0_TCM_SHIFT 16 902 #define ID_MMFR0_SHARELVL_SHIFT 12 903 #define ID_MMFR0_OUTERSHR_SHIFT 8 904 #define ID_MMFR0_PMSA_SHIFT 4 905 #define ID_MMFR0_VMSA_SHIFT 0 906 907 #define ID_MMFR4_EVT_SHIFT 28 908 #define ID_MMFR4_CCIDX_SHIFT 24 909 #define ID_MMFR4_LSM_SHIFT 20 910 #define ID_MMFR4_HPDS_SHIFT 16 911 #define ID_MMFR4_CNP_SHIFT 12 912 #define ID_MMFR4_XNX_SHIFT 8 913 #define ID_MMFR4_AC2_SHIFT 4 914 #define ID_MMFR4_SPECSEI_SHIFT 0 915 916 #define ID_MMFR5_ETS_SHIFT 0 917 918 #define ID_PFR0_DIT_SHIFT 24 919 #define ID_PFR0_CSV2_SHIFT 16 920 #define ID_PFR0_STATE3_SHIFT 12 921 #define ID_PFR0_STATE2_SHIFT 8 922 #define ID_PFR0_STATE1_SHIFT 4 923 #define ID_PFR0_STATE0_SHIFT 0 924 925 #define ID_DFR0_PERFMON_SHIFT 24 926 #define ID_DFR0_MPROFDBG_SHIFT 20 927 #define ID_DFR0_MMAPTRC_SHIFT 16 928 #define ID_DFR0_COPTRC_SHIFT 12 929 #define ID_DFR0_MMAPDBG_SHIFT 8 930 #define ID_DFR0_COPSDBG_SHIFT 4 931 #define ID_DFR0_COPDBG_SHIFT 0 932 933 #define ID_PFR2_SSBS_SHIFT 4 934 #define ID_PFR2_CSV3_SHIFT 0 935 936 #define MVFR0_FPROUND_SHIFT 28 937 #define MVFR0_FPSHVEC_SHIFT 24 938 #define MVFR0_FPSQRT_SHIFT 20 939 #define MVFR0_FPDIVIDE_SHIFT 16 940 #define MVFR0_FPTRAP_SHIFT 12 941 #define MVFR0_FPDP_SHIFT 8 942 #define MVFR0_FPSP_SHIFT 4 943 #define MVFR0_SIMD_SHIFT 0 944 945 #define MVFR1_SIMDFMAC_SHIFT 28 946 #define MVFR1_FPHP_SHIFT 24 947 #define MVFR1_SIMDHP_SHIFT 20 948 #define MVFR1_SIMDSP_SHIFT 16 949 #define MVFR1_SIMDINT_SHIFT 12 950 #define MVFR1_SIMDLS_SHIFT 8 951 #define MVFR1_FPDNAN_SHIFT 4 952 #define MVFR1_FPFTZ_SHIFT 0 953 954 #define ID_PFR1_GIC_SHIFT 28 955 #define ID_PFR1_VIRT_FRAC_SHIFT 24 956 #define ID_PFR1_SEC_FRAC_SHIFT 20 957 #define ID_PFR1_GENTIMER_SHIFT 16 958 #define ID_PFR1_VIRTUALIZATION_SHIFT 12 959 #define ID_PFR1_MPROGMOD_SHIFT 8 960 #define ID_PFR1_SECURITY_SHIFT 4 961 #define ID_PFR1_PROGMOD_SHIFT 0 962 963 #if defined(CONFIG_ARM64_4K_PAGES) 964 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 965 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED 966 #elif defined(CONFIG_ARM64_16K_PAGES) 967 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 968 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED 969 #elif defined(CONFIG_ARM64_64K_PAGES) 970 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 971 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED 972 #endif 973 974 #define MVFR2_FPMISC_SHIFT 4 975 #define MVFR2_SIMDMISC_SHIFT 0 976 977 #define DCZID_DZP_SHIFT 4 978 #define DCZID_BS_SHIFT 0 979 980 /* 981 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which 982 * are reserved by the SVE architecture for future expansion of the LEN 983 * field, with compatible semantics. 984 */ 985 #define ZCR_ELx_LEN_SHIFT 0 986 #define ZCR_ELx_LEN_SIZE 9 987 #define ZCR_ELx_LEN_MASK 0x1ff 988 989 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ 990 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ 991 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) 992 993 /* TCR EL1 Bit Definitions */ 994 #define SYS_TCR_EL1_TCMA1 (BIT(58)) 995 #define SYS_TCR_EL1_TCMA0 (BIT(57)) 996 997 /* GCR_EL1 Definitions */ 998 #define SYS_GCR_EL1_RRND (BIT(16)) 999 #define SYS_GCR_EL1_EXCL_MASK 0xffffUL 1000 1001 /* RGSR_EL1 Definitions */ 1002 #define SYS_RGSR_EL1_TAG_MASK 0xfUL 1003 #define SYS_RGSR_EL1_SEED_SHIFT 8 1004 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL 1005 1006 /* GMID_EL1 field definitions */ 1007 #define SYS_GMID_EL1_BS_SHIFT 0 1008 #define SYS_GMID_EL1_BS_SIZE 4 1009 1010 /* TFSR{,E0}_EL1 bit definitions */ 1011 #define SYS_TFSR_EL1_TF0_SHIFT 0 1012 #define SYS_TFSR_EL1_TF1_SHIFT 1 1013 #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) 1014 #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) 1015 1016 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 1017 #define SYS_MPIDR_SAFE_VAL (BIT(31)) 1018 1019 #define TRFCR_ELx_TS_SHIFT 5 1020 #define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) 1021 #define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) 1022 #define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) 1023 #define TRFCR_EL2_CX BIT(3) 1024 #define TRFCR_ELx_ExTRE BIT(1) 1025 #define TRFCR_ELx_E0TRE BIT(0) 1026 1027 #ifdef __ASSEMBLY__ 1028 1029 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 1030 .equ .L__reg_num_x\num, \num 1031 .endr 1032 .equ .L__reg_num_xzr, 31 1033 1034 .macro mrs_s, rt, sreg 1035 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 1036 .endm 1037 1038 .macro msr_s, sreg, rt 1039 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 1040 .endm 1041 1042 #else 1043 1044 #include <linux/build_bug.h> 1045 #include <linux/types.h> 1046 #include <asm/alternative.h> 1047 1048 #define __DEFINE_MRS_MSR_S_REGNUM \ 1049 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \ 1050 " .equ .L__reg_num_x\\num, \\num\n" \ 1051 " .endr\n" \ 1052 " .equ .L__reg_num_xzr, 31\n" 1053 1054 #define DEFINE_MRS_S \ 1055 __DEFINE_MRS_MSR_S_REGNUM \ 1056 " .macro mrs_s, rt, sreg\n" \ 1057 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \ 1058 " .endm\n" 1059 1060 #define DEFINE_MSR_S \ 1061 __DEFINE_MRS_MSR_S_REGNUM \ 1062 " .macro msr_s, sreg, rt\n" \ 1063 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \ 1064 " .endm\n" 1065 1066 #define UNDEFINE_MRS_S \ 1067 " .purgem mrs_s\n" 1068 1069 #define UNDEFINE_MSR_S \ 1070 " .purgem msr_s\n" 1071 1072 #define __mrs_s(v, r) \ 1073 DEFINE_MRS_S \ 1074 " mrs_s " v ", " __stringify(r) "\n" \ 1075 UNDEFINE_MRS_S 1076 1077 #define __msr_s(r, v) \ 1078 DEFINE_MSR_S \ 1079 " msr_s " __stringify(r) ", " v "\n" \ 1080 UNDEFINE_MSR_S 1081 1082 /* 1083 * Unlike read_cpuid, calls to read_sysreg are never expected to be 1084 * optimized away or replaced with synthetic values. 1085 */ 1086 #define read_sysreg(r) ({ \ 1087 u64 __val; \ 1088 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 1089 __val; \ 1090 }) 1091 1092 /* 1093 * The "Z" constraint normally means a zero immediate, but when combined with 1094 * the "%x0" template means XZR. 1095 */ 1096 #define write_sysreg(v, r) do { \ 1097 u64 __val = (u64)(v); \ 1098 asm volatile("msr " __stringify(r) ", %x0" \ 1099 : : "rZ" (__val)); \ 1100 } while (0) 1101 1102 /* 1103 * For registers without architectural names, or simply unsupported by 1104 * GAS. 1105 */ 1106 #define read_sysreg_s(r) ({ \ 1107 u64 __val; \ 1108 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ 1109 __val; \ 1110 }) 1111 1112 #define write_sysreg_s(v, r) do { \ 1113 u64 __val = (u64)(v); \ 1114 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ 1115 } while (0) 1116 1117 /* 1118 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 1119 * set mask are set. Other bits are left as-is. 1120 */ 1121 #define sysreg_clear_set(sysreg, clear, set) do { \ 1122 u64 __scs_val = read_sysreg(sysreg); \ 1123 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1124 if (__scs_new != __scs_val) \ 1125 write_sysreg(__scs_new, sysreg); \ 1126 } while (0) 1127 1128 #define sysreg_clear_set_s(sysreg, clear, set) do { \ 1129 u64 __scs_val = read_sysreg_s(sysreg); \ 1130 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1131 if (__scs_new != __scs_val) \ 1132 write_sysreg_s(__scs_new, sysreg); \ 1133 } while (0) 1134 1135 #define read_sysreg_par() ({ \ 1136 u64 par; \ 1137 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1138 par = read_sysreg(par_el1); \ 1139 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1140 par; \ 1141 }) 1142 1143 #endif 1144 1145 #endif /* __ASM_SYSREG_H */ 1146