xref: /openbmc/linux/arch/arm64/include/asm/sysreg.h (revision 26b32974)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Macros for accessing system registers with older binutils.
4  *
5  * Copyright (C) 2014 ARM Ltd.
6  * Author: Catalin Marinas <catalin.marinas@arm.com>
7  */
8 
9 #ifndef __ASM_SYSREG_H
10 #define __ASM_SYSREG_H
11 
12 #include <linux/bits.h>
13 #include <linux/stringify.h>
14 #include <linux/kasan-tags.h>
15 
16 #include <asm/gpr-num.h>
17 
18 /*
19  * ARMv8 ARM reserves the following encoding for system registers:
20  * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
21  *  C5.2, version:ARM DDI 0487A.f)
22  *	[20-19] : Op0
23  *	[18-16] : Op1
24  *	[15-12] : CRn
25  *	[11-8]  : CRm
26  *	[7-5]   : Op2
27  */
28 #define Op0_shift	19
29 #define Op0_mask	0x3
30 #define Op1_shift	16
31 #define Op1_mask	0x7
32 #define CRn_shift	12
33 #define CRn_mask	0xf
34 #define CRm_shift	8
35 #define CRm_mask	0xf
36 #define Op2_shift	5
37 #define Op2_mask	0x7
38 
39 #define sys_reg(op0, op1, crn, crm, op2) \
40 	(((op0) << Op0_shift) | ((op1) << Op1_shift) | \
41 	 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
42 	 ((op2) << Op2_shift))
43 
44 #define sys_insn	sys_reg
45 
46 #define sys_reg_Op0(id)	(((id) >> Op0_shift) & Op0_mask)
47 #define sys_reg_Op1(id)	(((id) >> Op1_shift) & Op1_mask)
48 #define sys_reg_CRn(id)	(((id) >> CRn_shift) & CRn_mask)
49 #define sys_reg_CRm(id)	(((id) >> CRm_shift) & CRm_mask)
50 #define sys_reg_Op2(id)	(((id) >> Op2_shift) & Op2_mask)
51 
52 #ifndef CONFIG_BROKEN_GAS_INST
53 
54 #ifdef __ASSEMBLY__
55 // The space separator is omitted so that __emit_inst(x) can be parsed as
56 // either an assembler directive or an assembler macro argument.
57 #define __emit_inst(x)			.inst(x)
58 #else
59 #define __emit_inst(x)			".inst " __stringify((x)) "\n\t"
60 #endif
61 
62 #else  /* CONFIG_BROKEN_GAS_INST */
63 
64 #ifndef CONFIG_CPU_BIG_ENDIAN
65 #define __INSTR_BSWAP(x)		(x)
66 #else  /* CONFIG_CPU_BIG_ENDIAN */
67 #define __INSTR_BSWAP(x)		((((x) << 24) & 0xff000000)	| \
68 					 (((x) <<  8) & 0x00ff0000)	| \
69 					 (((x) >>  8) & 0x0000ff00)	| \
70 					 (((x) >> 24) & 0x000000ff))
71 #endif	/* CONFIG_CPU_BIG_ENDIAN */
72 
73 #ifdef __ASSEMBLY__
74 #define __emit_inst(x)			.long __INSTR_BSWAP(x)
75 #else  /* __ASSEMBLY__ */
76 #define __emit_inst(x)			".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
77 #endif	/* __ASSEMBLY__ */
78 
79 #endif	/* CONFIG_BROKEN_GAS_INST */
80 
81 /*
82  * Instructions for modifying PSTATE fields.
83  * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
84  * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
85  * for accessing PSTATE fields have the following encoding:
86  *	Op0 = 0, CRn = 4
87  *	Op1, Op2 encodes the PSTATE field modified and defines the constraints.
88  *	CRm = Imm4 for the instruction.
89  *	Rt = 0x1f
90  */
91 #define pstate_field(op1, op2)		((op1) << Op1_shift | (op2) << Op2_shift)
92 #define PSTATE_Imm_shift		CRm_shift
93 #define SET_PSTATE(x, r)		__emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
94 
95 #define PSTATE_PAN			pstate_field(0, 4)
96 #define PSTATE_UAO			pstate_field(0, 3)
97 #define PSTATE_SSBS			pstate_field(3, 1)
98 #define PSTATE_DIT			pstate_field(3, 2)
99 #define PSTATE_TCO			pstate_field(3, 4)
100 
101 #define SET_PSTATE_PAN(x)		SET_PSTATE((x), PAN)
102 #define SET_PSTATE_UAO(x)		SET_PSTATE((x), UAO)
103 #define SET_PSTATE_SSBS(x)		SET_PSTATE((x), SSBS)
104 #define SET_PSTATE_DIT(x)		SET_PSTATE((x), DIT)
105 #define SET_PSTATE_TCO(x)		SET_PSTATE((x), TCO)
106 
107 #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
108 #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
109 #define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
110 #define set_pstate_dit(x)		asm volatile(SET_PSTATE_DIT(x))
111 
112 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \
113 	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
114 
115 #define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
116 
117 #define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
118 #define SYS_DC_IGSW			sys_insn(1, 0, 7, 6, 4)
119 #define SYS_DC_IGDSW			sys_insn(1, 0, 7, 6, 6)
120 #define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
121 #define SYS_DC_CGSW			sys_insn(1, 0, 7, 10, 4)
122 #define SYS_DC_CGDSW			sys_insn(1, 0, 7, 10, 6)
123 #define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
124 #define SYS_DC_CIGSW			sys_insn(1, 0, 7, 14, 4)
125 #define SYS_DC_CIGDSW			sys_insn(1, 0, 7, 14, 6)
126 
127 /*
128  * Automatically generated definitions for system registers, the
129  * manual encodings below are in the process of being converted to
130  * come from here. The header relies on the definition of sys_reg()
131  * earlier in this file.
132  */
133 #include "asm/sysreg-defs.h"
134 
135 /*
136  * System registers, organised loosely by encoding but grouped together
137  * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
138  */
139 #define SYS_SVCR_SMSTOP_SM_EL0		sys_reg(0, 3, 4, 2, 3)
140 #define SYS_SVCR_SMSTART_SM_EL0		sys_reg(0, 3, 4, 3, 3)
141 #define SYS_SVCR_SMSTOP_SMZA_EL0	sys_reg(0, 3, 4, 6, 3)
142 
143 #define SYS_DBGBVRn_EL1(n)		sys_reg(2, 0, 0, n, 4)
144 #define SYS_DBGBCRn_EL1(n)		sys_reg(2, 0, 0, n, 5)
145 #define SYS_DBGWVRn_EL1(n)		sys_reg(2, 0, 0, n, 6)
146 #define SYS_DBGWCRn_EL1(n)		sys_reg(2, 0, 0, n, 7)
147 #define SYS_MDRAR_EL1			sys_reg(2, 0, 1, 0, 0)
148 
149 #define SYS_OSLSR_EL1			sys_reg(2, 0, 1, 1, 4)
150 #define OSLSR_EL1_OSLM_MASK		(BIT(3) | BIT(0))
151 #define OSLSR_EL1_OSLM_NI		0
152 #define OSLSR_EL1_OSLM_IMPLEMENTED	BIT(3)
153 #define OSLSR_EL1_OSLK			BIT(1)
154 
155 #define SYS_OSDLR_EL1			sys_reg(2, 0, 1, 3, 4)
156 #define SYS_DBGPRCR_EL1			sys_reg(2, 0, 1, 4, 4)
157 #define SYS_DBGCLAIMSET_EL1		sys_reg(2, 0, 7, 8, 6)
158 #define SYS_DBGCLAIMCLR_EL1		sys_reg(2, 0, 7, 9, 6)
159 #define SYS_DBGAUTHSTATUS_EL1		sys_reg(2, 0, 7, 14, 6)
160 #define SYS_MDCCSR_EL0			sys_reg(2, 3, 0, 1, 0)
161 #define SYS_DBGDTR_EL0			sys_reg(2, 3, 0, 4, 0)
162 #define SYS_DBGDTRRX_EL0		sys_reg(2, 3, 0, 5, 0)
163 #define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
164 #define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)
165 
166 #define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
167 #define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
168 #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
169 
170 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
171 #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
172 #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
173 
174 #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
175 
176 #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
177 
178 #define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
179 #define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
180 #define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
181 #define SYS_APIBKEYHI_EL1		sys_reg(3, 0, 2, 1, 3)
182 
183 #define SYS_APDAKEYLO_EL1		sys_reg(3, 0, 2, 2, 0)
184 #define SYS_APDAKEYHI_EL1		sys_reg(3, 0, 2, 2, 1)
185 #define SYS_APDBKEYLO_EL1		sys_reg(3, 0, 2, 2, 2)
186 #define SYS_APDBKEYHI_EL1		sys_reg(3, 0, 2, 2, 3)
187 
188 #define SYS_APGAKEYLO_EL1		sys_reg(3, 0, 2, 3, 0)
189 #define SYS_APGAKEYHI_EL1		sys_reg(3, 0, 2, 3, 1)
190 
191 #define SYS_SPSR_EL1			sys_reg(3, 0, 4, 0, 0)
192 #define SYS_ELR_EL1			sys_reg(3, 0, 4, 0, 1)
193 
194 #define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
195 
196 #define SYS_AFSR0_EL1			sys_reg(3, 0, 5, 1, 0)
197 #define SYS_AFSR1_EL1			sys_reg(3, 0, 5, 1, 1)
198 #define SYS_ESR_EL1			sys_reg(3, 0, 5, 2, 0)
199 
200 #define SYS_ERRIDR_EL1			sys_reg(3, 0, 5, 3, 0)
201 #define SYS_ERRSELR_EL1			sys_reg(3, 0, 5, 3, 1)
202 #define SYS_ERXFR_EL1			sys_reg(3, 0, 5, 4, 0)
203 #define SYS_ERXCTLR_EL1			sys_reg(3, 0, 5, 4, 1)
204 #define SYS_ERXSTATUS_EL1		sys_reg(3, 0, 5, 4, 2)
205 #define SYS_ERXADDR_EL1			sys_reg(3, 0, 5, 4, 3)
206 #define SYS_ERXMISC0_EL1		sys_reg(3, 0, 5, 5, 0)
207 #define SYS_ERXMISC1_EL1		sys_reg(3, 0, 5, 5, 1)
208 #define SYS_TFSR_EL1			sys_reg(3, 0, 5, 6, 0)
209 #define SYS_TFSRE0_EL1			sys_reg(3, 0, 5, 6, 1)
210 
211 #define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)
212 
213 #define SYS_PAR_EL1_F			BIT(0)
214 #define SYS_PAR_EL1_FST			GENMASK(6, 1)
215 
216 /*** Statistical Profiling Extension ***/
217 #define PMSEVFR_EL1_RES0_IMP	\
218 	(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
219 	 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
220 #define PMSEVFR_EL1_RES0_V1P1	\
221 	(PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
222 #define PMSEVFR_EL1_RES0_V1P2	\
223 	(PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))
224 
225 /* Buffer error reporting */
226 #define PMBSR_EL1_FAULT_FSC_SHIFT	PMBSR_EL1_MSS_SHIFT
227 #define PMBSR_EL1_FAULT_FSC_MASK	PMBSR_EL1_MSS_MASK
228 
229 #define PMBSR_EL1_BUF_BSC_SHIFT		PMBSR_EL1_MSS_SHIFT
230 #define PMBSR_EL1_BUF_BSC_MASK		PMBSR_EL1_MSS_MASK
231 
232 #define PMBSR_EL1_BUF_BSC_FULL		0x1UL
233 
234 /*** End of Statistical Profiling Extension ***/
235 
236 #define TRBSR_EL1_BSC_MASK		GENMASK(5, 0)
237 #define TRBSR_EL1_BSC_SHIFT		0
238 
239 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
240 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
241 
242 #define SYS_PMMIR_EL1			sys_reg(3, 0, 9, 14, 6)
243 
244 #define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
245 #define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
246 
247 #define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
248 #define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
249 
250 #define SYS_ICC_IAR0_EL1		sys_reg(3, 0, 12, 8, 0)
251 #define SYS_ICC_EOIR0_EL1		sys_reg(3, 0, 12, 8, 1)
252 #define SYS_ICC_HPPIR0_EL1		sys_reg(3, 0, 12, 8, 2)
253 #define SYS_ICC_BPR0_EL1		sys_reg(3, 0, 12, 8, 3)
254 #define SYS_ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)
255 #define SYS_ICC_AP0R0_EL1		SYS_ICC_AP0Rn_EL1(0)
256 #define SYS_ICC_AP0R1_EL1		SYS_ICC_AP0Rn_EL1(1)
257 #define SYS_ICC_AP0R2_EL1		SYS_ICC_AP0Rn_EL1(2)
258 #define SYS_ICC_AP0R3_EL1		SYS_ICC_AP0Rn_EL1(3)
259 #define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)
260 #define SYS_ICC_AP1R0_EL1		SYS_ICC_AP1Rn_EL1(0)
261 #define SYS_ICC_AP1R1_EL1		SYS_ICC_AP1Rn_EL1(1)
262 #define SYS_ICC_AP1R2_EL1		SYS_ICC_AP1Rn_EL1(2)
263 #define SYS_ICC_AP1R3_EL1		SYS_ICC_AP1Rn_EL1(3)
264 #define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
265 #define SYS_ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)
266 #define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
267 #define SYS_ICC_ASGI1R_EL1		sys_reg(3, 0, 12, 11, 6)
268 #define SYS_ICC_SGI0R_EL1		sys_reg(3, 0, 12, 11, 7)
269 #define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
270 #define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
271 #define SYS_ICC_HPPIR1_EL1		sys_reg(3, 0, 12, 12, 2)
272 #define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
273 #define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
274 #define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
275 #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
276 #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
277 
278 #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
279 
280 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
281 
282 #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
283 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
284 
285 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
286 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
287 #define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
288 #define SYS_PMOVSCLR_EL0		sys_reg(3, 3, 9, 12, 3)
289 #define SYS_PMSWINC_EL0			sys_reg(3, 3, 9, 12, 4)
290 #define SYS_PMSELR_EL0			sys_reg(3, 3, 9, 12, 5)
291 #define SYS_PMCEID0_EL0			sys_reg(3, 3, 9, 12, 6)
292 #define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
293 #define SYS_PMCCNTR_EL0			sys_reg(3, 3, 9, 13, 0)
294 #define SYS_PMXEVTYPER_EL0		sys_reg(3, 3, 9, 13, 1)
295 #define SYS_PMXEVCNTR_EL0		sys_reg(3, 3, 9, 13, 2)
296 #define SYS_PMUSERENR_EL0		sys_reg(3, 3, 9, 14, 0)
297 #define SYS_PMOVSSET_EL0		sys_reg(3, 3, 9, 14, 3)
298 
299 #define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
300 #define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
301 #define SYS_TPIDR2_EL0			sys_reg(3, 3, 13, 0, 5)
302 
303 #define SYS_SCXTNUM_EL0			sys_reg(3, 3, 13, 0, 7)
304 
305 /* Definitions for system register interface to AMU for ARMv8.4 onwards */
306 #define SYS_AM_EL0(crm, op2)		sys_reg(3, 3, 13, (crm), (op2))
307 #define SYS_AMCR_EL0			SYS_AM_EL0(2, 0)
308 #define SYS_AMCFGR_EL0			SYS_AM_EL0(2, 1)
309 #define SYS_AMCGCR_EL0			SYS_AM_EL0(2, 2)
310 #define SYS_AMUSERENR_EL0		SYS_AM_EL0(2, 3)
311 #define SYS_AMCNTENCLR0_EL0		SYS_AM_EL0(2, 4)
312 #define SYS_AMCNTENSET0_EL0		SYS_AM_EL0(2, 5)
313 #define SYS_AMCNTENCLR1_EL0		SYS_AM_EL0(3, 0)
314 #define SYS_AMCNTENSET1_EL0		SYS_AM_EL0(3, 1)
315 
316 /*
317  * Group 0 of activity monitors (architected):
318  *                op0  op1  CRn   CRm       op2
319  * Counter:       11   011  1101  010:n<3>  n<2:0>
320  * Type:          11   011  1101  011:n<3>  n<2:0>
321  * n: 0-15
322  *
323  * Group 1 of activity monitors (auxiliary):
324  *                op0  op1  CRn   CRm       op2
325  * Counter:       11   011  1101  110:n<3>  n<2:0>
326  * Type:          11   011  1101  111:n<3>  n<2:0>
327  * n: 0-15
328  */
329 
330 #define SYS_AMEVCNTR0_EL0(n)		SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
331 #define SYS_AMEVTYPER0_EL0(n)		SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
332 #define SYS_AMEVCNTR1_EL0(n)		SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
333 #define SYS_AMEVTYPER1_EL0(n)		SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
334 
335 /* AMU v1: Fixed (architecturally defined) activity monitors */
336 #define SYS_AMEVCNTR0_CORE_EL0		SYS_AMEVCNTR0_EL0(0)
337 #define SYS_AMEVCNTR0_CONST_EL0		SYS_AMEVCNTR0_EL0(1)
338 #define SYS_AMEVCNTR0_INST_RET_EL0	SYS_AMEVCNTR0_EL0(2)
339 #define SYS_AMEVCNTR0_MEM_STALL		SYS_AMEVCNTR0_EL0(3)
340 
341 #define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
342 
343 #define SYS_CNTPCT_EL0			sys_reg(3, 3, 14, 0, 1)
344 #define SYS_CNTPCTSS_EL0		sys_reg(3, 3, 14, 0, 5)
345 #define SYS_CNTVCTSS_EL0		sys_reg(3, 3, 14, 0, 6)
346 
347 #define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
348 #define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
349 #define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)
350 
351 #define SYS_CNTV_CTL_EL0		sys_reg(3, 3, 14, 3, 1)
352 #define SYS_CNTV_CVAL_EL0		sys_reg(3, 3, 14, 3, 2)
353 
354 #define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)
355 #define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)
356 #define SYS_AARCH32_CNTPCT		sys_reg(0, 0, 0, 14, 0)
357 #define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)
358 #define SYS_AARCH32_CNTPCTSS		sys_reg(0, 8, 0, 14, 0)
359 
360 #define __PMEV_op2(n)			((n) & 0x7)
361 #define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
362 #define SYS_PMEVCNTRn_EL0(n)		sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
363 #define __TYPER_CRm(n)			(0xc | (((n) >> 3) & 0x3))
364 #define SYS_PMEVTYPERn_EL0(n)		sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
365 
366 #define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
367 
368 #define SYS_VPIDR_EL2			sys_reg(3, 4, 0, 0, 0)
369 #define SYS_VMPIDR_EL2			sys_reg(3, 4, 0, 0, 5)
370 
371 #define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)
372 #define SYS_ACTLR_EL2			sys_reg(3, 4, 1, 0, 1)
373 #define SYS_HCR_EL2			sys_reg(3, 4, 1, 1, 0)
374 #define SYS_MDCR_EL2			sys_reg(3, 4, 1, 1, 1)
375 #define SYS_CPTR_EL2			sys_reg(3, 4, 1, 1, 2)
376 #define SYS_HSTR_EL2			sys_reg(3, 4, 1, 1, 3)
377 #define SYS_HACR_EL2			sys_reg(3, 4, 1, 1, 7)
378 
379 #define SYS_TTBR0_EL2			sys_reg(3, 4, 2, 0, 0)
380 #define SYS_TTBR1_EL2			sys_reg(3, 4, 2, 0, 1)
381 #define SYS_TCR_EL2			sys_reg(3, 4, 2, 0, 2)
382 #define SYS_VTTBR_EL2			sys_reg(3, 4, 2, 1, 0)
383 #define SYS_VTCR_EL2			sys_reg(3, 4, 2, 1, 2)
384 
385 #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
386 #define SYS_HDFGRTR_EL2			sys_reg(3, 4, 3, 1, 4)
387 #define SYS_HDFGWTR_EL2			sys_reg(3, 4, 3, 1, 5)
388 #define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)
389 #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
390 #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
391 #define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)
392 #define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
393 #define SYS_AFSR0_EL2			sys_reg(3, 4, 5, 1, 0)
394 #define SYS_AFSR1_EL2			sys_reg(3, 4, 5, 1, 1)
395 #define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
396 #define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)
397 #define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
398 #define SYS_TFSR_EL2			sys_reg(3, 4, 5, 6, 0)
399 
400 #define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
401 #define SYS_HPFAR_EL2			sys_reg(3, 4, 6, 0, 4)
402 
403 #define SYS_MAIR_EL2			sys_reg(3, 4, 10, 2, 0)
404 #define SYS_AMAIR_EL2			sys_reg(3, 4, 10, 3, 0)
405 
406 #define SYS_VBAR_EL2			sys_reg(3, 4, 12, 0, 0)
407 #define SYS_RVBAR_EL2			sys_reg(3, 4, 12, 0, 1)
408 #define SYS_RMR_EL2			sys_reg(3, 4, 12, 0, 2)
409 #define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1, 1)
410 #define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
411 #define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
412 #define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
413 #define SYS_ICH_AP0R2_EL2		__SYS__AP0Rx_EL2(2)
414 #define SYS_ICH_AP0R3_EL2		__SYS__AP0Rx_EL2(3)
415 
416 #define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
417 #define SYS_ICH_AP1R0_EL2		__SYS__AP1Rx_EL2(0)
418 #define SYS_ICH_AP1R1_EL2		__SYS__AP1Rx_EL2(1)
419 #define SYS_ICH_AP1R2_EL2		__SYS__AP1Rx_EL2(2)
420 #define SYS_ICH_AP1R3_EL2		__SYS__AP1Rx_EL2(3)
421 
422 #define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
423 #define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
424 #define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
425 #define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
426 #define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)
427 #define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
428 #define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)
429 #define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
430 
431 #define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
432 #define SYS_ICH_LR0_EL2			__SYS__LR0_EL2(0)
433 #define SYS_ICH_LR1_EL2			__SYS__LR0_EL2(1)
434 #define SYS_ICH_LR2_EL2			__SYS__LR0_EL2(2)
435 #define SYS_ICH_LR3_EL2			__SYS__LR0_EL2(3)
436 #define SYS_ICH_LR4_EL2			__SYS__LR0_EL2(4)
437 #define SYS_ICH_LR5_EL2			__SYS__LR0_EL2(5)
438 #define SYS_ICH_LR6_EL2			__SYS__LR0_EL2(6)
439 #define SYS_ICH_LR7_EL2			__SYS__LR0_EL2(7)
440 
441 #define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
442 #define SYS_ICH_LR8_EL2			__SYS__LR8_EL2(0)
443 #define SYS_ICH_LR9_EL2			__SYS__LR8_EL2(1)
444 #define SYS_ICH_LR10_EL2		__SYS__LR8_EL2(2)
445 #define SYS_ICH_LR11_EL2		__SYS__LR8_EL2(3)
446 #define SYS_ICH_LR12_EL2		__SYS__LR8_EL2(4)
447 #define SYS_ICH_LR13_EL2		__SYS__LR8_EL2(5)
448 #define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
449 #define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
450 
451 #define SYS_CONTEXTIDR_EL2		sys_reg(3, 4, 13, 0, 1)
452 #define SYS_TPIDR_EL2			sys_reg(3, 4, 13, 0, 2)
453 
454 #define SYS_CNTVOFF_EL2			sys_reg(3, 4, 14, 0, 3)
455 #define SYS_CNTHCTL_EL2			sys_reg(3, 4, 14, 1, 0)
456 
457 /* VHE encodings for architectural EL0/1 system registers */
458 #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
459 #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
460 #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
461 #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
462 #define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)
463 #define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)
464 #define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)
465 #define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
466 #define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
467 #define SYS_TFSR_EL12			sys_reg(3, 5, 5, 6, 0)
468 #define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
469 #define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
470 #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
471 #define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
472 #define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
473 #define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
474 #define SYS_CNTP_CVAL_EL02		sys_reg(3, 5, 14, 2, 2)
475 #define SYS_CNTV_TVAL_EL02		sys_reg(3, 5, 14, 3, 0)
476 #define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
477 #define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
478 
479 #define SYS_SP_EL2			sys_reg(3, 6,  4, 1, 0)
480 
481 /* Common SCTLR_ELx flags. */
482 #define SCTLR_ELx_ENTP2	(BIT(60))
483 #define SCTLR_ELx_DSSBS	(BIT(44))
484 #define SCTLR_ELx_ATA	(BIT(43))
485 
486 #define SCTLR_ELx_EE_SHIFT	25
487 #define SCTLR_ELx_ENIA_SHIFT	31
488 
489 #define SCTLR_ELx_ITFSB	 (BIT(37))
490 #define SCTLR_ELx_ENIA	 (BIT(SCTLR_ELx_ENIA_SHIFT))
491 #define SCTLR_ELx_ENIB	 (BIT(30))
492 #define SCTLR_ELx_LSMAOE (BIT(29))
493 #define SCTLR_ELx_nTLSMD (BIT(28))
494 #define SCTLR_ELx_ENDA	 (BIT(27))
495 #define SCTLR_ELx_EE     (BIT(SCTLR_ELx_EE_SHIFT))
496 #define SCTLR_ELx_EIS	 (BIT(22))
497 #define SCTLR_ELx_IESB	 (BIT(21))
498 #define SCTLR_ELx_TSCXT	 (BIT(20))
499 #define SCTLR_ELx_WXN	 (BIT(19))
500 #define SCTLR_ELx_ENDB	 (BIT(13))
501 #define SCTLR_ELx_I	 (BIT(12))
502 #define SCTLR_ELx_EOS	 (BIT(11))
503 #define SCTLR_ELx_SA	 (BIT(3))
504 #define SCTLR_ELx_C	 (BIT(2))
505 #define SCTLR_ELx_A	 (BIT(1))
506 #define SCTLR_ELx_M	 (BIT(0))
507 
508 /* SCTLR_EL2 specific flags. */
509 #define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
510 			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
511 			 (BIT(29)))
512 
513 #ifdef CONFIG_CPU_BIG_ENDIAN
514 #define ENDIAN_SET_EL2		SCTLR_ELx_EE
515 #else
516 #define ENDIAN_SET_EL2		0
517 #endif
518 
519 #define INIT_SCTLR_EL2_MMU_ON						\
520 	(SCTLR_ELx_M  | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I |	\
521 	 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 |		\
522 	 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1)
523 
524 #define INIT_SCTLR_EL2_MMU_OFF \
525 	(SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
526 
527 /* SCTLR_EL1 specific flags. */
528 #ifdef CONFIG_CPU_BIG_ENDIAN
529 #define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
530 #else
531 #define ENDIAN_SET_EL1		0
532 #endif
533 
534 #define INIT_SCTLR_EL1_MMU_OFF \
535 	(ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \
536 	 SCTLR_EL1_EIS  | SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
537 
538 #define INIT_SCTLR_EL1_MMU_ON \
539 	(SCTLR_ELx_M      | SCTLR_ELx_C      | SCTLR_ELx_SA    | \
540 	 SCTLR_EL1_SA0    | SCTLR_EL1_SED    | SCTLR_ELx_I     | \
541 	 SCTLR_EL1_DZE    | SCTLR_EL1_UCT    | SCTLR_EL1_nTWE  | \
542 	 SCTLR_ELx_IESB   | SCTLR_EL1_SPAN   | SCTLR_ELx_ITFSB | \
543 	 ENDIAN_SET_EL1   | SCTLR_EL1_UCI    | SCTLR_EL1_EPAN  | \
544 	 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS   | \
545 	 SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
546 
547 /* MAIR_ELx memory attributes (used by Linux) */
548 #define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
549 #define MAIR_ATTR_DEVICE_nGnRE		UL(0x04)
550 #define MAIR_ATTR_NORMAL_NC		UL(0x44)
551 #define MAIR_ATTR_NORMAL_TAGGED		UL(0xf0)
552 #define MAIR_ATTR_NORMAL		UL(0xff)
553 #define MAIR_ATTR_MASK			UL(0xff)
554 
555 /* Position the attr at the correct index */
556 #define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
557 
558 /* id_aa64pfr0 */
559 #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY		0x1
560 #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT		0x2
561 
562 /* id_aa64mmfr0 */
563 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
564 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7
565 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0
566 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7
567 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1
568 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf
569 
570 #define ARM64_MIN_PARANGE_BITS		32
571 
572 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT	0x0
573 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE		0x1
574 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN		0x2
575 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX		0x7
576 
577 #ifdef CONFIG_ARM64_PA_BITS_52
578 #define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_52
579 #else
580 #define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_48
581 #endif
582 
583 #if defined(CONFIG_ARM64_4K_PAGES)
584 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_SHIFT
585 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
586 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
587 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
588 #elif defined(CONFIG_ARM64_16K_PAGES)
589 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_SHIFT
590 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
591 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
592 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
593 #elif defined(CONFIG_ARM64_64K_PAGES)
594 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_SHIFT
595 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN
596 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX
597 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
598 #endif
599 
600 #define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
601 #define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
602 
603 #define CPACR_EL1_SMEN_EL1EN	(BIT(24)) /* enable EL1 access */
604 #define CPACR_EL1_SMEN_EL0EN	(BIT(25)) /* enable EL0 access, if EL1EN set */
605 
606 #define CPACR_EL1_ZEN_EL1EN	(BIT(16)) /* enable EL1 access */
607 #define CPACR_EL1_ZEN_EL0EN	(BIT(17)) /* enable EL0 access, if EL1EN set */
608 
609 /* GCR_EL1 Definitions */
610 #define SYS_GCR_EL1_RRND	(BIT(16))
611 #define SYS_GCR_EL1_EXCL_MASK	0xffffUL
612 
613 #ifdef CONFIG_KASAN_HW_TAGS
614 /*
615  * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
616  * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
617  */
618 #define __MTE_TAG_MIN		(KASAN_TAG_MIN & 0xf)
619 #define __MTE_TAG_MAX		(KASAN_TAG_MAX & 0xf)
620 #define __MTE_TAG_INCL		GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
621 #define KERNEL_GCR_EL1_EXCL	(SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
622 #else
623 #define KERNEL_GCR_EL1_EXCL	SYS_GCR_EL1_EXCL_MASK
624 #endif
625 
626 #define KERNEL_GCR_EL1		(SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
627 
628 /* RGSR_EL1 Definitions */
629 #define SYS_RGSR_EL1_TAG_MASK	0xfUL
630 #define SYS_RGSR_EL1_SEED_SHIFT	8
631 #define SYS_RGSR_EL1_SEED_MASK	0xffffUL
632 
633 /* TFSR{,E0}_EL1 bit definitions */
634 #define SYS_TFSR_EL1_TF0_SHIFT	0
635 #define SYS_TFSR_EL1_TF1_SHIFT	1
636 #define SYS_TFSR_EL1_TF0	(UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
637 #define SYS_TFSR_EL1_TF1	(UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
638 
639 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
640 #define SYS_MPIDR_SAFE_VAL	(BIT(31))
641 
642 #define TRFCR_ELx_TS_SHIFT		5
643 #define TRFCR_ELx_TS_MASK		((0x3UL) << TRFCR_ELx_TS_SHIFT)
644 #define TRFCR_ELx_TS_VIRTUAL		((0x1UL) << TRFCR_ELx_TS_SHIFT)
645 #define TRFCR_ELx_TS_GUEST_PHYSICAL	((0x2UL) << TRFCR_ELx_TS_SHIFT)
646 #define TRFCR_ELx_TS_PHYSICAL		((0x3UL) << TRFCR_ELx_TS_SHIFT)
647 #define TRFCR_EL2_CX			BIT(3)
648 #define TRFCR_ELx_ExTRE			BIT(1)
649 #define TRFCR_ELx_E0TRE			BIT(0)
650 
651 /* GIC Hypervisor interface registers */
652 /* ICH_MISR_EL2 bit definitions */
653 #define ICH_MISR_EOI		(1 << 0)
654 #define ICH_MISR_U		(1 << 1)
655 
656 /* ICH_LR*_EL2 bit definitions */
657 #define ICH_LR_VIRTUAL_ID_MASK	((1ULL << 32) - 1)
658 
659 #define ICH_LR_EOI		(1ULL << 41)
660 #define ICH_LR_GROUP		(1ULL << 60)
661 #define ICH_LR_HW		(1ULL << 61)
662 #define ICH_LR_STATE		(3ULL << 62)
663 #define ICH_LR_PENDING_BIT	(1ULL << 62)
664 #define ICH_LR_ACTIVE_BIT	(1ULL << 63)
665 #define ICH_LR_PHYS_ID_SHIFT	32
666 #define ICH_LR_PHYS_ID_MASK	(0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
667 #define ICH_LR_PRIORITY_SHIFT	48
668 #define ICH_LR_PRIORITY_MASK	(0xffULL << ICH_LR_PRIORITY_SHIFT)
669 
670 /* ICH_HCR_EL2 bit definitions */
671 #define ICH_HCR_EN		(1 << 0)
672 #define ICH_HCR_UIE		(1 << 1)
673 #define ICH_HCR_NPIE		(1 << 3)
674 #define ICH_HCR_TC		(1 << 10)
675 #define ICH_HCR_TALL0		(1 << 11)
676 #define ICH_HCR_TALL1		(1 << 12)
677 #define ICH_HCR_TDIR		(1 << 14)
678 #define ICH_HCR_EOIcount_SHIFT	27
679 #define ICH_HCR_EOIcount_MASK	(0x1f << ICH_HCR_EOIcount_SHIFT)
680 
681 /* ICH_VMCR_EL2 bit definitions */
682 #define ICH_VMCR_ACK_CTL_SHIFT	2
683 #define ICH_VMCR_ACK_CTL_MASK	(1 << ICH_VMCR_ACK_CTL_SHIFT)
684 #define ICH_VMCR_FIQ_EN_SHIFT	3
685 #define ICH_VMCR_FIQ_EN_MASK	(1 << ICH_VMCR_FIQ_EN_SHIFT)
686 #define ICH_VMCR_CBPR_SHIFT	4
687 #define ICH_VMCR_CBPR_MASK	(1 << ICH_VMCR_CBPR_SHIFT)
688 #define ICH_VMCR_EOIM_SHIFT	9
689 #define ICH_VMCR_EOIM_MASK	(1 << ICH_VMCR_EOIM_SHIFT)
690 #define ICH_VMCR_BPR1_SHIFT	18
691 #define ICH_VMCR_BPR1_MASK	(7 << ICH_VMCR_BPR1_SHIFT)
692 #define ICH_VMCR_BPR0_SHIFT	21
693 #define ICH_VMCR_BPR0_MASK	(7 << ICH_VMCR_BPR0_SHIFT)
694 #define ICH_VMCR_PMR_SHIFT	24
695 #define ICH_VMCR_PMR_MASK	(0xffUL << ICH_VMCR_PMR_SHIFT)
696 #define ICH_VMCR_ENG0_SHIFT	0
697 #define ICH_VMCR_ENG0_MASK	(1 << ICH_VMCR_ENG0_SHIFT)
698 #define ICH_VMCR_ENG1_SHIFT	1
699 #define ICH_VMCR_ENG1_MASK	(1 << ICH_VMCR_ENG1_SHIFT)
700 
701 /* ICH_VTR_EL2 bit definitions */
702 #define ICH_VTR_PRI_BITS_SHIFT	29
703 #define ICH_VTR_PRI_BITS_MASK	(7 << ICH_VTR_PRI_BITS_SHIFT)
704 #define ICH_VTR_ID_BITS_SHIFT	23
705 #define ICH_VTR_ID_BITS_MASK	(7 << ICH_VTR_ID_BITS_SHIFT)
706 #define ICH_VTR_SEIS_SHIFT	22
707 #define ICH_VTR_SEIS_MASK	(1 << ICH_VTR_SEIS_SHIFT)
708 #define ICH_VTR_A3V_SHIFT	21
709 #define ICH_VTR_A3V_MASK	(1 << ICH_VTR_A3V_SHIFT)
710 #define ICH_VTR_TDS_SHIFT	19
711 #define ICH_VTR_TDS_MASK	(1 << ICH_VTR_TDS_SHIFT)
712 
713 /*
714  * Permission Indirection Extension (PIE) permission encodings.
715  * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
716  */
717 #define PIE_NONE_O	0x0
718 #define PIE_R_O		0x1
719 #define PIE_X_O		0x2
720 #define PIE_RX_O	0x3
721 #define PIE_RW_O	0x5
722 #define PIE_RWnX_O	0x6
723 #define PIE_RWX_O	0x7
724 #define PIE_R		0x8
725 #define PIE_GCS		0x9
726 #define PIE_RX		0xa
727 #define PIE_RW		0xc
728 #define PIE_RWX		0xe
729 
730 #define PIRx_ELx_PERM(idx, perm)	((perm) << ((idx) * 4))
731 
732 #define ARM64_FEATURE_FIELD_BITS	4
733 
734 /* Defined for compatibility only, do not add new users. */
735 #define ARM64_FEATURE_MASK(x)	(x##_MASK)
736 
737 #ifdef __ASSEMBLY__
738 
739 	.macro	mrs_s, rt, sreg
740 	 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
741 	.endm
742 
743 	.macro	msr_s, sreg, rt
744 	__emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
745 	.endm
746 
747 #else
748 
749 #include <linux/bitfield.h>
750 #include <linux/build_bug.h>
751 #include <linux/types.h>
752 #include <asm/alternative.h>
753 
754 #define DEFINE_MRS_S						\
755 	__DEFINE_ASM_GPR_NUMS					\
756 "	.macro	mrs_s, rt, sreg\n"				\
757 	__emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt))	\
758 "	.endm\n"
759 
760 #define DEFINE_MSR_S						\
761 	__DEFINE_ASM_GPR_NUMS					\
762 "	.macro	msr_s, sreg, rt\n"				\
763 	__emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt))	\
764 "	.endm\n"
765 
766 #define UNDEFINE_MRS_S						\
767 "	.purgem	mrs_s\n"
768 
769 #define UNDEFINE_MSR_S						\
770 "	.purgem	msr_s\n"
771 
772 #define __mrs_s(v, r)						\
773 	DEFINE_MRS_S						\
774 "	mrs_s " v ", " __stringify(r) "\n"			\
775 	UNDEFINE_MRS_S
776 
777 #define __msr_s(r, v)						\
778 	DEFINE_MSR_S						\
779 "	msr_s " __stringify(r) ", " v "\n"			\
780 	UNDEFINE_MSR_S
781 
782 /*
783  * Unlike read_cpuid, calls to read_sysreg are never expected to be
784  * optimized away or replaced with synthetic values.
785  */
786 #define read_sysreg(r) ({					\
787 	u64 __val;						\
788 	asm volatile("mrs %0, " __stringify(r) : "=r" (__val));	\
789 	__val;							\
790 })
791 
792 /*
793  * The "Z" constraint normally means a zero immediate, but when combined with
794  * the "%x0" template means XZR.
795  */
796 #define write_sysreg(v, r) do {					\
797 	u64 __val = (u64)(v);					\
798 	asm volatile("msr " __stringify(r) ", %x0"		\
799 		     : : "rZ" (__val));				\
800 } while (0)
801 
802 /*
803  * For registers without architectural names, or simply unsupported by
804  * GAS.
805  */
806 #define read_sysreg_s(r) ({						\
807 	u64 __val;							\
808 	asm volatile(__mrs_s("%0", r) : "=r" (__val));			\
809 	__val;								\
810 })
811 
812 #define write_sysreg_s(v, r) do {					\
813 	u64 __val = (u64)(v);						\
814 	asm volatile(__msr_s(r, "%x0") : : "rZ" (__val));		\
815 } while (0)
816 
817 /*
818  * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
819  * set mask are set. Other bits are left as-is.
820  */
821 #define sysreg_clear_set(sysreg, clear, set) do {			\
822 	u64 __scs_val = read_sysreg(sysreg);				\
823 	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
824 	if (__scs_new != __scs_val)					\
825 		write_sysreg(__scs_new, sysreg);			\
826 } while (0)
827 
828 #define sysreg_clear_set_s(sysreg, clear, set) do {			\
829 	u64 __scs_val = read_sysreg_s(sysreg);				\
830 	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
831 	if (__scs_new != __scs_val)					\
832 		write_sysreg_s(__scs_new, sysreg);			\
833 } while (0)
834 
835 #define read_sysreg_par() ({						\
836 	u64 par;							\
837 	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
838 	par = read_sysreg(par_el1);					\
839 	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
840 	par;								\
841 })
842 
843 #define SYS_FIELD_GET(reg, field, val)		\
844 		 FIELD_GET(reg##_##field##_MASK, val)
845 
846 #define SYS_FIELD_PREP(reg, field, val)		\
847 		 FIELD_PREP(reg##_##field##_MASK, val)
848 
849 #define SYS_FIELD_PREP_ENUM(reg, field, val)		\
850 		 FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val)
851 
852 #endif
853 
854 #endif	/* __ASM_SYSREG_H */
855