1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #ifndef __ASM_SYSREG_H 10 #define __ASM_SYSREG_H 11 12 #include <linux/bits.h> 13 #include <linux/stringify.h> 14 #include <linux/kasan-tags.h> 15 16 #include <asm/gpr-num.h> 17 18 /* 19 * ARMv8 ARM reserves the following encoding for system registers: 20 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 21 * C5.2, version:ARM DDI 0487A.f) 22 * [20-19] : Op0 23 * [18-16] : Op1 24 * [15-12] : CRn 25 * [11-8] : CRm 26 * [7-5] : Op2 27 */ 28 #define Op0_shift 19 29 #define Op0_mask 0x3 30 #define Op1_shift 16 31 #define Op1_mask 0x7 32 #define CRn_shift 12 33 #define CRn_mask 0xf 34 #define CRm_shift 8 35 #define CRm_mask 0xf 36 #define Op2_shift 5 37 #define Op2_mask 0x7 38 39 #define sys_reg(op0, op1, crn, crm, op2) \ 40 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 41 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 42 ((op2) << Op2_shift)) 43 44 #define sys_insn sys_reg 45 46 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 47 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 48 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 49 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 50 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 51 52 #ifndef CONFIG_BROKEN_GAS_INST 53 54 #ifdef __ASSEMBLY__ 55 // The space separator is omitted so that __emit_inst(x) can be parsed as 56 // either an assembler directive or an assembler macro argument. 57 #define __emit_inst(x) .inst(x) 58 #else 59 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 60 #endif 61 62 #else /* CONFIG_BROKEN_GAS_INST */ 63 64 #ifndef CONFIG_CPU_BIG_ENDIAN 65 #define __INSTR_BSWAP(x) (x) 66 #else /* CONFIG_CPU_BIG_ENDIAN */ 67 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 68 (((x) << 8) & 0x00ff0000) | \ 69 (((x) >> 8) & 0x0000ff00) | \ 70 (((x) >> 24) & 0x000000ff)) 71 #endif /* CONFIG_CPU_BIG_ENDIAN */ 72 73 #ifdef __ASSEMBLY__ 74 #define __emit_inst(x) .long __INSTR_BSWAP(x) 75 #else /* __ASSEMBLY__ */ 76 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 77 #endif /* __ASSEMBLY__ */ 78 79 #endif /* CONFIG_BROKEN_GAS_INST */ 80 81 /* 82 * Instructions for modifying PSTATE fields. 83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 84 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 85 * for accessing PSTATE fields have the following encoding: 86 * Op0 = 0, CRn = 4 87 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 88 * CRm = Imm4 for the instruction. 89 * Rt = 0x1f 90 */ 91 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 92 #define PSTATE_Imm_shift CRm_shift 93 94 #define PSTATE_PAN pstate_field(0, 4) 95 #define PSTATE_UAO pstate_field(0, 3) 96 #define PSTATE_SSBS pstate_field(3, 1) 97 #define PSTATE_TCO pstate_field(3, 4) 98 99 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) 100 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) 101 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) 102 #define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift)) 103 104 #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) 105 #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) 106 #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x)) 107 108 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ 109 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) 110 111 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) 112 113 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 114 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 115 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 116 117 /* 118 * Automatically generated definitions for system registers, the 119 * manual encodings below are in the process of being converted to 120 * come from here. The header relies on the definition of sys_reg() 121 * earlier in this file. 122 */ 123 #include "asm/sysreg-defs.h" 124 125 /* 126 * System registers, organised loosely by encoding but grouped together 127 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. 128 */ 129 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3) 130 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3) 131 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3) 132 133 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 134 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 135 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 136 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 137 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 138 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 139 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 140 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 141 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 142 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 143 144 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 145 #define SYS_OSLAR_OSLK BIT(0) 146 147 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 148 #define SYS_OSLSR_OSLM_MASK (BIT(3) | BIT(0)) 149 #define SYS_OSLSR_OSLM_NI 0 150 #define SYS_OSLSR_OSLM_IMPLEMENTED BIT(3) 151 #define SYS_OSLSR_OSLK BIT(1) 152 153 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 154 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 155 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 156 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 157 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 158 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 159 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 160 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 161 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 162 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 163 164 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 165 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 166 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 167 168 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 169 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 170 #define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) 171 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 172 #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5) 173 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 174 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 175 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 176 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 177 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 178 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 179 #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) 180 181 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 182 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 183 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 184 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 185 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 186 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 187 #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) 188 189 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 190 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 191 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 192 193 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 194 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 195 196 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 197 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 198 199 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 200 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 201 202 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 203 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 204 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 205 206 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 207 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) 208 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) 209 210 #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) 211 212 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 213 214 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 215 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 216 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 217 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 218 219 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 220 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 221 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 222 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 223 224 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 225 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 226 227 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) 228 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) 229 230 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 231 232 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 233 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 234 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 235 236 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 237 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 238 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 239 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 240 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 241 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 242 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 243 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 244 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0) 245 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1) 246 247 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 248 249 #define SYS_PAR_EL1_F BIT(0) 250 #define SYS_PAR_EL1_FST GENMASK(6, 1) 251 252 /*** Statistical Profiling Extension ***/ 253 /* ID registers */ 254 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 255 #define SYS_PMSIDR_EL1_FE_SHIFT 0 256 #define SYS_PMSIDR_EL1_FT_SHIFT 1 257 #define SYS_PMSIDR_EL1_FL_SHIFT 2 258 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 259 #define SYS_PMSIDR_EL1_LDS_SHIFT 4 260 #define SYS_PMSIDR_EL1_ERND_SHIFT 5 261 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 262 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 263 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 264 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 265 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 266 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 267 268 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 269 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 270 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 271 #define SYS_PMBIDR_EL1_P_SHIFT 4 272 #define SYS_PMBIDR_EL1_F_SHIFT 5 273 274 /* Sampling controls */ 275 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 276 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0 277 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1 278 #define SYS_PMSCR_EL1_CX_SHIFT 3 279 #define SYS_PMSCR_EL1_PA_SHIFT 4 280 #define SYS_PMSCR_EL1_TS_SHIFT 5 281 #define SYS_PMSCR_EL1_PCT_SHIFT 6 282 283 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 284 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 285 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1 286 #define SYS_PMSCR_EL2_CX_SHIFT 3 287 #define SYS_PMSCR_EL2_PA_SHIFT 4 288 #define SYS_PMSCR_EL2_TS_SHIFT 5 289 #define SYS_PMSCR_EL2_PCT_SHIFT 6 290 291 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 292 293 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 294 #define SYS_PMSIRR_EL1_RND_SHIFT 0 295 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 296 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 297 298 /* Filtering controls */ 299 #define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1) 300 301 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 302 #define SYS_PMSFCR_EL1_FE_SHIFT 0 303 #define SYS_PMSFCR_EL1_FT_SHIFT 1 304 #define SYS_PMSFCR_EL1_FL_SHIFT 2 305 #define SYS_PMSFCR_EL1_B_SHIFT 16 306 #define SYS_PMSFCR_EL1_LD_SHIFT 17 307 #define SYS_PMSFCR_EL1_ST_SHIFT 18 308 309 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 310 #define SYS_PMSEVFR_EL1_RES0_8_2 \ 311 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ 312 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) 313 #define SYS_PMSEVFR_EL1_RES0_8_3 \ 314 (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) 315 316 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 317 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 318 319 /* Buffer controls */ 320 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 321 #define SYS_PMBLIMITR_EL1_E_SHIFT 0 322 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1 323 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 324 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 325 326 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 327 328 /* Buffer error reporting */ 329 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 330 #define SYS_PMBSR_EL1_COLL_SHIFT 16 331 #define SYS_PMBSR_EL1_S_SHIFT 17 332 #define SYS_PMBSR_EL1_EA_SHIFT 18 333 #define SYS_PMBSR_EL1_DL_SHIFT 19 334 #define SYS_PMBSR_EL1_EC_SHIFT 26 335 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL 336 337 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 338 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 339 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 340 341 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 342 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 343 344 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 345 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 346 347 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 348 349 /*** End of Statistical Profiling Extension ***/ 350 351 /* 352 * TRBE Registers 353 */ 354 #define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0) 355 #define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1) 356 #define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2) 357 #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3) 358 #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4) 359 #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) 360 #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7) 361 362 #define TRBLIMITR_LIMIT_MASK GENMASK_ULL(51, 0) 363 #define TRBLIMITR_LIMIT_SHIFT 12 364 #define TRBLIMITR_NVM BIT(5) 365 #define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0) 366 #define TRBLIMITR_TRIG_MODE_SHIFT 3 367 #define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0) 368 #define TRBLIMITR_FILL_MODE_SHIFT 1 369 #define TRBLIMITR_ENABLE BIT(0) 370 #define TRBPTR_PTR_MASK GENMASK_ULL(63, 0) 371 #define TRBPTR_PTR_SHIFT 0 372 #define TRBBASER_BASE_MASK GENMASK_ULL(51, 0) 373 #define TRBBASER_BASE_SHIFT 12 374 #define TRBSR_EC_MASK GENMASK(5, 0) 375 #define TRBSR_EC_SHIFT 26 376 #define TRBSR_IRQ BIT(22) 377 #define TRBSR_TRG BIT(21) 378 #define TRBSR_WRAP BIT(20) 379 #define TRBSR_ABORT BIT(18) 380 #define TRBSR_STOP BIT(17) 381 #define TRBSR_MSS_MASK GENMASK(15, 0) 382 #define TRBSR_MSS_SHIFT 0 383 #define TRBSR_BSC_MASK GENMASK(5, 0) 384 #define TRBSR_BSC_SHIFT 0 385 #define TRBSR_FSC_MASK GENMASK(5, 0) 386 #define TRBSR_FSC_SHIFT 0 387 #define TRBMAR_SHARE_MASK GENMASK(1, 0) 388 #define TRBMAR_SHARE_SHIFT 8 389 #define TRBMAR_OUTER_MASK GENMASK(3, 0) 390 #define TRBMAR_OUTER_SHIFT 4 391 #define TRBMAR_INNER_MASK GENMASK(3, 0) 392 #define TRBMAR_INNER_SHIFT 0 393 #define TRBTRG_TRG_MASK GENMASK(31, 0) 394 #define TRBTRG_TRG_SHIFT 0 395 #define TRBIDR_FLAG BIT(5) 396 #define TRBIDR_PROG BIT(4) 397 #define TRBIDR_ALIGN_MASK GENMASK(3, 0) 398 #define TRBIDR_ALIGN_SHIFT 0 399 400 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 401 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 402 403 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6) 404 405 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 406 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 407 408 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 409 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 410 411 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 412 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 413 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 414 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 415 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 416 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 417 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 418 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 419 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 420 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 421 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 422 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 423 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 424 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 425 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 426 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 427 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 428 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 429 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 430 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 431 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 432 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 433 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 434 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 435 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 436 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 437 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 438 439 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 440 441 #define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7) 442 443 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 444 445 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) 446 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 447 448 #define SMIDR_EL1_IMPLEMENTER_SHIFT 24 449 #define SMIDR_EL1_SMPS_SHIFT 15 450 #define SMIDR_EL1_AFFINITY_SHIFT 0 451 452 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) 453 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) 454 455 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 456 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 457 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 458 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 459 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 460 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 461 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 462 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 463 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 464 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 465 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 466 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 467 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 468 469 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 470 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 471 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5) 472 473 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7) 474 475 /* Definitions for system register interface to AMU for ARMv8.4 onwards */ 476 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) 477 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) 478 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) 479 #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) 480 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) 481 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) 482 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) 483 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) 484 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) 485 486 /* 487 * Group 0 of activity monitors (architected): 488 * op0 op1 CRn CRm op2 489 * Counter: 11 011 1101 010:n<3> n<2:0> 490 * Type: 11 011 1101 011:n<3> n<2:0> 491 * n: 0-15 492 * 493 * Group 1 of activity monitors (auxiliary): 494 * op0 op1 CRn CRm op2 495 * Counter: 11 011 1101 110:n<3> n<2:0> 496 * Type: 11 011 1101 111:n<3> n<2:0> 497 * n: 0-15 498 */ 499 500 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) 501 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) 502 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) 503 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) 504 505 /* AMU v1: Fixed (architecturally defined) activity monitors */ 506 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) 507 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) 508 #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) 509 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) 510 511 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 512 513 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5) 514 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6) 515 516 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 517 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 518 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 519 520 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) 521 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) 522 523 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 524 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 525 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 526 527 #define __PMEV_op2(n) ((n) & 0x7) 528 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 529 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 530 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 531 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 532 533 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) 534 535 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) 536 #define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4) 537 #define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5) 538 #define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6) 539 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) 540 #define SYS_HCRX_EL2 sys_reg(3, 4, 1, 2, 2) 541 #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4) 542 #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5) 543 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) 544 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) 545 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) 546 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 547 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) 548 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 549 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 550 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0) 551 552 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 553 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 554 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 555 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 556 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 557 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 558 559 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 560 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 561 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 562 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 563 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 564 565 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 566 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 567 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 568 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 569 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 570 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 571 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 572 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 573 574 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 575 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 576 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 577 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 578 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 579 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 580 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 581 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 582 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 583 584 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 585 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 586 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 587 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 588 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 589 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 590 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 591 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 592 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 593 594 /* VHE encodings for architectural EL0/1 system registers */ 595 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) 596 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) 597 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) 598 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) 599 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) 600 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) 601 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) 602 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) 603 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) 604 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) 605 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) 606 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) 607 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) 608 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) 609 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) 610 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) 611 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) 612 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) 613 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) 614 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) 615 616 /* Common SCTLR_ELx flags. */ 617 #define SCTLR_ELx_ENTP2 (BIT(60)) 618 #define SCTLR_ELx_DSSBS (BIT(44)) 619 #define SCTLR_ELx_ATA (BIT(43)) 620 621 #define SCTLR_ELx_ENIA_SHIFT 31 622 623 #define SCTLR_ELx_ITFSB (BIT(37)) 624 #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT)) 625 #define SCTLR_ELx_ENIB (BIT(30)) 626 #define SCTLR_ELx_LSMAOE (BIT(29)) 627 #define SCTLR_ELx_nTLSMD (BIT(28)) 628 #define SCTLR_ELx_ENDA (BIT(27)) 629 #define SCTLR_ELx_EE (BIT(25)) 630 #define SCTLR_ELx_EIS (BIT(22)) 631 #define SCTLR_ELx_IESB (BIT(21)) 632 #define SCTLR_ELx_TSCXT (BIT(20)) 633 #define SCTLR_ELx_WXN (BIT(19)) 634 #define SCTLR_ELx_ENDB (BIT(13)) 635 #define SCTLR_ELx_I (BIT(12)) 636 #define SCTLR_ELx_EOS (BIT(11)) 637 #define SCTLR_ELx_SA (BIT(3)) 638 #define SCTLR_ELx_C (BIT(2)) 639 #define SCTLR_ELx_A (BIT(1)) 640 #define SCTLR_ELx_M (BIT(0)) 641 642 /* SCTLR_EL2 specific flags. */ 643 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 644 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 645 (BIT(29))) 646 647 #ifdef CONFIG_CPU_BIG_ENDIAN 648 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 649 #else 650 #define ENDIAN_SET_EL2 0 651 #endif 652 653 #define INIT_SCTLR_EL2_MMU_ON \ 654 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \ 655 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | \ 656 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1) 657 658 #define INIT_SCTLR_EL2_MMU_OFF \ 659 (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) 660 661 /* SCTLR_EL1 specific flags. */ 662 #ifdef CONFIG_CPU_BIG_ENDIAN 663 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 664 #else 665 #define ENDIAN_SET_EL1 0 666 #endif 667 668 #define INIT_SCTLR_EL1_MMU_OFF \ 669 (ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \ 670 SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) 671 672 #define INIT_SCTLR_EL1_MMU_ON \ 673 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \ 674 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | \ 675 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | \ 676 SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \ 677 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | \ 678 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \ 679 SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) 680 681 /* MAIR_ELx memory attributes (used by Linux) */ 682 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) 683 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) 684 #define MAIR_ATTR_NORMAL_NC UL(0x44) 685 #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0) 686 #define MAIR_ATTR_NORMAL UL(0xff) 687 #define MAIR_ATTR_MASK UL(0xff) 688 689 /* Position the attr at the correct index */ 690 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) 691 692 /* id_aa64pfr0 */ 693 #define ID_AA64PFR0_CSV3_SHIFT 60 694 #define ID_AA64PFR0_CSV2_SHIFT 56 695 #define ID_AA64PFR0_DIT_SHIFT 48 696 #define ID_AA64PFR0_AMU_SHIFT 44 697 #define ID_AA64PFR0_MPAM_SHIFT 40 698 #define ID_AA64PFR0_SEL2_SHIFT 36 699 #define ID_AA64PFR0_SVE_SHIFT 32 700 #define ID_AA64PFR0_RAS_SHIFT 28 701 #define ID_AA64PFR0_GIC_SHIFT 24 702 #define ID_AA64PFR0_ASIMD_SHIFT 20 703 #define ID_AA64PFR0_FP_SHIFT 16 704 #define ID_AA64PFR0_EL3_SHIFT 12 705 #define ID_AA64PFR0_EL2_SHIFT 8 706 #define ID_AA64PFR0_EL1_SHIFT 4 707 #define ID_AA64PFR0_EL0_SHIFT 0 708 709 #define ID_AA64PFR0_AMU 0x1 710 #define ID_AA64PFR0_SVE 0x1 711 #define ID_AA64PFR0_RAS_V1 0x1 712 #define ID_AA64PFR0_RAS_V1P1 0x2 713 #define ID_AA64PFR0_FP_NI 0xf 714 #define ID_AA64PFR0_FP_SUPPORTED 0x0 715 #define ID_AA64PFR0_ASIMD_NI 0xf 716 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 717 #define ID_AA64PFR0_ELx_64BIT_ONLY 0x1 718 #define ID_AA64PFR0_ELx_32BIT_64BIT 0x2 719 720 /* id_aa64pfr1 */ 721 #define ID_AA64PFR1_SME_SHIFT 24 722 #define ID_AA64PFR1_MPAMFRAC_SHIFT 16 723 #define ID_AA64PFR1_RASFRAC_SHIFT 12 724 #define ID_AA64PFR1_MTE_SHIFT 8 725 #define ID_AA64PFR1_SSBS_SHIFT 4 726 #define ID_AA64PFR1_BT_SHIFT 0 727 728 #define ID_AA64PFR1_SSBS_PSTATE_NI 0 729 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 730 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 731 #define ID_AA64PFR1_BT_BTI 0x1 732 #define ID_AA64PFR1_SME 1 733 734 #define ID_AA64PFR1_MTE_NI 0x0 735 #define ID_AA64PFR1_MTE_EL0 0x1 736 #define ID_AA64PFR1_MTE 0x2 737 #define ID_AA64PFR1_MTE_ASYMM 0x3 738 739 /* id_aa64mmfr0 */ 740 #define ID_AA64MMFR0_ECV_SHIFT 60 741 #define ID_AA64MMFR0_FGT_SHIFT 56 742 #define ID_AA64MMFR0_EXS_SHIFT 44 743 #define ID_AA64MMFR0_TGRAN4_2_SHIFT 40 744 #define ID_AA64MMFR0_TGRAN64_2_SHIFT 36 745 #define ID_AA64MMFR0_TGRAN16_2_SHIFT 32 746 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 747 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 748 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 749 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 750 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 751 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 752 #define ID_AA64MMFR0_ASID_SHIFT 4 753 #define ID_AA64MMFR0_PARANGE_SHIFT 0 754 755 #define ID_AA64MMFR0_ASID_8 0x0 756 #define ID_AA64MMFR0_ASID_16 0x2 757 758 #define ID_AA64MMFR0_TGRAN4_NI 0xf 759 #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0 760 #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7 761 #define ID_AA64MMFR0_TGRAN64_NI 0xf 762 #define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 0x0 763 #define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 0x7 764 #define ID_AA64MMFR0_TGRAN16_NI 0x0 765 #define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 0x1 766 #define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 0xf 767 768 #define ID_AA64MMFR0_PARANGE_32 0x0 769 #define ID_AA64MMFR0_PARANGE_36 0x1 770 #define ID_AA64MMFR0_PARANGE_40 0x2 771 #define ID_AA64MMFR0_PARANGE_42 0x3 772 #define ID_AA64MMFR0_PARANGE_44 0x4 773 #define ID_AA64MMFR0_PARANGE_48 0x5 774 #define ID_AA64MMFR0_PARANGE_52 0x6 775 776 #define ARM64_MIN_PARANGE_BITS 32 777 778 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0 779 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE 0x1 780 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN 0x2 781 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX 0x7 782 783 #ifdef CONFIG_ARM64_PA_BITS_52 784 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 785 #else 786 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48 787 #endif 788 789 /* id_aa64mmfr1 */ 790 #define ID_AA64MMFR1_ECBHB_SHIFT 60 791 #define ID_AA64MMFR1_TIDCP1_SHIFT 52 792 #define ID_AA64MMFR1_HCX_SHIFT 40 793 #define ID_AA64MMFR1_AFP_SHIFT 44 794 #define ID_AA64MMFR1_ETS_SHIFT 36 795 #define ID_AA64MMFR1_TWED_SHIFT 32 796 #define ID_AA64MMFR1_XNX_SHIFT 28 797 #define ID_AA64MMFR1_SPECSEI_SHIFT 24 798 #define ID_AA64MMFR1_PAN_SHIFT 20 799 #define ID_AA64MMFR1_LOR_SHIFT 16 800 #define ID_AA64MMFR1_HPD_SHIFT 12 801 #define ID_AA64MMFR1_VHE_SHIFT 8 802 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 803 #define ID_AA64MMFR1_HADBS_SHIFT 0 804 805 #define ID_AA64MMFR1_VMIDBITS_8 0 806 #define ID_AA64MMFR1_VMIDBITS_16 2 807 808 #define ID_AA64MMFR1_TIDCP1_NI 0 809 #define ID_AA64MMFR1_TIDCP1_IMP 1 810 811 /* id_aa64mmfr2 */ 812 #define ID_AA64MMFR2_E0PD_SHIFT 60 813 #define ID_AA64MMFR2_EVT_SHIFT 56 814 #define ID_AA64MMFR2_BBM_SHIFT 52 815 #define ID_AA64MMFR2_TTL_SHIFT 48 816 #define ID_AA64MMFR2_FWB_SHIFT 40 817 #define ID_AA64MMFR2_IDS_SHIFT 36 818 #define ID_AA64MMFR2_AT_SHIFT 32 819 #define ID_AA64MMFR2_ST_SHIFT 28 820 #define ID_AA64MMFR2_NV_SHIFT 24 821 #define ID_AA64MMFR2_CCIDX_SHIFT 20 822 #define ID_AA64MMFR2_LVA_SHIFT 16 823 #define ID_AA64MMFR2_IESB_SHIFT 12 824 #define ID_AA64MMFR2_LSM_SHIFT 8 825 #define ID_AA64MMFR2_UAO_SHIFT 4 826 #define ID_AA64MMFR2_CNP_SHIFT 0 827 828 /* id_aa64dfr0 */ 829 #define ID_AA64DFR0_MTPMU_SHIFT 48 830 #define ID_AA64DFR0_TRBE_SHIFT 44 831 #define ID_AA64DFR0_TRACE_FILT_SHIFT 40 832 #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 833 #define ID_AA64DFR0_PMSVER_SHIFT 32 834 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 835 #define ID_AA64DFR0_WRPS_SHIFT 20 836 #define ID_AA64DFR0_BRPS_SHIFT 12 837 #define ID_AA64DFR0_PMUVER_SHIFT 8 838 #define ID_AA64DFR0_TRACEVER_SHIFT 4 839 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 840 841 #define ID_AA64DFR0_PMUVER_8_0 0x1 842 #define ID_AA64DFR0_PMUVER_8_1 0x4 843 #define ID_AA64DFR0_PMUVER_8_4 0x5 844 #define ID_AA64DFR0_PMUVER_8_5 0x6 845 #define ID_AA64DFR0_PMUVER_8_7 0x7 846 #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf 847 848 #define ID_AA64DFR0_PMSVER_8_2 0x1 849 #define ID_AA64DFR0_PMSVER_8_3 0x2 850 851 #define ID_DFR0_PERFMON_SHIFT 24 852 853 #define ID_DFR0_PERFMON_8_0 0x3 854 #define ID_DFR0_PERFMON_8_1 0x4 855 #define ID_DFR0_PERFMON_8_4 0x5 856 #define ID_DFR0_PERFMON_8_5 0x6 857 858 #define ID_ISAR4_SWP_FRAC_SHIFT 28 859 #define ID_ISAR4_PSR_M_SHIFT 24 860 #define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT 20 861 #define ID_ISAR4_BARRIER_SHIFT 16 862 #define ID_ISAR4_SMC_SHIFT 12 863 #define ID_ISAR4_WRITEBACK_SHIFT 8 864 #define ID_ISAR4_WITHSHIFTS_SHIFT 4 865 #define ID_ISAR4_UNPRIV_SHIFT 0 866 867 #define ID_DFR1_MTPMU_SHIFT 0 868 869 #define ID_ISAR0_DIVIDE_SHIFT 24 870 #define ID_ISAR0_DEBUG_SHIFT 20 871 #define ID_ISAR0_COPROC_SHIFT 16 872 #define ID_ISAR0_CMPBRANCH_SHIFT 12 873 #define ID_ISAR0_BITFIELD_SHIFT 8 874 #define ID_ISAR0_BITCOUNT_SHIFT 4 875 #define ID_ISAR0_SWAP_SHIFT 0 876 877 #define ID_ISAR5_RDM_SHIFT 24 878 #define ID_ISAR5_CRC32_SHIFT 16 879 #define ID_ISAR5_SHA2_SHIFT 12 880 #define ID_ISAR5_SHA1_SHIFT 8 881 #define ID_ISAR5_AES_SHIFT 4 882 #define ID_ISAR5_SEVL_SHIFT 0 883 884 #define ID_ISAR6_I8MM_SHIFT 24 885 #define ID_ISAR6_BF16_SHIFT 20 886 #define ID_ISAR6_SPECRES_SHIFT 16 887 #define ID_ISAR6_SB_SHIFT 12 888 #define ID_ISAR6_FHM_SHIFT 8 889 #define ID_ISAR6_DP_SHIFT 4 890 #define ID_ISAR6_JSCVT_SHIFT 0 891 892 #define ID_MMFR0_INNERSHR_SHIFT 28 893 #define ID_MMFR0_FCSE_SHIFT 24 894 #define ID_MMFR0_AUXREG_SHIFT 20 895 #define ID_MMFR0_TCM_SHIFT 16 896 #define ID_MMFR0_SHARELVL_SHIFT 12 897 #define ID_MMFR0_OUTERSHR_SHIFT 8 898 #define ID_MMFR0_PMSA_SHIFT 4 899 #define ID_MMFR0_VMSA_SHIFT 0 900 901 #define ID_MMFR4_EVT_SHIFT 28 902 #define ID_MMFR4_CCIDX_SHIFT 24 903 #define ID_MMFR4_LSM_SHIFT 20 904 #define ID_MMFR4_HPDS_SHIFT 16 905 #define ID_MMFR4_CNP_SHIFT 12 906 #define ID_MMFR4_XNX_SHIFT 8 907 #define ID_MMFR4_AC2_SHIFT 4 908 #define ID_MMFR4_SPECSEI_SHIFT 0 909 910 #define ID_MMFR5_ETS_SHIFT 0 911 912 #define ID_PFR0_DIT_SHIFT 24 913 #define ID_PFR0_CSV2_SHIFT 16 914 #define ID_PFR0_STATE3_SHIFT 12 915 #define ID_PFR0_STATE2_SHIFT 8 916 #define ID_PFR0_STATE1_SHIFT 4 917 #define ID_PFR0_STATE0_SHIFT 0 918 919 #define ID_DFR0_PERFMON_SHIFT 24 920 #define ID_DFR0_MPROFDBG_SHIFT 20 921 #define ID_DFR0_MMAPTRC_SHIFT 16 922 #define ID_DFR0_COPTRC_SHIFT 12 923 #define ID_DFR0_MMAPDBG_SHIFT 8 924 #define ID_DFR0_COPSDBG_SHIFT 4 925 #define ID_DFR0_COPDBG_SHIFT 0 926 927 #define ID_PFR2_SSBS_SHIFT 4 928 #define ID_PFR2_CSV3_SHIFT 0 929 930 #define MVFR0_FPROUND_SHIFT 28 931 #define MVFR0_FPSHVEC_SHIFT 24 932 #define MVFR0_FPSQRT_SHIFT 20 933 #define MVFR0_FPDIVIDE_SHIFT 16 934 #define MVFR0_FPTRAP_SHIFT 12 935 #define MVFR0_FPDP_SHIFT 8 936 #define MVFR0_FPSP_SHIFT 4 937 #define MVFR0_SIMD_SHIFT 0 938 939 #define MVFR1_SIMDFMAC_SHIFT 28 940 #define MVFR1_FPHP_SHIFT 24 941 #define MVFR1_SIMDHP_SHIFT 20 942 #define MVFR1_SIMDSP_SHIFT 16 943 #define MVFR1_SIMDINT_SHIFT 12 944 #define MVFR1_SIMDLS_SHIFT 8 945 #define MVFR1_FPDNAN_SHIFT 4 946 #define MVFR1_FPFTZ_SHIFT 0 947 948 #define ID_PFR1_GIC_SHIFT 28 949 #define ID_PFR1_VIRT_FRAC_SHIFT 24 950 #define ID_PFR1_SEC_FRAC_SHIFT 20 951 #define ID_PFR1_GENTIMER_SHIFT 16 952 #define ID_PFR1_VIRTUALIZATION_SHIFT 12 953 #define ID_PFR1_MPROGMOD_SHIFT 8 954 #define ID_PFR1_SECURITY_SHIFT 4 955 #define ID_PFR1_PROGMOD_SHIFT 0 956 957 #if defined(CONFIG_ARM64_4K_PAGES) 958 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 959 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 960 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 961 #define ID_AA64MMFR0_TGRAN_2_SHIFT ID_AA64MMFR0_TGRAN4_2_SHIFT 962 #elif defined(CONFIG_ARM64_16K_PAGES) 963 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 964 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 965 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 966 #define ID_AA64MMFR0_TGRAN_2_SHIFT ID_AA64MMFR0_TGRAN16_2_SHIFT 967 #elif defined(CONFIG_ARM64_64K_PAGES) 968 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 969 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 970 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 971 #define ID_AA64MMFR0_TGRAN_2_SHIFT ID_AA64MMFR0_TGRAN64_2_SHIFT 972 #endif 973 974 #define MVFR2_FPMISC_SHIFT 4 975 #define MVFR2_SIMDMISC_SHIFT 0 976 977 #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ 978 #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ 979 980 #define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */ 981 #define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */ 982 983 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ 984 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ 985 986 /* GCR_EL1 Definitions */ 987 #define SYS_GCR_EL1_RRND (BIT(16)) 988 #define SYS_GCR_EL1_EXCL_MASK 0xffffUL 989 990 #ifdef CONFIG_KASAN_HW_TAGS 991 /* 992 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it 993 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF. 994 */ 995 #define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf) 996 #define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf) 997 #define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN) 998 #define KERNEL_GCR_EL1_EXCL (SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL) 999 #else 1000 #define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK 1001 #endif 1002 1003 #define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL) 1004 1005 /* RGSR_EL1 Definitions */ 1006 #define SYS_RGSR_EL1_TAG_MASK 0xfUL 1007 #define SYS_RGSR_EL1_SEED_SHIFT 8 1008 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL 1009 1010 /* GMID_EL1 field definitions */ 1011 #define GMID_EL1_BS_SHIFT 0 1012 #define GMID_EL1_BS_SIZE 4 1013 1014 /* TFSR{,E0}_EL1 bit definitions */ 1015 #define SYS_TFSR_EL1_TF0_SHIFT 0 1016 #define SYS_TFSR_EL1_TF1_SHIFT 1 1017 #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) 1018 #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) 1019 1020 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 1021 #define SYS_MPIDR_SAFE_VAL (BIT(31)) 1022 1023 #define TRFCR_ELx_TS_SHIFT 5 1024 #define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) 1025 #define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) 1026 #define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) 1027 #define TRFCR_EL2_CX BIT(3) 1028 #define TRFCR_ELx_ExTRE BIT(1) 1029 #define TRFCR_ELx_E0TRE BIT(0) 1030 1031 /* HCRX_EL2 definitions */ 1032 #define HCRX_EL2_SMPME_MASK (1 << 5) 1033 1034 /* GIC Hypervisor interface registers */ 1035 /* ICH_MISR_EL2 bit definitions */ 1036 #define ICH_MISR_EOI (1 << 0) 1037 #define ICH_MISR_U (1 << 1) 1038 1039 /* ICH_LR*_EL2 bit definitions */ 1040 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) 1041 1042 #define ICH_LR_EOI (1ULL << 41) 1043 #define ICH_LR_GROUP (1ULL << 60) 1044 #define ICH_LR_HW (1ULL << 61) 1045 #define ICH_LR_STATE (3ULL << 62) 1046 #define ICH_LR_PENDING_BIT (1ULL << 62) 1047 #define ICH_LR_ACTIVE_BIT (1ULL << 63) 1048 #define ICH_LR_PHYS_ID_SHIFT 32 1049 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) 1050 #define ICH_LR_PRIORITY_SHIFT 48 1051 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) 1052 1053 /* ICH_HCR_EL2 bit definitions */ 1054 #define ICH_HCR_EN (1 << 0) 1055 #define ICH_HCR_UIE (1 << 1) 1056 #define ICH_HCR_NPIE (1 << 3) 1057 #define ICH_HCR_TC (1 << 10) 1058 #define ICH_HCR_TALL0 (1 << 11) 1059 #define ICH_HCR_TALL1 (1 << 12) 1060 #define ICH_HCR_TDIR (1 << 14) 1061 #define ICH_HCR_EOIcount_SHIFT 27 1062 #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT) 1063 1064 /* ICH_VMCR_EL2 bit definitions */ 1065 #define ICH_VMCR_ACK_CTL_SHIFT 2 1066 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) 1067 #define ICH_VMCR_FIQ_EN_SHIFT 3 1068 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) 1069 #define ICH_VMCR_CBPR_SHIFT 4 1070 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) 1071 #define ICH_VMCR_EOIM_SHIFT 9 1072 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT) 1073 #define ICH_VMCR_BPR1_SHIFT 18 1074 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) 1075 #define ICH_VMCR_BPR0_SHIFT 21 1076 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) 1077 #define ICH_VMCR_PMR_SHIFT 24 1078 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) 1079 #define ICH_VMCR_ENG0_SHIFT 0 1080 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) 1081 #define ICH_VMCR_ENG1_SHIFT 1 1082 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT) 1083 1084 /* ICH_VTR_EL2 bit definitions */ 1085 #define ICH_VTR_PRI_BITS_SHIFT 29 1086 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT) 1087 #define ICH_VTR_ID_BITS_SHIFT 23 1088 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT) 1089 #define ICH_VTR_SEIS_SHIFT 22 1090 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT) 1091 #define ICH_VTR_A3V_SHIFT 21 1092 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT) 1093 #define ICH_VTR_TDS_SHIFT 19 1094 #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT) 1095 1096 /* HFG[WR]TR_EL2 bit definitions */ 1097 #define HFGxTR_EL2_nTPIDR2_EL0_SHIFT 55 1098 #define HFGxTR_EL2_nTPIDR2_EL0_MASK BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT) 1099 #define HFGxTR_EL2_nSMPRI_EL1_SHIFT 54 1100 #define HFGxTR_EL2_nSMPRI_EL1_MASK BIT_MASK(HFGxTR_EL2_nSMPRI_EL1_SHIFT) 1101 1102 #define ARM64_FEATURE_FIELD_BITS 4 1103 1104 /* Create a mask for the feature bits of the specified feature. */ 1105 #define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT)) 1106 1107 #ifdef __ASSEMBLY__ 1108 1109 .macro mrs_s, rt, sreg 1110 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt)) 1111 .endm 1112 1113 .macro msr_s, sreg, rt 1114 __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt)) 1115 .endm 1116 1117 #else 1118 1119 #include <linux/build_bug.h> 1120 #include <linux/types.h> 1121 #include <asm/alternative.h> 1122 1123 #define DEFINE_MRS_S \ 1124 __DEFINE_ASM_GPR_NUMS \ 1125 " .macro mrs_s, rt, sreg\n" \ 1126 __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \ 1127 " .endm\n" 1128 1129 #define DEFINE_MSR_S \ 1130 __DEFINE_ASM_GPR_NUMS \ 1131 " .macro msr_s, sreg, rt\n" \ 1132 __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \ 1133 " .endm\n" 1134 1135 #define UNDEFINE_MRS_S \ 1136 " .purgem mrs_s\n" 1137 1138 #define UNDEFINE_MSR_S \ 1139 " .purgem msr_s\n" 1140 1141 #define __mrs_s(v, r) \ 1142 DEFINE_MRS_S \ 1143 " mrs_s " v ", " __stringify(r) "\n" \ 1144 UNDEFINE_MRS_S 1145 1146 #define __msr_s(r, v) \ 1147 DEFINE_MSR_S \ 1148 " msr_s " __stringify(r) ", " v "\n" \ 1149 UNDEFINE_MSR_S 1150 1151 /* 1152 * Unlike read_cpuid, calls to read_sysreg are never expected to be 1153 * optimized away or replaced with synthetic values. 1154 */ 1155 #define read_sysreg(r) ({ \ 1156 u64 __val; \ 1157 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 1158 __val; \ 1159 }) 1160 1161 /* 1162 * The "Z" constraint normally means a zero immediate, but when combined with 1163 * the "%x0" template means XZR. 1164 */ 1165 #define write_sysreg(v, r) do { \ 1166 u64 __val = (u64)(v); \ 1167 asm volatile("msr " __stringify(r) ", %x0" \ 1168 : : "rZ" (__val)); \ 1169 } while (0) 1170 1171 /* 1172 * For registers without architectural names, or simply unsupported by 1173 * GAS. 1174 */ 1175 #define read_sysreg_s(r) ({ \ 1176 u64 __val; \ 1177 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ 1178 __val; \ 1179 }) 1180 1181 #define write_sysreg_s(v, r) do { \ 1182 u64 __val = (u64)(v); \ 1183 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ 1184 } while (0) 1185 1186 /* 1187 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 1188 * set mask are set. Other bits are left as-is. 1189 */ 1190 #define sysreg_clear_set(sysreg, clear, set) do { \ 1191 u64 __scs_val = read_sysreg(sysreg); \ 1192 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1193 if (__scs_new != __scs_val) \ 1194 write_sysreg(__scs_new, sysreg); \ 1195 } while (0) 1196 1197 #define sysreg_clear_set_s(sysreg, clear, set) do { \ 1198 u64 __scs_val = read_sysreg_s(sysreg); \ 1199 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1200 if (__scs_new != __scs_val) \ 1201 write_sysreg_s(__scs_new, sysreg); \ 1202 } while (0) 1203 1204 #define read_sysreg_par() ({ \ 1205 u64 par; \ 1206 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1207 par = read_sysreg(par_el1); \ 1208 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1209 par; \ 1210 }) 1211 1212 #endif 1213 1214 #define SYS_FIELD_GET(reg, field, val) \ 1215 FIELD_GET(reg##_##field##_MASK, val) 1216 1217 #define SYS_FIELD_PREP(reg, field, val) \ 1218 FIELD_PREP(reg##_##field##_MASK, val) 1219 1220 #define SYS_FIELD_PREP_ENUM(reg, field, val) \ 1221 FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val) 1222 1223 #endif /* __ASM_SYSREG_H */ 1224