1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #ifndef __ASM_SYSREG_H 10 #define __ASM_SYSREG_H 11 12 #include <linux/bits.h> 13 #include <linux/stringify.h> 14 #include <linux/kasan-tags.h> 15 16 #include <asm/gpr-num.h> 17 18 /* 19 * ARMv8 ARM reserves the following encoding for system registers: 20 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 21 * C5.2, version:ARM DDI 0487A.f) 22 * [20-19] : Op0 23 * [18-16] : Op1 24 * [15-12] : CRn 25 * [11-8] : CRm 26 * [7-5] : Op2 27 */ 28 #define Op0_shift 19 29 #define Op0_mask 0x3 30 #define Op1_shift 16 31 #define Op1_mask 0x7 32 #define CRn_shift 12 33 #define CRn_mask 0xf 34 #define CRm_shift 8 35 #define CRm_mask 0xf 36 #define Op2_shift 5 37 #define Op2_mask 0x7 38 39 #define sys_reg(op0, op1, crn, crm, op2) \ 40 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 41 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 42 ((op2) << Op2_shift)) 43 44 #define sys_insn sys_reg 45 46 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 47 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 48 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 49 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 50 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 51 52 #ifndef CONFIG_BROKEN_GAS_INST 53 54 #ifdef __ASSEMBLY__ 55 // The space separator is omitted so that __emit_inst(x) can be parsed as 56 // either an assembler directive or an assembler macro argument. 57 #define __emit_inst(x) .inst(x) 58 #else 59 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 60 #endif 61 62 #else /* CONFIG_BROKEN_GAS_INST */ 63 64 #ifndef CONFIG_CPU_BIG_ENDIAN 65 #define __INSTR_BSWAP(x) (x) 66 #else /* CONFIG_CPU_BIG_ENDIAN */ 67 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 68 (((x) << 8) & 0x00ff0000) | \ 69 (((x) >> 8) & 0x0000ff00) | \ 70 (((x) >> 24) & 0x000000ff)) 71 #endif /* CONFIG_CPU_BIG_ENDIAN */ 72 73 #ifdef __ASSEMBLY__ 74 #define __emit_inst(x) .long __INSTR_BSWAP(x) 75 #else /* __ASSEMBLY__ */ 76 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 77 #endif /* __ASSEMBLY__ */ 78 79 #endif /* CONFIG_BROKEN_GAS_INST */ 80 81 /* 82 * Instructions for modifying PSTATE fields. 83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 84 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 85 * for accessing PSTATE fields have the following encoding: 86 * Op0 = 0, CRn = 4 87 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 88 * CRm = Imm4 for the instruction. 89 * Rt = 0x1f 90 */ 91 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 92 #define PSTATE_Imm_shift CRm_shift 93 94 #define PSTATE_PAN pstate_field(0, 4) 95 #define PSTATE_UAO pstate_field(0, 3) 96 #define PSTATE_SSBS pstate_field(3, 1) 97 #define PSTATE_TCO pstate_field(3, 4) 98 99 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) 100 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) 101 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) 102 #define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift)) 103 104 #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) 105 #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) 106 #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x)) 107 108 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ 109 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) 110 111 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) 112 113 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 114 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 115 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 116 117 /* 118 * System registers, organised loosely by encoding but grouped together 119 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. 120 */ 121 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 122 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 123 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 124 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 125 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 126 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 127 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 128 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 129 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 130 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 131 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 132 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 133 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 134 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 135 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 136 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 137 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 138 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 139 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 140 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 141 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 142 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 143 144 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 145 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 146 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 147 148 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 149 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 150 #define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) 151 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 152 #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5) 153 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 154 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 155 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 156 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 157 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 158 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 159 #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) 160 161 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 162 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 163 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 164 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 165 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 166 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 167 #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) 168 169 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 170 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 171 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 172 173 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 174 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 175 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) 176 177 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 178 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 179 180 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 181 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 182 183 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 184 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 185 186 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 187 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 188 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 189 190 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 191 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 192 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 193 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) 194 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) 195 196 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) 197 #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) 198 199 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 200 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 201 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 202 203 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 204 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 205 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 206 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 207 208 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 209 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 210 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 211 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 212 213 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 214 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 215 216 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) 217 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) 218 219 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 220 221 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 222 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 223 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 224 225 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 226 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 227 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 228 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 229 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 230 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 231 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 232 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 233 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0) 234 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1) 235 236 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 237 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 238 239 #define SYS_PAR_EL1_F BIT(0) 240 #define SYS_PAR_EL1_FST GENMASK(6, 1) 241 242 /*** Statistical Profiling Extension ***/ 243 /* ID registers */ 244 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 245 #define SYS_PMSIDR_EL1_FE_SHIFT 0 246 #define SYS_PMSIDR_EL1_FT_SHIFT 1 247 #define SYS_PMSIDR_EL1_FL_SHIFT 2 248 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 249 #define SYS_PMSIDR_EL1_LDS_SHIFT 4 250 #define SYS_PMSIDR_EL1_ERND_SHIFT 5 251 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 252 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 253 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 254 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 255 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 256 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 257 258 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 259 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 260 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 261 #define SYS_PMBIDR_EL1_P_SHIFT 4 262 #define SYS_PMBIDR_EL1_F_SHIFT 5 263 264 /* Sampling controls */ 265 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 266 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0 267 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1 268 #define SYS_PMSCR_EL1_CX_SHIFT 3 269 #define SYS_PMSCR_EL1_PA_SHIFT 4 270 #define SYS_PMSCR_EL1_TS_SHIFT 5 271 #define SYS_PMSCR_EL1_PCT_SHIFT 6 272 273 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 274 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 275 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1 276 #define SYS_PMSCR_EL2_CX_SHIFT 3 277 #define SYS_PMSCR_EL2_PA_SHIFT 4 278 #define SYS_PMSCR_EL2_TS_SHIFT 5 279 #define SYS_PMSCR_EL2_PCT_SHIFT 6 280 281 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 282 283 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 284 #define SYS_PMSIRR_EL1_RND_SHIFT 0 285 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 286 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 287 288 /* Filtering controls */ 289 #define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1) 290 291 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 292 #define SYS_PMSFCR_EL1_FE_SHIFT 0 293 #define SYS_PMSFCR_EL1_FT_SHIFT 1 294 #define SYS_PMSFCR_EL1_FL_SHIFT 2 295 #define SYS_PMSFCR_EL1_B_SHIFT 16 296 #define SYS_PMSFCR_EL1_LD_SHIFT 17 297 #define SYS_PMSFCR_EL1_ST_SHIFT 18 298 299 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 300 #define SYS_PMSEVFR_EL1_RES0_8_2 \ 301 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ 302 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) 303 #define SYS_PMSEVFR_EL1_RES0_8_3 \ 304 (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) 305 306 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 307 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 308 309 /* Buffer controls */ 310 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 311 #define SYS_PMBLIMITR_EL1_E_SHIFT 0 312 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1 313 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 314 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 315 316 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 317 318 /* Buffer error reporting */ 319 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 320 #define SYS_PMBSR_EL1_COLL_SHIFT 16 321 #define SYS_PMBSR_EL1_S_SHIFT 17 322 #define SYS_PMBSR_EL1_EA_SHIFT 18 323 #define SYS_PMBSR_EL1_DL_SHIFT 19 324 #define SYS_PMBSR_EL1_EC_SHIFT 26 325 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL 326 327 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 328 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 329 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 330 331 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 332 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 333 334 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 335 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 336 337 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 338 339 /*** End of Statistical Profiling Extension ***/ 340 341 /* 342 * TRBE Registers 343 */ 344 #define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0) 345 #define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1) 346 #define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2) 347 #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3) 348 #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4) 349 #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) 350 #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7) 351 352 #define TRBLIMITR_LIMIT_MASK GENMASK_ULL(51, 0) 353 #define TRBLIMITR_LIMIT_SHIFT 12 354 #define TRBLIMITR_NVM BIT(5) 355 #define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0) 356 #define TRBLIMITR_TRIG_MODE_SHIFT 3 357 #define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0) 358 #define TRBLIMITR_FILL_MODE_SHIFT 1 359 #define TRBLIMITR_ENABLE BIT(0) 360 #define TRBPTR_PTR_MASK GENMASK_ULL(63, 0) 361 #define TRBPTR_PTR_SHIFT 0 362 #define TRBBASER_BASE_MASK GENMASK_ULL(51, 0) 363 #define TRBBASER_BASE_SHIFT 12 364 #define TRBSR_EC_MASK GENMASK(5, 0) 365 #define TRBSR_EC_SHIFT 26 366 #define TRBSR_IRQ BIT(22) 367 #define TRBSR_TRG BIT(21) 368 #define TRBSR_WRAP BIT(20) 369 #define TRBSR_ABORT BIT(18) 370 #define TRBSR_STOP BIT(17) 371 #define TRBSR_MSS_MASK GENMASK(15, 0) 372 #define TRBSR_MSS_SHIFT 0 373 #define TRBSR_BSC_MASK GENMASK(5, 0) 374 #define TRBSR_BSC_SHIFT 0 375 #define TRBSR_FSC_MASK GENMASK(5, 0) 376 #define TRBSR_FSC_SHIFT 0 377 #define TRBMAR_SHARE_MASK GENMASK(1, 0) 378 #define TRBMAR_SHARE_SHIFT 8 379 #define TRBMAR_OUTER_MASK GENMASK(3, 0) 380 #define TRBMAR_OUTER_SHIFT 4 381 #define TRBMAR_INNER_MASK GENMASK(3, 0) 382 #define TRBMAR_INNER_SHIFT 0 383 #define TRBTRG_TRG_MASK GENMASK(31, 0) 384 #define TRBTRG_TRG_SHIFT 0 385 #define TRBIDR_FLAG BIT(5) 386 #define TRBIDR_PROG BIT(4) 387 #define TRBIDR_ALIGN_MASK GENMASK(3, 0) 388 #define TRBIDR_ALIGN_SHIFT 0 389 390 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 391 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 392 393 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6) 394 395 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 396 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 397 398 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) 399 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) 400 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) 401 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) 402 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) 403 404 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 405 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 406 407 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 408 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 409 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 410 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 411 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 412 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 413 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 414 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 415 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 416 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 417 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 418 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 419 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 420 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 421 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 422 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 423 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 424 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 425 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 426 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 427 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 428 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 429 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 430 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 431 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 432 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 433 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 434 435 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 436 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 437 438 #define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7) 439 440 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 441 442 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) 443 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 444 #define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4) 445 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 446 447 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 448 449 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 450 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 451 452 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) 453 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) 454 455 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 456 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 457 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 458 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 459 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 460 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 461 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 462 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 463 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 464 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 465 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 466 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 467 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 468 469 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 470 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 471 472 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7) 473 474 /* Definitions for system register interface to AMU for ARMv8.4 onwards */ 475 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) 476 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) 477 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) 478 #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) 479 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) 480 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) 481 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) 482 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) 483 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) 484 485 /* 486 * Group 0 of activity monitors (architected): 487 * op0 op1 CRn CRm op2 488 * Counter: 11 011 1101 010:n<3> n<2:0> 489 * Type: 11 011 1101 011:n<3> n<2:0> 490 * n: 0-15 491 * 492 * Group 1 of activity monitors (auxiliary): 493 * op0 op1 CRn CRm op2 494 * Counter: 11 011 1101 110:n<3> n<2:0> 495 * Type: 11 011 1101 111:n<3> n<2:0> 496 * n: 0-15 497 */ 498 499 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) 500 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) 501 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) 502 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) 503 504 /* AMU v1: Fixed (architecturally defined) activity monitors */ 505 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) 506 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) 507 #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) 508 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) 509 510 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 511 512 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5) 513 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6) 514 515 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 516 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 517 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 518 519 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) 520 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) 521 522 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 523 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 524 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 525 526 #define __PMEV_op2(n) ((n) & 0x7) 527 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 528 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 529 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 530 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 531 532 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) 533 534 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) 535 #define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4) 536 #define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5) 537 #define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6) 538 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 539 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) 540 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 541 #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4) 542 #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5) 543 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) 544 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) 545 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) 546 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 547 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) 548 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 549 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 550 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0) 551 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) 552 553 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 554 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 555 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 556 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 557 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 558 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 559 560 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 561 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 562 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 563 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 564 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 565 566 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 567 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 568 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 569 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 570 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 571 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 572 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 573 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 574 575 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 576 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 577 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 578 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 579 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 580 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 581 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 582 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 583 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 584 585 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 586 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 587 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 588 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 589 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 590 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 591 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 592 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 593 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 594 595 /* VHE encodings for architectural EL0/1 system registers */ 596 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) 597 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) 598 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) 599 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) 600 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) 601 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) 602 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) 603 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) 604 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) 605 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) 606 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) 607 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) 608 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) 609 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) 610 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) 611 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) 612 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) 613 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) 614 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) 615 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) 616 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) 617 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) 618 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) 619 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) 620 621 /* Common SCTLR_ELx flags. */ 622 #define SCTLR_ELx_DSSBS (BIT(44)) 623 #define SCTLR_ELx_ATA (BIT(43)) 624 625 #define SCTLR_ELx_TCF_SHIFT 40 626 #define SCTLR_ELx_TCF_NONE (UL(0x0) << SCTLR_ELx_TCF_SHIFT) 627 #define SCTLR_ELx_TCF_SYNC (UL(0x1) << SCTLR_ELx_TCF_SHIFT) 628 #define SCTLR_ELx_TCF_ASYNC (UL(0x2) << SCTLR_ELx_TCF_SHIFT) 629 #define SCTLR_ELx_TCF_ASYMM (UL(0x3) << SCTLR_ELx_TCF_SHIFT) 630 #define SCTLR_ELx_TCF_MASK (UL(0x3) << SCTLR_ELx_TCF_SHIFT) 631 632 #define SCTLR_ELx_ENIA_SHIFT 31 633 634 #define SCTLR_ELx_ITFSB (BIT(37)) 635 #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT)) 636 #define SCTLR_ELx_ENIB (BIT(30)) 637 #define SCTLR_ELx_ENDA (BIT(27)) 638 #define SCTLR_ELx_EE (BIT(25)) 639 #define SCTLR_ELx_IESB (BIT(21)) 640 #define SCTLR_ELx_WXN (BIT(19)) 641 #define SCTLR_ELx_ENDB (BIT(13)) 642 #define SCTLR_ELx_I (BIT(12)) 643 #define SCTLR_ELx_SA (BIT(3)) 644 #define SCTLR_ELx_C (BIT(2)) 645 #define SCTLR_ELx_A (BIT(1)) 646 #define SCTLR_ELx_M (BIT(0)) 647 648 /* SCTLR_EL2 specific flags. */ 649 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 650 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 651 (BIT(29))) 652 653 #ifdef CONFIG_CPU_BIG_ENDIAN 654 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 655 #else 656 #define ENDIAN_SET_EL2 0 657 #endif 658 659 #define INIT_SCTLR_EL2_MMU_ON \ 660 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \ 661 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | \ 662 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1) 663 664 #define INIT_SCTLR_EL2_MMU_OFF \ 665 (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) 666 667 /* SCTLR_EL1 specific flags. */ 668 #define SCTLR_EL1_EPAN (BIT(57)) 669 #define SCTLR_EL1_ATA0 (BIT(42)) 670 671 #define SCTLR_EL1_TCF0_SHIFT 38 672 #define SCTLR_EL1_TCF0_NONE (UL(0x0) << SCTLR_EL1_TCF0_SHIFT) 673 #define SCTLR_EL1_TCF0_SYNC (UL(0x1) << SCTLR_EL1_TCF0_SHIFT) 674 #define SCTLR_EL1_TCF0_ASYNC (UL(0x2) << SCTLR_EL1_TCF0_SHIFT) 675 #define SCTLR_EL1_TCF0_ASYMM (UL(0x3) << SCTLR_EL1_TCF0_SHIFT) 676 #define SCTLR_EL1_TCF0_MASK (UL(0x3) << SCTLR_EL1_TCF0_SHIFT) 677 678 #define SCTLR_EL1_BT1 (BIT(36)) 679 #define SCTLR_EL1_BT0 (BIT(35)) 680 #define SCTLR_EL1_UCI (BIT(26)) 681 #define SCTLR_EL1_E0E (BIT(24)) 682 #define SCTLR_EL1_SPAN (BIT(23)) 683 #define SCTLR_EL1_NTWE (BIT(18)) 684 #define SCTLR_EL1_NTWI (BIT(16)) 685 #define SCTLR_EL1_UCT (BIT(15)) 686 #define SCTLR_EL1_DZE (BIT(14)) 687 #define SCTLR_EL1_UMA (BIT(9)) 688 #define SCTLR_EL1_SED (BIT(8)) 689 #define SCTLR_EL1_ITD (BIT(7)) 690 #define SCTLR_EL1_CP15BEN (BIT(5)) 691 #define SCTLR_EL1_SA0 (BIT(4)) 692 693 #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \ 694 (BIT(29))) 695 696 #ifdef CONFIG_CPU_BIG_ENDIAN 697 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 698 #else 699 #define ENDIAN_SET_EL1 0 700 #endif 701 702 #define INIT_SCTLR_EL1_MMU_OFF \ 703 (ENDIAN_SET_EL1 | SCTLR_EL1_RES1) 704 705 #define INIT_SCTLR_EL1_MMU_ON \ 706 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_EL1_SA0 | \ 707 SCTLR_EL1_SED | SCTLR_ELx_I | SCTLR_EL1_DZE | SCTLR_EL1_UCT | \ 708 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \ 709 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | SCTLR_EL1_RES1) 710 711 /* MAIR_ELx memory attributes (used by Linux) */ 712 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) 713 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) 714 #define MAIR_ATTR_NORMAL_NC UL(0x44) 715 #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0) 716 #define MAIR_ATTR_NORMAL UL(0xff) 717 #define MAIR_ATTR_MASK UL(0xff) 718 719 /* Position the attr at the correct index */ 720 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) 721 722 /* id_aa64isar0 */ 723 #define ID_AA64ISAR0_RNDR_SHIFT 60 724 #define ID_AA64ISAR0_TLB_SHIFT 56 725 #define ID_AA64ISAR0_TS_SHIFT 52 726 #define ID_AA64ISAR0_FHM_SHIFT 48 727 #define ID_AA64ISAR0_DP_SHIFT 44 728 #define ID_AA64ISAR0_SM4_SHIFT 40 729 #define ID_AA64ISAR0_SM3_SHIFT 36 730 #define ID_AA64ISAR0_SHA3_SHIFT 32 731 #define ID_AA64ISAR0_RDM_SHIFT 28 732 #define ID_AA64ISAR0_ATOMICS_SHIFT 20 733 #define ID_AA64ISAR0_CRC32_SHIFT 16 734 #define ID_AA64ISAR0_SHA2_SHIFT 12 735 #define ID_AA64ISAR0_SHA1_SHIFT 8 736 #define ID_AA64ISAR0_AES_SHIFT 4 737 738 #define ID_AA64ISAR0_TLB_RANGE_NI 0x0 739 #define ID_AA64ISAR0_TLB_RANGE 0x2 740 741 /* id_aa64isar1 */ 742 #define ID_AA64ISAR1_I8MM_SHIFT 52 743 #define ID_AA64ISAR1_DGH_SHIFT 48 744 #define ID_AA64ISAR1_BF16_SHIFT 44 745 #define ID_AA64ISAR1_SPECRES_SHIFT 40 746 #define ID_AA64ISAR1_SB_SHIFT 36 747 #define ID_AA64ISAR1_FRINTTS_SHIFT 32 748 #define ID_AA64ISAR1_GPI_SHIFT 28 749 #define ID_AA64ISAR1_GPA_SHIFT 24 750 #define ID_AA64ISAR1_LRCPC_SHIFT 20 751 #define ID_AA64ISAR1_FCMA_SHIFT 16 752 #define ID_AA64ISAR1_JSCVT_SHIFT 12 753 #define ID_AA64ISAR1_API_SHIFT 8 754 #define ID_AA64ISAR1_APA_SHIFT 4 755 #define ID_AA64ISAR1_DPB_SHIFT 0 756 757 #define ID_AA64ISAR1_APA_NI 0x0 758 #define ID_AA64ISAR1_APA_ARCHITECTED 0x1 759 #define ID_AA64ISAR1_APA_ARCH_EPAC 0x2 760 #define ID_AA64ISAR1_APA_ARCH_EPAC2 0x3 761 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC 0x4 762 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB 0x5 763 #define ID_AA64ISAR1_API_NI 0x0 764 #define ID_AA64ISAR1_API_IMP_DEF 0x1 765 #define ID_AA64ISAR1_API_IMP_DEF_EPAC 0x2 766 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2 0x3 767 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC 0x4 768 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB 0x5 769 #define ID_AA64ISAR1_GPA_NI 0x0 770 #define ID_AA64ISAR1_GPA_ARCHITECTED 0x1 771 #define ID_AA64ISAR1_GPI_NI 0x0 772 #define ID_AA64ISAR1_GPI_IMP_DEF 0x1 773 774 /* id_aa64pfr0 */ 775 #define ID_AA64PFR0_CSV3_SHIFT 60 776 #define ID_AA64PFR0_CSV2_SHIFT 56 777 #define ID_AA64PFR0_DIT_SHIFT 48 778 #define ID_AA64PFR0_AMU_SHIFT 44 779 #define ID_AA64PFR0_MPAM_SHIFT 40 780 #define ID_AA64PFR0_SEL2_SHIFT 36 781 #define ID_AA64PFR0_SVE_SHIFT 32 782 #define ID_AA64PFR0_RAS_SHIFT 28 783 #define ID_AA64PFR0_GIC_SHIFT 24 784 #define ID_AA64PFR0_ASIMD_SHIFT 20 785 #define ID_AA64PFR0_FP_SHIFT 16 786 #define ID_AA64PFR0_EL3_SHIFT 12 787 #define ID_AA64PFR0_EL2_SHIFT 8 788 #define ID_AA64PFR0_EL1_SHIFT 4 789 #define ID_AA64PFR0_EL0_SHIFT 0 790 791 #define ID_AA64PFR0_AMU 0x1 792 #define ID_AA64PFR0_SVE 0x1 793 #define ID_AA64PFR0_RAS_V1 0x1 794 #define ID_AA64PFR0_RAS_V1P1 0x2 795 #define ID_AA64PFR0_FP_NI 0xf 796 #define ID_AA64PFR0_FP_SUPPORTED 0x0 797 #define ID_AA64PFR0_ASIMD_NI 0xf 798 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 799 #define ID_AA64PFR0_ELx_64BIT_ONLY 0x1 800 #define ID_AA64PFR0_ELx_32BIT_64BIT 0x2 801 802 /* id_aa64pfr1 */ 803 #define ID_AA64PFR1_MPAMFRAC_SHIFT 16 804 #define ID_AA64PFR1_RASFRAC_SHIFT 12 805 #define ID_AA64PFR1_MTE_SHIFT 8 806 #define ID_AA64PFR1_SSBS_SHIFT 4 807 #define ID_AA64PFR1_BT_SHIFT 0 808 809 #define ID_AA64PFR1_SSBS_PSTATE_NI 0 810 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 811 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 812 #define ID_AA64PFR1_BT_BTI 0x1 813 814 #define ID_AA64PFR1_MTE_NI 0x0 815 #define ID_AA64PFR1_MTE_EL0 0x1 816 #define ID_AA64PFR1_MTE 0x2 817 #define ID_AA64PFR1_MTE_ASYMM 0x3 818 819 /* id_aa64zfr0 */ 820 #define ID_AA64ZFR0_F64MM_SHIFT 56 821 #define ID_AA64ZFR0_F32MM_SHIFT 52 822 #define ID_AA64ZFR0_I8MM_SHIFT 44 823 #define ID_AA64ZFR0_SM4_SHIFT 40 824 #define ID_AA64ZFR0_SHA3_SHIFT 32 825 #define ID_AA64ZFR0_BF16_SHIFT 20 826 #define ID_AA64ZFR0_BITPERM_SHIFT 16 827 #define ID_AA64ZFR0_AES_SHIFT 4 828 #define ID_AA64ZFR0_SVEVER_SHIFT 0 829 830 #define ID_AA64ZFR0_F64MM 0x1 831 #define ID_AA64ZFR0_F32MM 0x1 832 #define ID_AA64ZFR0_I8MM 0x1 833 #define ID_AA64ZFR0_BF16 0x1 834 #define ID_AA64ZFR0_SM4 0x1 835 #define ID_AA64ZFR0_SHA3 0x1 836 #define ID_AA64ZFR0_BITPERM 0x1 837 #define ID_AA64ZFR0_AES 0x1 838 #define ID_AA64ZFR0_AES_PMULL 0x2 839 #define ID_AA64ZFR0_SVEVER_SVE2 0x1 840 841 /* id_aa64mmfr0 */ 842 #define ID_AA64MMFR0_ECV_SHIFT 60 843 #define ID_AA64MMFR0_FGT_SHIFT 56 844 #define ID_AA64MMFR0_EXS_SHIFT 44 845 #define ID_AA64MMFR0_TGRAN4_2_SHIFT 40 846 #define ID_AA64MMFR0_TGRAN64_2_SHIFT 36 847 #define ID_AA64MMFR0_TGRAN16_2_SHIFT 32 848 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 849 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 850 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 851 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 852 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 853 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 854 #define ID_AA64MMFR0_ASID_SHIFT 4 855 #define ID_AA64MMFR0_PARANGE_SHIFT 0 856 857 #define ID_AA64MMFR0_ASID_8 0x0 858 #define ID_AA64MMFR0_ASID_16 0x2 859 860 #define ID_AA64MMFR0_TGRAN4_NI 0xf 861 #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0 862 #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7 863 #define ID_AA64MMFR0_TGRAN64_NI 0xf 864 #define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 0x0 865 #define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 0x7 866 #define ID_AA64MMFR0_TGRAN16_NI 0x0 867 #define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 0x1 868 #define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 0xf 869 870 #define ID_AA64MMFR0_PARANGE_32 0x0 871 #define ID_AA64MMFR0_PARANGE_36 0x1 872 #define ID_AA64MMFR0_PARANGE_40 0x2 873 #define ID_AA64MMFR0_PARANGE_42 0x3 874 #define ID_AA64MMFR0_PARANGE_44 0x4 875 #define ID_AA64MMFR0_PARANGE_48 0x5 876 #define ID_AA64MMFR0_PARANGE_52 0x6 877 878 #define ARM64_MIN_PARANGE_BITS 32 879 880 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0 881 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE 0x1 882 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN 0x2 883 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX 0x7 884 885 #ifdef CONFIG_ARM64_PA_BITS_52 886 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 887 #else 888 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48 889 #endif 890 891 /* id_aa64mmfr1 */ 892 #define ID_AA64MMFR1_ETS_SHIFT 36 893 #define ID_AA64MMFR1_TWED_SHIFT 32 894 #define ID_AA64MMFR1_XNX_SHIFT 28 895 #define ID_AA64MMFR1_SPECSEI_SHIFT 24 896 #define ID_AA64MMFR1_PAN_SHIFT 20 897 #define ID_AA64MMFR1_LOR_SHIFT 16 898 #define ID_AA64MMFR1_HPD_SHIFT 12 899 #define ID_AA64MMFR1_VHE_SHIFT 8 900 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 901 #define ID_AA64MMFR1_HADBS_SHIFT 0 902 903 #define ID_AA64MMFR1_VMIDBITS_8 0 904 #define ID_AA64MMFR1_VMIDBITS_16 2 905 906 /* id_aa64mmfr2 */ 907 #define ID_AA64MMFR2_E0PD_SHIFT 60 908 #define ID_AA64MMFR2_EVT_SHIFT 56 909 #define ID_AA64MMFR2_BBM_SHIFT 52 910 #define ID_AA64MMFR2_TTL_SHIFT 48 911 #define ID_AA64MMFR2_FWB_SHIFT 40 912 #define ID_AA64MMFR2_IDS_SHIFT 36 913 #define ID_AA64MMFR2_AT_SHIFT 32 914 #define ID_AA64MMFR2_ST_SHIFT 28 915 #define ID_AA64MMFR2_NV_SHIFT 24 916 #define ID_AA64MMFR2_CCIDX_SHIFT 20 917 #define ID_AA64MMFR2_LVA_SHIFT 16 918 #define ID_AA64MMFR2_IESB_SHIFT 12 919 #define ID_AA64MMFR2_LSM_SHIFT 8 920 #define ID_AA64MMFR2_UAO_SHIFT 4 921 #define ID_AA64MMFR2_CNP_SHIFT 0 922 923 /* id_aa64dfr0 */ 924 #define ID_AA64DFR0_MTPMU_SHIFT 48 925 #define ID_AA64DFR0_TRBE_SHIFT 44 926 #define ID_AA64DFR0_TRACE_FILT_SHIFT 40 927 #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 928 #define ID_AA64DFR0_PMSVER_SHIFT 32 929 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 930 #define ID_AA64DFR0_WRPS_SHIFT 20 931 #define ID_AA64DFR0_BRPS_SHIFT 12 932 #define ID_AA64DFR0_PMUVER_SHIFT 8 933 #define ID_AA64DFR0_TRACEVER_SHIFT 4 934 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 935 936 #define ID_AA64DFR0_PMUVER_8_0 0x1 937 #define ID_AA64DFR0_PMUVER_8_1 0x4 938 #define ID_AA64DFR0_PMUVER_8_4 0x5 939 #define ID_AA64DFR0_PMUVER_8_5 0x6 940 #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf 941 942 #define ID_AA64DFR0_PMSVER_8_2 0x1 943 #define ID_AA64DFR0_PMSVER_8_3 0x2 944 945 #define ID_DFR0_PERFMON_SHIFT 24 946 947 #define ID_DFR0_PERFMON_8_0 0x3 948 #define ID_DFR0_PERFMON_8_1 0x4 949 #define ID_DFR0_PERFMON_8_4 0x5 950 #define ID_DFR0_PERFMON_8_5 0x6 951 952 #define ID_ISAR4_SWP_FRAC_SHIFT 28 953 #define ID_ISAR4_PSR_M_SHIFT 24 954 #define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT 20 955 #define ID_ISAR4_BARRIER_SHIFT 16 956 #define ID_ISAR4_SMC_SHIFT 12 957 #define ID_ISAR4_WRITEBACK_SHIFT 8 958 #define ID_ISAR4_WITHSHIFTS_SHIFT 4 959 #define ID_ISAR4_UNPRIV_SHIFT 0 960 961 #define ID_DFR1_MTPMU_SHIFT 0 962 963 #define ID_ISAR0_DIVIDE_SHIFT 24 964 #define ID_ISAR0_DEBUG_SHIFT 20 965 #define ID_ISAR0_COPROC_SHIFT 16 966 #define ID_ISAR0_CMPBRANCH_SHIFT 12 967 #define ID_ISAR0_BITFIELD_SHIFT 8 968 #define ID_ISAR0_BITCOUNT_SHIFT 4 969 #define ID_ISAR0_SWAP_SHIFT 0 970 971 #define ID_ISAR5_RDM_SHIFT 24 972 #define ID_ISAR5_CRC32_SHIFT 16 973 #define ID_ISAR5_SHA2_SHIFT 12 974 #define ID_ISAR5_SHA1_SHIFT 8 975 #define ID_ISAR5_AES_SHIFT 4 976 #define ID_ISAR5_SEVL_SHIFT 0 977 978 #define ID_ISAR6_I8MM_SHIFT 24 979 #define ID_ISAR6_BF16_SHIFT 20 980 #define ID_ISAR6_SPECRES_SHIFT 16 981 #define ID_ISAR6_SB_SHIFT 12 982 #define ID_ISAR6_FHM_SHIFT 8 983 #define ID_ISAR6_DP_SHIFT 4 984 #define ID_ISAR6_JSCVT_SHIFT 0 985 986 #define ID_MMFR0_INNERSHR_SHIFT 28 987 #define ID_MMFR0_FCSE_SHIFT 24 988 #define ID_MMFR0_AUXREG_SHIFT 20 989 #define ID_MMFR0_TCM_SHIFT 16 990 #define ID_MMFR0_SHARELVL_SHIFT 12 991 #define ID_MMFR0_OUTERSHR_SHIFT 8 992 #define ID_MMFR0_PMSA_SHIFT 4 993 #define ID_MMFR0_VMSA_SHIFT 0 994 995 #define ID_MMFR4_EVT_SHIFT 28 996 #define ID_MMFR4_CCIDX_SHIFT 24 997 #define ID_MMFR4_LSM_SHIFT 20 998 #define ID_MMFR4_HPDS_SHIFT 16 999 #define ID_MMFR4_CNP_SHIFT 12 1000 #define ID_MMFR4_XNX_SHIFT 8 1001 #define ID_MMFR4_AC2_SHIFT 4 1002 #define ID_MMFR4_SPECSEI_SHIFT 0 1003 1004 #define ID_MMFR5_ETS_SHIFT 0 1005 1006 #define ID_PFR0_DIT_SHIFT 24 1007 #define ID_PFR0_CSV2_SHIFT 16 1008 #define ID_PFR0_STATE3_SHIFT 12 1009 #define ID_PFR0_STATE2_SHIFT 8 1010 #define ID_PFR0_STATE1_SHIFT 4 1011 #define ID_PFR0_STATE0_SHIFT 0 1012 1013 #define ID_DFR0_PERFMON_SHIFT 24 1014 #define ID_DFR0_MPROFDBG_SHIFT 20 1015 #define ID_DFR0_MMAPTRC_SHIFT 16 1016 #define ID_DFR0_COPTRC_SHIFT 12 1017 #define ID_DFR0_MMAPDBG_SHIFT 8 1018 #define ID_DFR0_COPSDBG_SHIFT 4 1019 #define ID_DFR0_COPDBG_SHIFT 0 1020 1021 #define ID_PFR2_SSBS_SHIFT 4 1022 #define ID_PFR2_CSV3_SHIFT 0 1023 1024 #define MVFR0_FPROUND_SHIFT 28 1025 #define MVFR0_FPSHVEC_SHIFT 24 1026 #define MVFR0_FPSQRT_SHIFT 20 1027 #define MVFR0_FPDIVIDE_SHIFT 16 1028 #define MVFR0_FPTRAP_SHIFT 12 1029 #define MVFR0_FPDP_SHIFT 8 1030 #define MVFR0_FPSP_SHIFT 4 1031 #define MVFR0_SIMD_SHIFT 0 1032 1033 #define MVFR1_SIMDFMAC_SHIFT 28 1034 #define MVFR1_FPHP_SHIFT 24 1035 #define MVFR1_SIMDHP_SHIFT 20 1036 #define MVFR1_SIMDSP_SHIFT 16 1037 #define MVFR1_SIMDINT_SHIFT 12 1038 #define MVFR1_SIMDLS_SHIFT 8 1039 #define MVFR1_FPDNAN_SHIFT 4 1040 #define MVFR1_FPFTZ_SHIFT 0 1041 1042 #define ID_PFR1_GIC_SHIFT 28 1043 #define ID_PFR1_VIRT_FRAC_SHIFT 24 1044 #define ID_PFR1_SEC_FRAC_SHIFT 20 1045 #define ID_PFR1_GENTIMER_SHIFT 16 1046 #define ID_PFR1_VIRTUALIZATION_SHIFT 12 1047 #define ID_PFR1_MPROGMOD_SHIFT 8 1048 #define ID_PFR1_SECURITY_SHIFT 4 1049 #define ID_PFR1_PROGMOD_SHIFT 0 1050 1051 #if defined(CONFIG_ARM64_4K_PAGES) 1052 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 1053 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 1054 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 1055 #define ID_AA64MMFR0_TGRAN_2_SHIFT ID_AA64MMFR0_TGRAN4_2_SHIFT 1056 #elif defined(CONFIG_ARM64_16K_PAGES) 1057 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 1058 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 1059 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 1060 #define ID_AA64MMFR0_TGRAN_2_SHIFT ID_AA64MMFR0_TGRAN16_2_SHIFT 1061 #elif defined(CONFIG_ARM64_64K_PAGES) 1062 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 1063 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 1064 #define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 1065 #define ID_AA64MMFR0_TGRAN_2_SHIFT ID_AA64MMFR0_TGRAN64_2_SHIFT 1066 #endif 1067 1068 #define MVFR2_FPMISC_SHIFT 4 1069 #define MVFR2_SIMDMISC_SHIFT 0 1070 1071 #define DCZID_DZP_SHIFT 4 1072 #define DCZID_BS_SHIFT 0 1073 1074 /* 1075 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which 1076 * are reserved by the SVE architecture for future expansion of the LEN 1077 * field, with compatible semantics. 1078 */ 1079 #define ZCR_ELx_LEN_SHIFT 0 1080 #define ZCR_ELx_LEN_SIZE 9 1081 #define ZCR_ELx_LEN_MASK 0x1ff 1082 1083 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ 1084 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ 1085 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) 1086 1087 /* TCR EL1 Bit Definitions */ 1088 #define SYS_TCR_EL1_TCMA1 (BIT(58)) 1089 #define SYS_TCR_EL1_TCMA0 (BIT(57)) 1090 1091 /* GCR_EL1 Definitions */ 1092 #define SYS_GCR_EL1_RRND (BIT(16)) 1093 #define SYS_GCR_EL1_EXCL_MASK 0xffffUL 1094 1095 #ifdef CONFIG_KASAN_HW_TAGS 1096 /* 1097 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it 1098 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF. 1099 */ 1100 #define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf) 1101 #define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf) 1102 #define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN) 1103 #define KERNEL_GCR_EL1_EXCL (SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL) 1104 #else 1105 #define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK 1106 #endif 1107 1108 #define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL) 1109 1110 /* RGSR_EL1 Definitions */ 1111 #define SYS_RGSR_EL1_TAG_MASK 0xfUL 1112 #define SYS_RGSR_EL1_SEED_SHIFT 8 1113 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL 1114 1115 /* GMID_EL1 field definitions */ 1116 #define SYS_GMID_EL1_BS_SHIFT 0 1117 #define SYS_GMID_EL1_BS_SIZE 4 1118 1119 /* TFSR{,E0}_EL1 bit definitions */ 1120 #define SYS_TFSR_EL1_TF0_SHIFT 0 1121 #define SYS_TFSR_EL1_TF1_SHIFT 1 1122 #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) 1123 #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) 1124 1125 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 1126 #define SYS_MPIDR_SAFE_VAL (BIT(31)) 1127 1128 #define TRFCR_ELx_TS_SHIFT 5 1129 #define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) 1130 #define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) 1131 #define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) 1132 #define TRFCR_EL2_CX BIT(3) 1133 #define TRFCR_ELx_ExTRE BIT(1) 1134 #define TRFCR_ELx_E0TRE BIT(0) 1135 1136 1137 /* GIC Hypervisor interface registers */ 1138 /* ICH_MISR_EL2 bit definitions */ 1139 #define ICH_MISR_EOI (1 << 0) 1140 #define ICH_MISR_U (1 << 1) 1141 1142 /* ICH_LR*_EL2 bit definitions */ 1143 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) 1144 1145 #define ICH_LR_EOI (1ULL << 41) 1146 #define ICH_LR_GROUP (1ULL << 60) 1147 #define ICH_LR_HW (1ULL << 61) 1148 #define ICH_LR_STATE (3ULL << 62) 1149 #define ICH_LR_PENDING_BIT (1ULL << 62) 1150 #define ICH_LR_ACTIVE_BIT (1ULL << 63) 1151 #define ICH_LR_PHYS_ID_SHIFT 32 1152 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) 1153 #define ICH_LR_PRIORITY_SHIFT 48 1154 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) 1155 1156 /* ICH_HCR_EL2 bit definitions */ 1157 #define ICH_HCR_EN (1 << 0) 1158 #define ICH_HCR_UIE (1 << 1) 1159 #define ICH_HCR_NPIE (1 << 3) 1160 #define ICH_HCR_TC (1 << 10) 1161 #define ICH_HCR_TALL0 (1 << 11) 1162 #define ICH_HCR_TALL1 (1 << 12) 1163 #define ICH_HCR_TDIR (1 << 14) 1164 #define ICH_HCR_EOIcount_SHIFT 27 1165 #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT) 1166 1167 /* ICH_VMCR_EL2 bit definitions */ 1168 #define ICH_VMCR_ACK_CTL_SHIFT 2 1169 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) 1170 #define ICH_VMCR_FIQ_EN_SHIFT 3 1171 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) 1172 #define ICH_VMCR_CBPR_SHIFT 4 1173 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) 1174 #define ICH_VMCR_EOIM_SHIFT 9 1175 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT) 1176 #define ICH_VMCR_BPR1_SHIFT 18 1177 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) 1178 #define ICH_VMCR_BPR0_SHIFT 21 1179 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) 1180 #define ICH_VMCR_PMR_SHIFT 24 1181 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) 1182 #define ICH_VMCR_ENG0_SHIFT 0 1183 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) 1184 #define ICH_VMCR_ENG1_SHIFT 1 1185 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT) 1186 1187 /* ICH_VTR_EL2 bit definitions */ 1188 #define ICH_VTR_PRI_BITS_SHIFT 29 1189 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT) 1190 #define ICH_VTR_ID_BITS_SHIFT 23 1191 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT) 1192 #define ICH_VTR_SEIS_SHIFT 22 1193 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT) 1194 #define ICH_VTR_A3V_SHIFT 21 1195 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT) 1196 #define ICH_VTR_TDS_SHIFT 19 1197 #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT) 1198 1199 #define ARM64_FEATURE_FIELD_BITS 4 1200 1201 /* Create a mask for the feature bits of the specified feature. */ 1202 #define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT)) 1203 1204 #ifdef __ASSEMBLY__ 1205 1206 .macro mrs_s, rt, sreg 1207 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt)) 1208 .endm 1209 1210 .macro msr_s, sreg, rt 1211 __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt)) 1212 .endm 1213 1214 #else 1215 1216 #include <linux/build_bug.h> 1217 #include <linux/types.h> 1218 #include <asm/alternative.h> 1219 1220 #define DEFINE_MRS_S \ 1221 __DEFINE_ASM_GPR_NUMS \ 1222 " .macro mrs_s, rt, sreg\n" \ 1223 __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \ 1224 " .endm\n" 1225 1226 #define DEFINE_MSR_S \ 1227 __DEFINE_ASM_GPR_NUMS \ 1228 " .macro msr_s, sreg, rt\n" \ 1229 __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \ 1230 " .endm\n" 1231 1232 #define UNDEFINE_MRS_S \ 1233 " .purgem mrs_s\n" 1234 1235 #define UNDEFINE_MSR_S \ 1236 " .purgem msr_s\n" 1237 1238 #define __mrs_s(v, r) \ 1239 DEFINE_MRS_S \ 1240 " mrs_s " v ", " __stringify(r) "\n" \ 1241 UNDEFINE_MRS_S 1242 1243 #define __msr_s(r, v) \ 1244 DEFINE_MSR_S \ 1245 " msr_s " __stringify(r) ", " v "\n" \ 1246 UNDEFINE_MSR_S 1247 1248 /* 1249 * Unlike read_cpuid, calls to read_sysreg are never expected to be 1250 * optimized away or replaced with synthetic values. 1251 */ 1252 #define read_sysreg(r) ({ \ 1253 u64 __val; \ 1254 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 1255 __val; \ 1256 }) 1257 1258 /* 1259 * The "Z" constraint normally means a zero immediate, but when combined with 1260 * the "%x0" template means XZR. 1261 */ 1262 #define write_sysreg(v, r) do { \ 1263 u64 __val = (u64)(v); \ 1264 asm volatile("msr " __stringify(r) ", %x0" \ 1265 : : "rZ" (__val)); \ 1266 } while (0) 1267 1268 /* 1269 * For registers without architectural names, or simply unsupported by 1270 * GAS. 1271 */ 1272 #define read_sysreg_s(r) ({ \ 1273 u64 __val; \ 1274 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ 1275 __val; \ 1276 }) 1277 1278 #define write_sysreg_s(v, r) do { \ 1279 u64 __val = (u64)(v); \ 1280 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ 1281 } while (0) 1282 1283 /* 1284 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 1285 * set mask are set. Other bits are left as-is. 1286 */ 1287 #define sysreg_clear_set(sysreg, clear, set) do { \ 1288 u64 __scs_val = read_sysreg(sysreg); \ 1289 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1290 if (__scs_new != __scs_val) \ 1291 write_sysreg(__scs_new, sysreg); \ 1292 } while (0) 1293 1294 #define sysreg_clear_set_s(sysreg, clear, set) do { \ 1295 u64 __scs_val = read_sysreg_s(sysreg); \ 1296 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1297 if (__scs_new != __scs_val) \ 1298 write_sysreg_s(__scs_new, sysreg); \ 1299 } while (0) 1300 1301 #define read_sysreg_par() ({ \ 1302 u64 par; \ 1303 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1304 par = read_sysreg(par_el1); \ 1305 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1306 par; \ 1307 }) 1308 1309 #endif 1310 1311 #endif /* __ASM_SYSREG_H */ 1312