1 /* 2 * Copyright (C) 2016 - ARM Ltd 3 * 4 * stage2 page table helpers 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef __ARM64_S2_PGTABLE_H_ 20 #define __ARM64_S2_PGTABLE_H_ 21 22 #include <asm/pgtable.h> 23 24 /* 25 * The hardware supports concatenation of up to 16 tables at stage2 entry level 26 * and we use the feature whenever possible. 27 * 28 * Now, the minimum number of bits resolved at any level is (PAGE_SHIFT - 3). 29 * On arm64, the smallest PAGE_SIZE supported is 4k, which means 30 * (PAGE_SHIFT - 3) > 4 holds for all page sizes. 31 * This implies, the total number of page table levels at stage2 expected 32 * by the hardware is actually the number of levels required for (KVM_PHYS_SHIFT - 4) 33 * in normal translations(e.g, stage1), since we cannot have another level in 34 * the range (KVM_PHYS_SHIFT, KVM_PHYS_SHIFT - 4). 35 */ 36 #define STAGE2_PGTABLE_LEVELS ARM64_HW_PGTABLE_LEVELS(KVM_PHYS_SHIFT - 4) 37 38 /* 39 * With all the supported VA_BITs and 40bit guest IPA, the following condition 40 * is always true: 41 * 42 * STAGE2_PGTABLE_LEVELS <= CONFIG_PGTABLE_LEVELS 43 * 44 * We base our stage-2 page table walker helpers on this assumption and 45 * fall back to using the host version of the helper wherever possible. 46 * i.e, if a particular level is not folded (e.g, PUD) at stage2, we fall back 47 * to using the host version, since it is guaranteed it is not folded at host. 48 * 49 * If the condition breaks in the future, we can rearrange the host level 50 * definitions and reuse them for stage2. Till then... 51 */ 52 #if STAGE2_PGTABLE_LEVELS > CONFIG_PGTABLE_LEVELS 53 #error "Unsupported combination of guest IPA and host VA_BITS." 54 #endif 55 56 /* S2_PGDIR_SHIFT is the size mapped by top-level stage2 entry */ 57 #define S2_PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - STAGE2_PGTABLE_LEVELS) 58 #define S2_PGDIR_SIZE (1UL << S2_PGDIR_SHIFT) 59 #define S2_PGDIR_MASK (~(S2_PGDIR_SIZE - 1)) 60 61 /* 62 * The number of PTRS across all concatenated stage2 tables given by the 63 * number of bits resolved at the initial level. 64 */ 65 #define PTRS_PER_S2_PGD (1 << (KVM_PHYS_SHIFT - S2_PGDIR_SHIFT)) 66 67 /* 68 * kvm_mmmu_cache_min_pages() is the number of pages required to install 69 * a stage-2 translation. We pre-allocate the entry level page table at 70 * the VM creation. 71 */ 72 #define kvm_mmu_cache_min_pages(kvm) (STAGE2_PGTABLE_LEVELS - 1) 73 74 75 #if STAGE2_PGTABLE_LEVELS > 3 76 77 #define S2_PUD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(1) 78 #define S2_PUD_SIZE (1UL << S2_PUD_SHIFT) 79 #define S2_PUD_MASK (~(S2_PUD_SIZE - 1)) 80 81 #define stage2_pgd_none(kvm, pgd) pgd_none(pgd) 82 #define stage2_pgd_clear(kvm, pgd) pgd_clear(pgd) 83 #define stage2_pgd_present(kvm, pgd) pgd_present(pgd) 84 #define stage2_pgd_populate(kvm, pgd, pud) pgd_populate(NULL, pgd, pud) 85 #define stage2_pud_offset(kvm, pgd, address) pud_offset(pgd, address) 86 #define stage2_pud_free(kvm, pud) pud_free(NULL, pud) 87 88 #define stage2_pud_table_empty(kvm, pudp) kvm_page_empty(pudp) 89 90 static inline phys_addr_t 91 stage2_pud_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) 92 { 93 phys_addr_t boundary = (addr + S2_PUD_SIZE) & S2_PUD_MASK; 94 95 return (boundary - 1 < end - 1) ? boundary : end; 96 } 97 98 #endif /* STAGE2_PGTABLE_LEVELS > 3 */ 99 100 101 #if STAGE2_PGTABLE_LEVELS > 2 102 103 #define S2_PMD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(2) 104 #define S2_PMD_SIZE (1UL << S2_PMD_SHIFT) 105 #define S2_PMD_MASK (~(S2_PMD_SIZE - 1)) 106 107 #define stage2_pud_none(kvm, pud) pud_none(pud) 108 #define stage2_pud_clear(kvm, pud) pud_clear(pud) 109 #define stage2_pud_present(kvm, pud) pud_present(pud) 110 #define stage2_pud_populate(kvm, pud, pmd) pud_populate(NULL, pud, pmd) 111 #define stage2_pmd_offset(kvm, pud, address) pmd_offset(pud, address) 112 #define stage2_pmd_free(kvm, pmd) pmd_free(NULL, pmd) 113 114 #define stage2_pud_huge(kvm, pud) pud_huge(pud) 115 #define stage2_pmd_table_empty(kvm, pmdp) kvm_page_empty(pmdp) 116 117 static inline phys_addr_t 118 stage2_pmd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) 119 { 120 phys_addr_t boundary = (addr + S2_PMD_SIZE) & S2_PMD_MASK; 121 122 return (boundary - 1 < end - 1) ? boundary : end; 123 } 124 125 #endif /* STAGE2_PGTABLE_LEVELS > 2 */ 126 127 #define stage2_pte_table_empty(kvm, ptep) kvm_page_empty(ptep) 128 129 #if STAGE2_PGTABLE_LEVELS == 2 130 #include <asm/stage2_pgtable-nopmd.h> 131 #elif STAGE2_PGTABLE_LEVELS == 3 132 #include <asm/stage2_pgtable-nopud.h> 133 #endif 134 135 #define stage2_pgd_size(kvm) (PTRS_PER_S2_PGD * sizeof(pgd_t)) 136 137 #define stage2_pgd_index(kvm, addr) \ 138 (((addr) >> S2_PGDIR_SHIFT) & (PTRS_PER_S2_PGD - 1)) 139 140 static inline phys_addr_t 141 stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) 142 { 143 phys_addr_t boundary = (addr + S2_PGDIR_SIZE) & S2_PGDIR_MASK; 144 145 return (boundary - 1 < end - 1) ? boundary : end; 146 } 147 148 #endif /* __ARM64_S2_PGTABLE_H_ */ 149