1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2c0ef6326SSuzuki K Poulose /* 3c0ef6326SSuzuki K Poulose * Copyright (C) 2016 - ARM Ltd 4c0ef6326SSuzuki K Poulose * 5c0ef6326SSuzuki K Poulose * stage2 page table helpers 6c0ef6326SSuzuki K Poulose */ 7c0ef6326SSuzuki K Poulose 8c0ef6326SSuzuki K Poulose #ifndef __ARM64_S2_PGTABLE_H_ 9c0ef6326SSuzuki K Poulose #define __ARM64_S2_PGTABLE_H_ 10c0ef6326SSuzuki K Poulose 11ca5999fdSMike Rapoport #include <linux/pgtable.h> 12c0ef6326SSuzuki K Poulose 13c0ef6326SSuzuki K Poulose /* 146992195cSChristoffer Dall * The hardware supports concatenation of up to 16 tables at stage2 entry 156992195cSChristoffer Dall * level and we use the feature whenever possible, which means we resolve 4 166992195cSChristoffer Dall * additional bits of address at the entry level. 17da04fa04SSuzuki K Poulose * 186992195cSChristoffer Dall * This implies, the total number of page table levels required for 196992195cSChristoffer Dall * IPA_SHIFT at stage2 expected by the hardware can be calculated using 206992195cSChristoffer Dall * the same logic used for the (non-collapsable) stage1 page tables but for 216992195cSChristoffer Dall * (IPA_SHIFT - 4). 22c0ef6326SSuzuki K Poulose */ 2361fa5a86SSuzuki K Poulose #define stage2_pgtable_levels(ipa) ARM64_HW_PGTABLE_LEVELS((ipa) - 4) 2413ac4bbcSSuzuki K Poulose #define kvm_stage2_levels(kvm) VTCR_EL2_LVLS(kvm->arch.vtcr) 25c0ef6326SSuzuki K Poulose 26da04fa04SSuzuki K Poulose /* 27e55cac5bSSuzuki K Poulose * kvm_mmmu_cache_min_pages() is the number of pages required to install 28e55cac5bSSuzuki K Poulose * a stage-2 translation. We pre-allocate the entry level page table at 29e55cac5bSSuzuki K Poulose * the VM creation. 30da04fa04SSuzuki K Poulose */ 3161fa5a86SSuzuki K Poulose #define kvm_mmu_cache_min_pages(kvm) (kvm_stage2_levels(kvm) - 1) 32da04fa04SSuzuki K Poulose 33c0ef6326SSuzuki K Poulose #endif /* __ARM64_S2_PGTABLE_H_ */ 34